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256 10 External Memory Interfaces IP User Guide

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Intel Stratix 10 External MemoryInterfaces IP User GuideUpdated for Intel Quartus Prime Design Suite: FeedbackUG-S10EMI | document on the web: PDF | HTMLContents1 Intel Stratix 10 EMIF IP Intel Stratix 10 EMIF IP Design Intel Stratix 10 EMIF IP Design Intel Stratix 10 EMIF IP Product Intel Stratix 10 EMIF Architecture: Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: Input DQS Clock Intel Stratix 10 EMIF Architecture: PHY Clock Intel Stratix 10 EMIF Architecture: PLL Reference Clock Intel Stratix 10 EMIF Architecture: Clock Phase Intel Stratix 10 EMIF Intel Stratix 10 EMIF DQS Intel Stratix 10 EMIF Intel Stratix 10 Calibration Stages ........................................ ...................... Intel Stratix 10 Calibration Stages Intel Stratix 10 Calibration Intel Stratix 10 Calibration Intel Stratix 10 EMIF IP Intel Stratix 10 Hard Memory Controller Rate Conversion Hardware Resource Sharing Among Multiple Intel Stratix 10 I/O SSM I/O Bank PLL Reference Clock Core Clock Network User-requested Reset in Intel Stratix 10 EMIF Intel Stratix 10 EMIF for Hard Processor Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP with Intel Stratix 10 EMIF Ping Pong Intel Stratix 10 Ping Pong PHY Feature Intel Stratix 10 Ping Pong PHY Intel Stratix 10 Ping Pong PHY Intel Stratix 10 Ping Pong PHY Using the Ping Pong Ping Pong PHY Simulation Example Intel Stratix 10 EMIF and 443 Intel Stratix 10 EMIF IP End-User Interface and Signal Intel Stratix 10 EMIF IP Interfaces for Intel Stratix 10 EMIF IP Interfaces for Intel Stratix 10 EMIF IP Interfaces for Intel Stratix 10 EMIF IP Interfaces for QDR II/II+/II+ Intel Stratix 10 EMIF IP Interfaces for Stratix 10 External Memory Interfaces IP User Intel Stratix 10 EMIF IP Interfaces for RLDRAM AFI AFI Clock and Reset AFI Address and Command AFI Write Data AFI Read Data AFI Calibration Status AFI Tracking Management AFI Shadow Register Management AFI Timing AFI Address and Command Timing AFI Write Sequence Timing AFI Read Sequence Timing AFI Calibration Status Timing Intel Stratix 10 Memory Mapped Register (MMR) ecc3: ECC Error and Interrupt ecc4: Status and Error ecc5: Address of Most Recent ecc6: Address of Most Recent Correction Command ecc7: Extension for Address of Most Recent ecc8: Extension for Address of Most Recent Correction Command Stratix 10 External Memory Interfaces IP User Guide34 Intel Stratix 10 EMIF Simulating Memory Simulation Simulation Calibration Abstract PHY Simulation Functional Simulation with Verilog Functional Simulation with Simulating the Example Intel Stratix 10 EMIF IP for Parameter Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: Mem Intel Stratix 10 EMIF IP DDR3 Parameters: FPGA Intel Stratix 10 EMIF IP DDR3 Parameters: Mem Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: Example Board Skew Equations for DDR3 Board Skew Pin and Resource Interface FPGA Pin Guidelines for Intel Stratix 10 EMIF DDR3 Board Design Terminations for DDR3 and DDR4 with Intel Stratix 10 Channel Signal Integrity Layout Design Layout Package 1986 Intel Stratix 10 EMIF IP for Parameter Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Mem Intel Stratix 10 EMIF IP DDR4 Parameters: FPGA Intel Stratix 10 EMIF IP DDR4 Parameters: Mem Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Example Board Skew Equations for DDR4 Board Skew Pin and Resource Interface FPGA Pin Guidelines for Intel Stratix 10 EMIF Stratix 10 External Memory Interfaces IP User Resource Sharing Guidelines (Multiple Interfaces)............................. ........... DDR4 Board Design Terminations for DDR3 and DDR4 with Intel Stratix 10 Channel Signal Integrity Layout Design Layout Package 2557 Intel Stratix 10 EMIF IP for QDR II/II+/II+ Parameter Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: FPGA Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Example Board Skew Equations for QDRII, QDRII+, and QDRII+ Xtreme Board Skew Pin and Resource Interface QDR II/II+/II+ Xtreme Board Design QDR II SRAM General Layout QDR II Layout QDR II SRAM Layout Package 2878 Intel Stratix 10 EMIF IP for Parameter Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: FPGA Intel Stratix 10 EMIF IP QDR-IV Parameters: Mem Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Example Board Skew Equations for QDR-IV Board Skew Pin and Resource Interface QDR-IV Board Design QDR-IV Layout General Layout QDR-IV Layout Package 3159 Intel Stratix 10 EMIF IP for RLDRAM Parameter Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Stratix 10 External Memory Interfaces IP User Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: FPGA Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Mem Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Example Board Skew Equations for RLDRAM 3 Board Skew Pin and Resource Interface RLDRAM 3 Board Design RLDRAM 3 General Layout RLDRAM 3 Layout Layout Package 34510 Intel Stratix 10 EMIF IP for Parameter Intel Stratix 10 EMIF IP LPDDR3 Parameters: Intel Stratix 10 EMIF IP LPDDR3 Parameters: Intel Stratix 10 EMIF IP LPDDR3 Parameters: Mem Intel Stratix 10 EMIF IP LPDDR3 Parameters: FPGA Intel Stratix 10 EMIF IP LPDDR3 Parameters: Mem Intel Stratix 10 EMIF IP LPDDR3 Parameters: Intel Stratix 10 EMIF IP LPDDR3 Parameters: Intel Stratix 10 EMIF IP LPDDR3 Parameters: Intel Stratix 10 EMIF IP LPDDR3 Parameters: Example Board Skew Equations for LPDDR3 Board Skew Pin and Resource Interface LPDDR3 Board Design Terminations for DDR3 and DDR4 with Intel Stratix 10 Channel Signal Integrity Layout Design Layout Package Intel Stratix 10 EMIF IP Timing Timing Closure ........................................ ........................................ ................. Timing Timing Report Optimizing Early I/O Timing Performing Early I/O Timing 40112 Optimizing Controller Interface Bank Management Data Improving Controller Stratix 10 External Memory Interfaces IP User Auto-Precharge Bank Command Queue Look-Ahead Additive Latency and Bank User-Controlled Frequency of Series of Reads or Data Starvation Command Intel Stratix 10 EMIF IP Interface Configuration Performance Interface Configuration Bottleneck and Efficiency Functional Issue Intel IP Memory Vendor Memory Transcript Window Modifying the Example Driver to Replicate the Timing Issue Evaluating FPGA Timing Evaluating External Memory Interface Timing Verifying Memory IP Using the Signal Tap II Logic Signals to Monitor with the Signal Tap II Logic Hardware Debugging Create a Simplified Design that Demonstrates the Same Measure Power Distribution Measure Signal Integrity and Setup and Hold Vary Operate at a Lower Determine Whether the Issue Exists in Previous Versions of Determine Whether the Issue Exists in the Current Version of Try A Different Try Other Debugging Catagorizing Hardware Signal Integrity Hardware and Calibration Debugging Intel Stratix 10 EMIF External Memory Interface Debug On-Chip Debug for Intel Stratix Configuring Your EMIF IP for Use with the Debug Example Tcl Script for Running the EMIF Debug Using the EMIF Debug Toolkit with Intel Stratix 10 HPS Intel Stratix 10 EMIF Debugging User Setup and 444ContentsIntel Stratix 10 External Memory Interfaces IP User On-Chip Debug Port for Intel Stratix 10 EMIF EMIF On-Chip Debug Access On-Die Termination Calibration ........................................ ....................... Eye Diagram ........................................ ........................................ ........ Driver Margining for Intel Stratix 10 EMIF Determining Traffic Generator Configuring the Traffic Generator Configurable Traffic Generator Configuration Running the Traffic Generator Understanding the Custom Traffic Generator User Applying the Traffic Generator Testing the EMIF Interface Using the Traffic Generator The Traffic Generator Calibration Adjustment Delay Step Sizes for Intel Stratix 10 Output and Strobe Enable Minimum and Maximum Phase 47314 Document Revision History for Intel Stratix 10 External Memory Interfaces IPUser Stratix 10 External Memory Interfaces IP User Guide81 Intel Stratix 10 EMIF IP IntroductionIntel's fast, efficient, and low-latency external memory interface (EMIF) intellectualproperty (IP) cores easily interface with today's higher speed memory can easily implement the EMIF IP core functions through the Intel Quartus Prime software. The Intel Quartus Prime software also provides external memorytoolkits that help you test the implementation of the IP in the EMIF IP provides the following components: A physical layer interface (PHY) which builds the data path and manages timingtransfers between the FPGA and the memory device. A memory controller which implements all the memory commands and protocol-level information on the maximum speeds supported by the external memory interfaceIP, refer to the External Memory Interface Spec Stratix 10 EMIF IP Protocol and Feature Support Supports DDR4, DDR3, DDR3L, and LPDDR3 protocols with hard memorycontroller and hard PHY. Supports QDR-IV, QDR II + Xtreme, QDR II +, and QDR II using soft memorycontroller and hard PHY. Supports RLDRAM 3 using third-party soft controller. Supports UDIMM, RDIMM, LRDIMM and SODIMM memory devices. Supports 3D Stacked Die for DDR4 devices. Supports up to 4 physical ranks. Supports Ping Pong PHY mode, allowing two memory controllers to sharecommand, address, and control pins. Supports error correction code (ECC) for both hard memory controller and softmemory Links External Memory Interfaces Support Center Intel Stratix 10 General Purpose I/O User GuideUG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of Intel Stratix 10 EMIF IP Design FlowIntel recommends creating an example top-level file with the desired pin outs and allinterface IPs instantiated. This enables the Intel Quartus Prime software to validatethe design and resource allocation before PCB and schematic sign following figure shows the design flow to provide the fastest out-of-the-boxexperience with the EMIF IP Design FlowSelect a Memory Device and FPGAPlan Pin/FPGA Resource UsageInitiate Board LayoutParameterize and Generate EMIF IPCompile Design and Verify TimingVerify Functionality on BoardDetermine Memory RequirementsPerform Board SimulationUpdate Board ParametersVerify IP ParametersDesign CompletedDebugIs Timing Passing?Is Design Working?Perform Functional SimulationYesNoNoYesRelated Links Introduction to Intel FPGA IP Cores Generating a Combined Simulator Setup Script Project Management Best Practices1 Intel Stratix 10 EMIF IP IntroductionUG-S10EMI | Stratix 10 External Memory Interfaces IP User Intel Stratix 10 EMIF IP Design ChecklistRefer to the following checklist as a quick reference for information about each step inthe EMIF design Design ChecklistDesign StepDescriptionResourcesSelect an FPGANot all Intel FPGAs support all memory typesand configurations. To help with the FPGAselection process, refer to these resources. Intel FPGA Product Selector External Memory Interface DeviceSelector External Memory Interface SpecEstimatorParameterize the IPCorrect IP parameterization is important forgood EMIF IP operation. These resources definethe memory parameters during IP generation. DDR3 Parameter Descriptions DDR4 Parameter Descriptions QDR II/II+/II+ Xtreme ParameterDescriptions QDR-IV Parameter Descriptions RLDRAM 3 Parameter Descriptions LPDDR3 Parameter DescriptionsGenerate initial IP andexample designAfter you have parameterized the EMIF IP, youcan generate the IP, along with an optionalexample design. Refer to the Quick-Start Guidefor a walkthrough of this process. Design Example Quick Start Guide Design Example DescriptionPerform functionalsimulationSimulation of the EMIF design helps todetermine correct operation. These resourcesexplain how to perform simulation and whatdifferences exist between simulation andhardware implementation. Design Example Quick Start Guide Simulating Memory IPMake pin assigmentsFor guidance on pin placement, refer to theseresources. DDR3 Parameter Descriptions DDR4 Parameter Descriptions QDR II/II+/II+ Xtreme ParameterDescriptions QDR-IV Parameter Descriptions RLDRAM 3 Parameter Descriptions LPDDR3 Parameter DescriptionsPerform board simulationBoard simulation helps determine optimalsettings for signal integrity, drive strength, aswell as sufficient timing margins and eyeopenings. For guidance on board simulation,refer to these resources. DDR3 Board Design Guidelines DDR4 Board Design Guidelines QDR II/II+/II+ Xtreme Board DesignGuidelines QDR-IV Board Design Guidelines RLDRAM 3 Board Design Guidelines LPDDR3 Board Design Guidelines Board Skew Parameter ToolUpdate board parametersin the IPBoard simulation is important to determineoptimal settings for signal integrity, drivestrength, and sufficient timing margins and eyeopenings. For guidance on board simulationrefer to the mentioned resources. DDR3 Board Design Guidelines DDR4 Board Design Guidelines QDR II/II+/II+ Xtreme Board DesignGuidelines QDR-IV Board Design Guidelines RLDRAM 3 Board Design Guidelines LPDDR3 Board Design Guidelines Board Skew Parameter 1 Intel Stratix 10 EMIF IP IntroductionUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide11Design StepDescriptionResourcesVerify timing closureFor information regarding compilation, system-level timing closure and timing reports refer tothe Timing Closure section of this User Guide. Timing ClosureRun the design onhardwareFor instructions on how to program a FPGArefer to the Quick-Start Guide section of thisUser Guide. Design Example Quick Start GuideDebug issues withpreceeding stepsOperational problems can generally beattributed to one of the following: interfaceconfiguration, pin/resource planning, signalintegrity, or timing. These resources containinformation on typical debug procedures andavailable tools to help diagnose hardwareissues. Debugging External Memory Interfaces SupportCenter1 Intel Stratix 10 EMIF IP IntroductionUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide122 Intel Stratix 10 EMIF IP Product ArchitectureThis chapter describes the Intel Stratix 10 product Intel Stratix 10 EMIF Architecture: IntroductionThe Intel Stratix 10 EMIF architecture contains many new hardware features designedto meet the high-speed requirements of emerging memory protocols, while consumingthe smallest amount of core logic area and following are key hardware features of the Intel Stratix 10 EMIF architecture:Hard SequencerThe sequencer employs a hard Nios II processor, and can perform memory calibrationfor a wide range of protocols. You can share the sequencer among multiple memoryinterfaces of the same or different : You cannot use the hard Nios II processor for any user applications after calibration PHYThe hard PHY in Intel Stratix 10 devices can interface with external memories runningat speeds of up to GHz. The PHY circuitry is hardened in the silicon, whichsimplifies the challenges of achieving timing closure and minimal power Memory ControllerThe hard memory controller reduces latency and minimizes core logic consumption inthe external memory interface. The hard memory controller supports the DDR3,DDR4, and LPDDR3 memory ModeProtocols that use a hard controller (DDR4, DDR3, LPDDR3, and RLDRAM 3), provide aPHY-only option, which generates only the PHY and sequencer, but not the PHY-only mode provides a mechanism by which to integrate your own customsoft PHY Clock TreeDedicated high speed PHY clock networks clock the I/O buffers in Intel Stratix 10 EMIFIP. The PHY clock trees exhibit low jitter and low duty cycle distortion, maximizing thedata valid | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008RegisteredAutomatic Clock Phase AlignmentAutomatic clock phase alignment circuitry dynamically adjusts the clock phase of coreclock networks to match the clock phase of the PHY clock networks. The clock phasealignment circuitry minimizes clock skew that can complicate timing closure intransfers between the FPGA core and the SharingThe Intel Stratix 10 architecture simplifies resource sharing between memoryinterfaces. Resources such as the OCT calibration block, PLL reference clock pin, andcore clock can be shared. The hard Nios processor in the I/O subsystem manager (I/OSSM) must be shared across all interfaces in a Links External Memory Interface Spec Estimator Introduction to Intel FPGA IP Cores Generating a Combined Simulator Setup Script Project Management Best Intel Stratix 10 EMIF Architecture: I/O SubsystemDepending on the Intel Stratix 10 device, the I/O subsystem consists of either two orthree columns inside the 10 I/O SubsystemCore FabricI/O ColumnTransceivers (if applicable)The I/O subsystem provides the following features: General-purpose I/O registers and I/O buffers On-chip termination control (OCT) I/O PLLs for external memory interfaces and user logic Low-voltage differential signaling (LVDS) External memory interface components, as follows: Hard memory controller Hard PHY Hard Nios processor and calibration logic DLL2 Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Intel Stratix 10 EMIF Architecture: I/O ColumnMost Intel Stratix 10 devices have two I/O columns (some can have three), whichcontain the hardware related to external memory I/O column contains the following major parts: A hardened Nios processor with dedicated memory. This Nios block is referred toas the I/O SSM. Up to 13 I/O banks. Each I/O bank contains the hardware necessary for anexternal memory Column2L2K2J2I2H2G2F2A3H3G3F3E3D3C3B3ATr ansceiver BlockTransceiver BlockTransceiverBlock I/OColumnBankControl I/OColumnIndividualI/O BanksLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairSERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPAI/O LaneLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairSERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPAI/O LaneI/O CenterI/O PLLHard Memory ControllerandPHY SequencerI/O DLLI/O CLKOCTVRLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairSERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPAI/O LaneLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairLVDS I/O Buffer PairSERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPASERDES & DPAI/O Intel Stratix 10 EMIF Architecture: I/O SSMEach column includes one I/O subsystem manager (I/O SSM), which contains ahardened Nios II processor with dedicated memory. The I/O SSM is responsible forcalibration of all the EMIFs in the I/O SSM includes dedicated memory which stores both the calibration algorithmand calibration run-time data. The hardened Nios II processor and the dedicatedmemory can be used only by an external memory interface, and cannot be employedfor any other use. The I/O SSM can interface with soft logic, such as the debug toolkit,via an Avalon-MM I/O SSM is clocked by an on-die oscillator, and therefore does not consume a Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Intel Stratix 10 EMIF Architecture: I/O BankA single I/O bank contains all the hardware needed to build an external memoryinterface. Each I/O column contains up to 13 I/O banks; the exact number of banksdepends on device size and pin package. You can make a wider interface byconnecting multiple banks I/O bank resides in an I/O column, and contains the following components: Hard memory controller Sequencer components PLL and PHY clock trees DLL Input DQS clock trees 48 pins, organized into four I/O lanes of 12 pins eachFigure Bank Architecture in Intel Stratix 10 Devices Memory Controller Sequencer PLL Clock Phase Alignment I/O Lane 3 Output Path Input Path I/O Lane 2 Output Path Input Path I/O Lane 1 Output Path Input Path I/O Lane 0 Output Path Input Path to / from bank aboveto / from bank below to / from FPGA coreI/O BankI/O Bank UsageThe pins in an I/O bank can serve as address and command pins, data pins, or clockand strobe pins for an external memory interface. You can implement a narrowinterface, such as a DDR3 or DDR4 x8 interface, with only a single I/O bank. A widerinterface, such as x72 or x144, can be implemented by configuring multiple adjacentbanks in a multi-bank interface. Any pins in a bank which are not used by the externalmemory interface remain available for use as general purpose I/O pins (of the samevoltage standard).Every I/O bank includes a hard memory controller which you can configure for DDR3,DDR4, or LPDDR3. In a multi-bank interface, only the controller of one bank is active;controllers in the remaining banks are turned off to conserve Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide16To use a multi-bank Intel Stratix 10 EMIF interface, you must observe the followingrules: Designate one bank as the address and command bank. The address and command bank must contain all the address and command pins. The locations of individual address and command pins within the address andcommand bank must adhere to the pin map defined in the pin table regardlessof whether you use the hard memory controller or not. If you do use the hard memory controller, the address and command bankcontains the active hard the I/O banks in a column are capable of functioning as the address and commandbank. However, for minimal latency, you should select the center-most bank of theinterface as the address and command Intel Stratix 10 EMIF Architecture: I/O LaneAn I/O bank contains 48 I/O pins, organized into four I/O lanes of 12 pins I/O lane can implement one x8/x9 read capture group (DQS group), with twopins functioning as the read capture clock/strobe pair (DQS/DQS#), and up to 10 pinsfunctioning as data pins (DQ and DM pins). To implement x18 and x36 groups, youcan use multiple lanes within the same is also possible to implement a pair of x4 groups in a lane. In this case, four pinsfunction as clock/strobe pair, and 8 pins function as data pins. DM is not available forx4 groups. There must be an even number of x4 groups for each x4 groups, DQS0 and DQS1 must be placed in the same I/O lane as a , DQS2 and DQS3 must be paired. In general, DQS(x) and DQS(x+1) must bepaired in the same I/O Used Per GroupGroup SizeNumber of Lanes UsedMaximum Number of Data Pins perGroupx8 / x9110x18222x36446pair of x414 per group, 8 per lane2 Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide17Figure GroupMemoryControllerClock PhaseAlignmentSequencerPLLI/O Lane 3Output PathInput PathI/O Lane 2Output PathInput PathI/O Lane 1Output PathInput PathI/O Lane 0Output PathInput PathX4 Groups 6 and 7X4 Groups 4 and 5X4 Groups 2 and 3X4 Groups 0 and 1Figure GroupMemoryControllerClock PhaseAlignmentSequencerPLLI/O Lane 3Output PathInput PathI/O Lane 2Output PathInput PathI/O Lane 1Output PathInput PathI/O Lane 0Output PathInput PathX8 Group 3X8 Group 2X8 Group 1X8 Group 02 Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide18Figure Group Memory Controller Sequencer PLL Clock Phase Alignment I/O Lane 3 Output Path Input Path I/O Lane 2 Output Path Input Path I/O Lane 1 Output Path Input Path I/O Lane 0 Output Path Input Path X18 Group 0X18 Group 1Figure Group Memory Controller Sequencer PLL Clock Phase Alignment I/O Lane 3 Output Path Input Path I/O Lane 2 Output Path Input Path I/O Lane 1 Output Path Input Path I/O Lane 0 Output Path Input Path X36 Group Intel Stratix 10 EMIF Architecture: Input DQS Clock TreeThe input DQS clock tree is a balanced clock network that distributes the read captureclock and strobe from the external memory device to the read capture registers insidethe can configure an input DQS clock tree in x4 mode, x8/x9 mode, x18 mode, or Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide19Within every bank, only certain physical pins at specific locations can drive the inputDQS clock trees. The pin locations that can drive the input DQS clock trees vary,depending on the size of the Usable as Read Capture Clock / Strobe PairGroup SizeIndex of Lanes Spannedby Clock TreeIn-Bank Index of Pins Usable as Read Capture Clock /Strobe PairPositive LegNegative Legx40A45x40B89x41A1617x41B2021x42A2829x 42B3233x43A4041x43B4445x8 / x9045x8 / x911617x8 / x922829x8 / x934041x180, 11213x182, 33637x360, 1, 2, Intel Stratix 10 EMIF Architecture: PHY Clock TreeDedicated high-speed clock networks drive I/Os in Intel Stratix 10 EMIF. Each PHYclock network spans only one relatively short span of the PHY clock trees results in low jitter and low duty-cycledistortion, maximizing the data valid PHY clock tree in Intel Stratix 10 devices can run as fast as GHz. All IntelStratix 10 external memory interfaces use the PHY clock Intel Stratix 10 EMIF Architecture: PLL Reference Clock NetworksEach I/O bank includes a PLL that can drive the PHY clock trees of that bank, throughdedicated connections. In addition to supporting EMIF-specific functions, such PLLscan also serve as general-purpose PLLs for user Stratix 10 external memory interfaces that span multiple banks use the PLL ineach bank. The Intel Stratix 10 architecture allows for relatively short PHY clocknetworks, reducing jitter and duty-cycle Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide20The following mechanisms ensure that the clock outputs of individual PLLs in a multi-bank interface remain in phase: A single PLL reference clock source feeds all PLLs. The reference clock signalreaches the PLLs by a balanced PLL reference clock tree. The Intel Quartus Primesoftware automatically configures the PLL reference clock tree so that it spans thecorrect number of banks. The EMIF IP sets the PLL M and N values appropriately to maintain synchronizationamong the clock dividers across the PLLs. This requirement restricts the legal PLLreference clock frequencies for a given memory interface frequency and clock Stratix 10 EMIF IP parameter editor automatically calculates and displays theset of legal PLL reference clock frequencies. If you plan to use an on-boardoscillator, you must ensure that its frequency matches the PLL reference clockfrequency that you select from the displayed list. The correct M and N values ofthe PLLs are set automatically based on the PLL reference clock frequency thatyou : The PLL reference clock pin may be placed in the address and command I/O bank or ina data I/O bank, there is no implication on timing. However, for debug flexibility, it isrecommended to place the PLL reference clock in the address and command I/O Balanced Reference Clock TreeBalanced Reference Clock Network PLLPLLPLLPLLPHY clock treePHY clock treePHY clock treePHY clock treeI/O BankI/O BankI/O BankI/O BankI/O Columnref_clkRelated LinksMaximum Number of Interfaces on page Intel Stratix 10 EMIF Architecture: Clock Phase AlignmentIn Intel Stratix 10 external memory interfaces, a global clock network clocks registersinside the FPGA core, and the PHY clock network clocks registers inside the FPGAperiphery. Clock phase alignment circuitry employs negative feedback to dynamicallyadjust the phase of the core clock signal to match the phase of the PHY clock Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide21The clock phase alignment feature effectively eliminates the clock skew effect in alltransfers between the core and the periphery, facilitating timing closure. All Stratix 10external memory interfaces employ clock phase alignment Phase Alignment Illustration-+Clock Phase AlignmentPLLPHY Clock NetworkCore Clock NetworkFPGA CoreFPGA PeripherytpFigure of Clock Phase Intel Stratix 10 EMIF SequencerThe Intel Stratix 10 EMIF sequencer is fully hardened in silicon, with executable codeto handle protocols and topologies. Hardened RAM contains the calibration Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide22The Intel Stratix 10 EMIF sequencer is responsible for the following operations: Initializes memory devices. Calibrates the external memory interface. Governs the hand-off of control to the memory controller. Handles recalibration requests and debug requests. Handles all supported protocols and Stratix 10 EMIF Sequencer OperationDiscover EMIFs in columnInitialize external memoryCalibrate interfaceHand-offProcessed allinterfaces? Intel Stratix 10 EMIF DQS TrackingDQS tracking is enabled for QDR II / II+ / QDR II+ Xtreme, RLDRAM 3, and LPDDR3protocols. DQS tracking is not available for DDR3 and DDR4 Intel Stratix 10 EMIF CalibrationThe calibration process compensates for skews and delays in the external following effects can be compensated for by the calibration process: Timing and electrical constraints, such as setup/hold time and Vref variations. Circuit board and package factors, such as skew, fly-by effects, and manufacturingvariations. Environmental uncertainties, such as variations in voltage and temperature. The demanding effects of small margins associated with high-speed : The calibration process is intended to maximize margins for robust EMIF operation; itcannot compensate for an inadequate PCB Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Intel Stratix 10 Calibration StagesAt a high level, the calibration routine consists of address and command calibration,read calibration, and write stages of calibration vary, depending on the protocol of the external Stages by ProtocolStageDDR4DDR3LPDDR3RLDRAM 3QDR-IVQDR II/II+Address and commandLevelingYesYes DeskewYes Yes Yes ReadDQSenYesYesYesYesYesYesDeskewYesYesY esYesYesYesVREF-InYes Yes LFIFOYesYesYesYesYesYesWriteLevelingYesY esYesYesYes DeskewYesYesYesYesYesYesVREF-OutYes Intel Stratix 10 Calibration Stages DescriptionsThe various stages of calibration perform address and command calibration, readcalibration, and write and Command CalibrationThe goal of address and command calibration is to delay address and commandsignals as necessary to optimize the address and command window. This stage is notavailable for all protocols, and cannot compensate for an inefficient board and command calibration consists of the following parts: Leveling calibration Centers the CS# signal and the entire address andcommand bus, relative to the CK clock. This operation is available for DDR3 andDDR4 interfaces only. Deskew calibration Provides per-bit deskew for the address and command bus(except CS#), relative to the CK clock. This operation is available for DDR4 andQDR-IV interfaces Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide24Read CalibrationRead calibration consists of the following parts: DQSen calibration Calibrates the timing of the read capture clock gating andungating, so that the PHY can gate and ungate the read clock at precisely thecorrect time if too early or too late, data corruption can occur. The algorithm forthis stage varies, depending on the memory protocol. Deskew calibration Performs per-bit deskew of read data relative to the readstrobe or clock. VREF-In calibration Calibrates the VREF level at the FPGA. LFIFO calibration: Normalizes differences in read delays between groups due tofly-by, skews, and other variables and CalibrationWrite calibration consists of the following parts: Leveling calibration Aligns the write strobe and clock to the memory clock, tocompensate for skews, especially those associated with fly-by topology. Thealgorithm for this stage varies, depending on the memory protocol. Deskew calibration Performs per-bit deskew of write data relative to the writestrobe and clock. VREF-Out calibration Calibrates the VREF level at the memory Intel Stratix 10 Calibration AlgorithmsThe calibration algorithms sometimes vary, depending on the targeted and Command CalibrationAddress and command calibration consists of the following parts:2 Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide25 Leveling calibration (DDR3 and DDR4 only) Toggles the CS# and CAS# signalsto send read commands while keeping other address and command signalsconstant. The algorithm monitors for incoming DQS signals, and if the DQS signaltoggles, it indicates that the read commands have been accepted. The algorithmthen repeats using different delay values, to find the optimal window. Deskew calibration (DDR4, QDR-IV, and LPDDR3 only) (DDR4) Uses the DDR4 address and command parity feature. The FPGA sendsthe address and command parity bit, and the DDR4 memory device respondswith an alert signal if the parity bit is detected. The alert signal from thememory device tells the FPGA that the parity bit was calibration requires use of the PAR/ALERT# pins, so you should notomit these pins from your design. One limitation of deskew calibration is thatit cannot deskew ODT and CKE pins. (QDR-IV) Uses the QDR-IV loopback mode. The FPGA sends address andcommand signals, and the memory device sends back the address andcommand signals which it captures, via the read data pins. The returnedsignals indicate to the FPGA what the memory device has captured. Deskewcalibration can deskew all synchronous address and command signals. (LPDDR3) Uses the LPDDR3 CA training mode. The FPGA sends signals ontothe LPDDR3 CA bus, and the memory device sends back those signals that itcaptures, via the DQ pins. The returned signals indicate to the FPGA what thememory device has captured. Deskew calibration can deskew all signals on theCA bus. The remaining command signals (CS, CKE, and ODT) are calibratedbased on the average of the deskewed CA Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide26Read Calibration DQSen calibration (DDR3, DDR4, LPDDR3, RLDRAMx and QDRx) DQSencalibration occurs before Read deskew, therefore only a single DQ bit is required topass in order to achieve a successful read pass. (DDR3, DDR4,and LPDDR3) The DQSen calibration algorithm searches theDQS preamble using a hardware state machine. The algorithm sends manyback-to-back reads with a one clock cycle gap between. The hardware statemachine searches for the DQS gap while sweeping DQSen delay values. thealgorithm then increments the VFIFO value, and repeats the process until apattern is found. The process is then repeated for all other read DQS groups. (RLDRAMx and QDRx) The DQSen calibration algorithm does not use ahardware state machine; rather, it calibrates cycle-level delays using softwareand subcycle delays using DQS tracking hardware. The algorithm requiresgood data in memory, and therefore relies on guaranteed writes. (Writing aburst of 0s to one location, and a burst of 1s to another; back-to-back readsfrom these two locations are used for read calibration.)The algorithm enables DQS tracking to calibrate the phase component of DQSenable, and then issues a guaranteed write, followed by back-to-back algorithm sweeps DQSen values cycle by cycle until the read operationsucceeds. The process is then repeated for all other read groups. Deskew calibration Read deskew calibration is performed before write leveling,and must be performed at least twice: once before write calibration, using simpledata patterns from guaranteed writes, and again after write calibration, usingcomplex data deskew calibration algorithm performs a guaranteed write, and then sweepsdqs_in delay values from low to high, to find the right edge of the read algorithm then sweeps dq-in delay values low to high, to find the left edge ofthe read window. Updated dqs_in and dq_in delay values are then applied tocenter the read window. The algorithm then repeats the process for all data pins. Vref-In calibration Read Vref-In calibration begins by programming Vref-Inwith an arbitrary value. The algorithm then sweeps the Vref-In value from thestarting value to both ends, and measures the read window for each value. Thealgorithm selects the Vref-In value which provides the maximum read window. LFIFO calibration Read LFIFO calibration normalizes read delays between PHY must present all data to the controller as a single data bus. The LFIFOlatency should be large enough for the slowest read data group, and large enoughto allow proper synchronization across Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide27Write Calibration Leveling calibration Write leveling calibration aligns the write strobe and clock tothe memory clock, to compensate for skews. In general, leveling calibration tries avariety of delay values to determine the edges of the write window, and thenselects an appropriate value to center the window. The details of the algorithmvary, depending on the memory protocol. (DDRx, LPDDR3) Write leveling occurs before write deskew, therefore only onesuccessful DQ bit is required to register a pass. Write leveling staggers the DQbus to ensure that at least one DQ bit falls within the valid write window. (RLDRAMx) Optimizes for the CK versus DK relationship. (QDR-IV) Optimizes for the CK versus DK relationship. Is covered by addressand command deskew using the loopback mode. (QDR II/II+/Xtreme) The K clock is the only clock, therefore write leveling isnot required. Deskew calibration Performs per-bit deskew of write data relative to the writestrobe and clock. Write deskew calibration does not change dqs_out delays; thewrite clock is aligned to the CK clock during write leveling. VREF-Out calibration (DDR4) Calibrates the VREF level at the memory VREF-Out calibration algorithm is similar to the VREF-In calibration Intel Stratix 10 Calibration FlowchartThe following flowchart illustrates the Intel Stratix 10 calibration Flowchart2 Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Intel Stratix 10 EMIF IP Intel Stratix 10 Hard Memory Controller Rate Conversion FeatureThe hard memory controller's rate conversion feature allows the hard memorycontroller and PHY to run at half-rate, even though user logic is configured to run facilitate timing closure, you may choose to clock your core user logic at quarter-rate, resulting in easier timing closure at the expense of increased area and improve efficiency and help reduce overall latency, you can run the hard memorycontroller and PHY at half rate conversion feature converts traffic from the FPGA core to the hard memorycontroller from quarter-rate to half-rate, and traffic from the hard memory controllerto the FPGA core from half-rate to quarter-rate. From the perspective of user logicinside the FPGA core, the effect is the same as if the hard memory controller wererunning at rate conversion feature is enabled automatically during IP generation whenever allof the following conditions are met: The hard memory controller is in use. User logic runs at quarter-rate. The interface targets either an ES2 or production device. Running the hard memory controller at half-rate dpoes not exceed the fMaxspecification of the hard memory controller and hard the rate conversion feature is enabled, you should see the following infomessage displayed in the IP generation GUI:PHY and controller running at 2x the frequency of user logic forimproved Hardware Resource Sharing Among Multiple Intel Stratix 10EMIFsOften, it is necessary or desirable to share certain hardware resources I/O SSM SharingThe I/O SSM contains a hard Nios-II processor and dedicated memory storing thecalibration software code and a column contains multiple memory interfaces, the hard Nios-II processorcalibrates each interface serially. Interfaces placed within the same I/O column alwaysshare the same I/O SSM. The Intel Quartus Prime Fitter handles I/O SSM Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User I/O Bank SharingData lanes from multiple compatible interfaces can share a physical I/O bank toachieve a more compact pin placement. To share an I/O bank, interfaces must use thesame memory protocol, rate, frequency, I/O standard, and PLL reference clock for Sharing I/O Banks A bank cannot serve as the address and command bank for more than oneinterface. This means that lanes which implement address and command pins fordifferent interfaces cannot be allocated to the same physical : An exception to the above rule exists when two interfaces are configured ina Ping-Pong PHY fashion. In such a configuration, two interfaces share thesame set of address and command pins, effectively meaning that they sharethe same address and command tile. Pins within a lane cannot be shared by multiple memory interfaces. Pins that are not used by EMIF IP can serve as general-purpose I/Os of compatiblevoltage and termination settings. You can configure a bank as LVDS or as EMIF, but not both at the same time. Interfaces that share banks must reside at adjacent bank following diagram illustrates two x16 interfaces sharing an I/O bank. The twointerfaces share the same clock phase alignment block, so that one core clock signalcan interact with both interfaces. Without sharing, the two interfaces would occupy atotal of four physical banks instead of Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide30Figure Bank SharingI/O Lane 2I/O Lane 1I/O Lane 0I/O Lane 3I/O Lane 0I/O Lane 3I/O Lane 2I/O Lane 1I/O Lane 0MemoryControllerClock PhaseAlignmentSequencerPLLI/O Lane 3Output PathInput PathOutput PathInput PathOutput PathInput PathOutput PathInput PathMemoryControllerClock PhaseAlignmentSequencerPLLOutput PathInput PathOutput PathInput PathOutput PathInput PathOutput PathInput PathMemoryControllerClock PhaseAlignmentSequencerPLLOutput PathInput PathOutput PathInput PathOutput PathInput PathOutput PathInput PathAddress/Command Lane 2Address/Command Lane 1Address/Command Lane 0DQ Group 0DQ Group 1I/O Lane 2I/O Lane 1DQ Group 1Address/Command Lane 2Address/Command Lane 1Address/Command Lane 0DQ Group 0Interface 1Interface PLL Reference Clock SharingTo implement PLL reference clock sharing, in your RTL code connect the PLL referenceclock signal at your design's top-level to the PLL reference clock port of Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide31To share a PLL reference clock, the following requirements must be met: Interfaces must expect a reference clock signal of the same frequency. Interfaces must be placed in the same column. Interfaces must be placed at adjacent bank Core Clock Network SharingIt is often desirable or necessary for multiple memory interfaces to be accessible usinga single clock domain in the FPGA might want to share core clock networks for the following reasons: To minimize the area and latency penalty associated with clock domain crossing. To minimize consumption of core clock memory interfaces can share the same core clock signals under the followingconditions: The memory interfaces have the same protocol, rate, frequency, and PLL referenceclock source. The interfaces reside in the same I/O column. The interfaces reside in adjacent bank multiple memory interfaces to share core clocks, you must specify one of theinterfaces as master and the remaining interfaces as slaves. Use the Core clockssharing setting in the parameter editor to specify the master and your RTL, connect the clks_sharing_master_out signal from the masterinterface to the clks_sharing_slave_in signal of all the slave interfaces. Both themaster and slave interfaces expose their own output clock ports in the RTL ( , afi_clk), but the signals are equivalent, so it does not matterwhether a clock port from a master or a slave is clock sharing necessitates PLL reference clock sharing; therefore, only themaster interface exposes an input port for the PLL reference clock. All slave interfacesuse the same PLL reference clock User-requested Reset in Intel Stratix 10 EMIF IPThe following table summarizes information about the user-requested resetmechanism in the Intel Stratix 10 EMIF signalslocal_reset_req (input)local_reset_done (output)When can user logic request a reset?local_reset_req has effect only local_reset_done device power-on, the local_reset_done signaltransitions high upon completion of the first calibration,whether the calibration is successful or 2 Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide32DescriptionIs user-requested reset a requirement?A user-requested reset is optional. The I/O SSMautomatically ensures that the memory interface beginsfrom a known state as part of the device power-onsequence. A user-requested reset is necessarily only if theuser logic must explicitly reset a memory interface after thedevice power-on does a user-requested reset actually happen?A reset request is handled by the I/O SSM. If the I/O SSMreceives a reset request from multiple interfaces within thesame I/O column, it must serialize the reset sequence ofthe individual interfaces. You should avoid makingassumptions on when the reset sequence will begin after arequest is requirement and triggering request is sent by transitioning thelocal_reset_req signal from low to high, then keepingthe signal at the high state for a minimum of 2 EMIF coreclock cycles, then transitioning the signal from high to is asynchronous in that there is nosetup/hold timing to meet, but it must meet the minimumpulse width requirement of 2 EMIF core clock long can an external memory interface be kept inreset?It is not possible to keep an external memory interface inreset indefinitely. Asserting local_reset_req highcontinuously has no effect as a reset request is completedby a full 0->1->0 initial calibration cannot be skipped. Thelocal_reset_done signal is driven high only after initialcalibration has scope (within an external memory interface).Only circuits that are required to restore EMIF to power-upstate are reset. Excluded from the reset sequence are theIOSSM, the IOPLL(s), the DLL(s), and the scope (within an I/O column).local_reset_req is a per-interface for Initiating a User-requested ResetStep 1 - PreconditionBefore asserting local_reset_req, user logic must ensure that thelocal_reset_done signal is part of the device power-on sequence, the local_reset_done signalautomatically transitions to high upon the completion of the interface calibrationsequence, regardless of whether calibration is successful or : When targeting a group of interfaces that share the same core clocks, user logic mustensure that the local_reset_done signal of every interface is 2 - Reset Request2 Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide33After the pre-condition is satisfied, user logic can send a reset request by driving thelocal_cal_req signal from low to high and then low again (that is, by sending apulse of 1). The 0-to-1 and 1-to-0 transitions need not happen in relation to any clock edges(that is, they can occur asynchronously); however, the pulse must meet aminimum pulse width of at least 2 EMIF core clock cycles. For example, if theemif_usr_clk has a period of 4ns, then the local_reset_req pulse must lastat least 8ns (that is, two emif_usr_clk periods). The reset request is considered complete only after the 1-to-0 transition. The EMIFIP does not initiate the reset sequence when the local_reset_req is simplyheld high. Additional pulses to local_reset_req are ignored until the reset sequence - Detecting local_reset_done deassertion and assertionIf you want, you can monitor the status of the local_reset_done signal to toexplicitly detect the status of the reset sequence. After the EMIF IP receives a reset request, it deasserts the local_reset_donesignal. After initial power-up calibration, local_reset_done is de-asserted onlyin response to a user-requested reset. The reset sequence is imminent whenlocal_reset_done has transitioned to low, although the exact timing dependson the current state of the I/O SSM. As part of the EMIF reset sequence, the corereset signal (emif_usr_reset_n, afi_reset_n) is driven low. Do not use aregister reset by the core reset signal to sample local_reset_done. After the reset sequence has completed, local_reset_done is driven highagain. local_reset_done being driven high indicates the completion of thereset sequence and the readiness to accept a new reset request; however, it doesnot imply that calibration was successful or that the hard memory controller isready to accept requests. For these purposes, user logic must check signals suchas afi_cal_success, afi_cal_fail, and Intel Stratix 10 EMIF for Hard Processor SubsystemThe Intel Stratix 10 EMIF IP can enable the Intel Stratix 10 Hard Processor Subsystem(HPS) to access external DRAM memory enable connectivity between the Intel Stratix 10 HPS and the Intel Stratix 10 EMIFIP, you must create and configure an instance of the Intel Stratix 10 External MemoryInterface for HPS IP core, and use Platform Designer to connect it to the Intel Stratix10 Hard Processor Subsystem instance in your Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide34Supported ModesThe Intel Stratix 10 Hard Processor Subsystem is compatible with the followingexternal memory configurations:Table Stratix 10 Hard Processor Subsystem CompatibilityProtocolDDR3, DDR4, LPDDR3Maximum memory clock frequencyDDR3: GHzDDR4: GHzLPDDR3: 800 MHzConfigurationHard PHY with hard memory controllerClock rate of PHY and hard memory controllerHalf-rateData width (without ECC)16-bit, 32-bit, 64-bitData width (with ECC)24-bit, 40-bit, 72-bitDQ width per groupx8Maximum number of I/O lanes for address/command3Memory formatDiscrete, UDIMM, SODIMM, RDIMMRanks / CS# widthUp to Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP withHPSYou can use only certain Intel Stratix 10 I/O banks to implement Intel Stratix 10 EMIFIP with the Intel Stratix 10 Hard Processor restrictions on I/O bank usage result from the Intel Stratix 10 HPS having hard-wired connections to the EMIF circuits in the I/O banks closest to the HPS. For anygiven EMIF configuration, the pin-out of the EMIF-to-HPS interface is Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide35The following diagram illustrates the use of I/O banks and lanes for various EMIF-HPSdata widths:Figure Stratix 10 External Memory Interfaces I/O Bank and Lanes UsageECC8bitsECC8bitsECC8bitsAddr/ cmdAddr/ cmdAddr/ cmdAddr/ cmdAddr/ cmdData32bitsData32bitsLane 0Lane 1Lane 2Lane 3Lane 0Lane 1Lane 2Lane 3Lane 0Lane 1Lane 2Lane 364 bit, with ECC64 bit, no ECC32 bit, with ECC32 bit, no ECC16 bit, with ECC16 bit, no ECCI/O Bank 2L I/O Bank 2MI/O Bank 2NHPS(Data bits 63:32)(Addr/Cmd + ECC data)(Data bits 31:0)Data32bitsData32bitsData32bitsData3 2bitsData16bitsData16bitsAddr/ cmdThe HPS EMIF uses the closest located external memory interfaces I/O banks toconnect to SDRAM. These banks include: Bank 2N used for data I/Os (Data bits 31:0) Bank 2M used for address, command and ECC data I/Os Bank 2L used for data I/Os (Data bits 63:32)2 Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide36If no HPS EMIF is used in a system, the entire HPS EMIF bank can be used as FPGAGPIO. If there is a HPS EMIF in a system, the unused HPS EMIF pins can be used asFPGA general I/O with restrictions: Bank 2M: Lane 3 is used for SDRAM ECC data. Unused pins in lane 3 can be used asFPGA inputs only. Lanes 2, 1, and 0 are used for SDRAM address and command. Unused pins inthese lanes can be used as FPGA inputs or outputs. Bank 2N and Bank 2L : Lanes 3, 2, 1, and 0 are used for data bits. With 64-bit data widths, unused pins in these banks can be used as FPGAinputs only. With 32-bit data widths, unused pins in Bank 2N can be used as FPGA pins for Bank 2L can be used as FPGA inputs or outputs. With 16-bit data widths, Intel Quartus Prime assigns lane 0 and lane 1 as datalanes in bank 2N. Unused pins in lane 0 and lane 1 can be used as FPGAinputs only. The other two lanes are available to use as FPGA inputs default, the Intel Stratix 10 External Memory Interface for HPS IP core togetherwith the Intel Quartus Prime Fitter automatically implement the correct pin-out forHPS EMIF without you having to apply additional constraints. If you must modify thedefault pin-out for any reason, you must adhere to the following requirements, whichare specific to HPS EMIF:1. Within a single data lane (which implements a single x8 DQS group): DQ pins must use pins at indices 1, 2, 3, 6, 7, 8, 9, 10. You may swap thelocations between the DQ bits (that is, you may swap location of DQ[0] andDQ[3]) so long as the resulting pin-out uses pins at these indices only. DM/DBI pin must use pin at index 11. There is no flexibility. DQS/DQS# must use pins at index 4 and 5. There is no Assignment of data lanes must be as illustrated in the above figure. You areallowed to swap the locations of entire byte lanes (that is, you may swap locationsof byte 0 and byte 3) so long as the resulting pin-out uses only the lanespermitted by your HPS EMIF configuration, as shown in the above You must not change placement of the address and command pins from may place the alert# pin at any available pin location in either a data lane oran address and command override the default generated pin assignments, comment out the relevantHPS_LOCATION assignments in the .qip file, and add your own location assignments(using set_location_assignment) in the .qsf Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Intel Stratix 10 EMIF Ping Pong PHYPing Pong PHY allows two memory interfaces to share the address and command busthrough time multiplexing. Compared to having two independent interfaces thatallocate address and command lanes separately, Ping Pong PHY achieves the samethroughput with fewer resources, by sharing the address and command Intel Stratix 10 EMIF, Ping Pong PHY supports both half-rate and quarter-rateinterfaces for DDR3, and quarter-rate for Intel Stratix 10 Ping Pong PHY Feature DescriptionConventionally, the address and command buses of a DDR3 or DDR4 half-rate orquarter-rate interface use 2T time meaning that commands are issued for two full-rate clock cycles, as illustrated Command TimingCKCSnAddr, ba2T Command IssuedExtra Setup TimeActive PeriodWith the Ping Pong PHY, address and command signals from two independentcontrollers are multiplexed onto shared buses by delaying one of the controlleroutputs by one full-rate clock cycle. The result is 1T timing, with a new commandbeing issued on each full-rate clock cycle. The following figure shows address andcommand timing for the Ping Pong command signals CS, ODT, and CKE have two signals (one for ping and one forpong); the other address and command signals are Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide38Figure Command Timing Use by Ping Pong PHYCKCSn[0]CSn[1]Addr, Intel Stratix 10 Ping Pong PHY ArchitectureIn Intel Stratix 10 EMIF, the Ping Pong PHY feature can be enabled only with the hardmemory controller, where two hard memory controllers are instantiated one for theprimary interface and one for the secondary hard memory controller I/O bank of the primary interface is used for address andcommand and is always adjacent and above the hard memory controller bank of thesecondary interface. All four lanes of the primary hard memory controller bank areused for address and following example shows a 2x16 Ping Pong PHY bank-lane configuration. Theupper bank (I/O bank N) is the address and command bank, which serves both theprimary and secondary interfaces. The primary hard memory controller is linked to thesecondary interface by the Ping Pong bus. The lower bank (I/O bank N-1) is thesecondary interface bank, which carries the data buses for both primary andsecondary interfaces. In the 2x16 case a total of four I/O banks are required for data,hence two banks in total are sufficient for the data for the primary interface is routed down to the top two lanes of thesecondary I/O bank, and the data for the secondary interface is routed to the bottomtwo lanes of the secondary I/O Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide39Figure Ping Pong PHY I/O Bank-Lane ConfigurationPrimary HMCDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile NAddress/CommandSecondary HMCDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile N - 1PrimaaryInterfaceData BusSecondaryInterfaceData BusA 2x32 interface can be implemented similarly, with the additional data lanes placedabove and below the primary and secondary I/O banks, such that primary data lanesare placed above the primary bank and secondary data lanes are placed below thesecondary Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide40Figure Ping Pong PHY I/O Bank-Lane HMCDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile NAddress/CommandControl PathDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile N + 1PrimaryInterfaceData BusControl PathDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile N - 2SecondaryInterfaceData BusSecondary HMCDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile N - 1PrimaaryInterfaceData BusSecondaryInterfaceData Intel Stratix 10 Ping Pong PHY LimitationsPing Pong PHY supports up to two ranks per memory interface. In addition, themaximum data width is x72, which is half the maximum width of x144 for a Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide41Ping Pong PHY uses all lanes of the address and command I/O bank as address andcommand. For information on the pin allocations of the DDR3 and DDR4 address andcommand I/O bank, refer to DDR3 Scheme 1 and DDR4 Scheme 3, in ExternalMemory Interface Pin Information for Stratix 10 Devices, on additional limitation is that I/O lanes may be left unused when you instantiatemultiple pairs of Ping Pong PHY interfaces. The following diagram shows two pairs ofx8 Pin Pong controllers (a total of 4 interfaces). Lanes highlighted in yellow are notdriven by any memory interfaces (unused lanes and pins can still serve as generalpurpose I/Os). Even with some I/O lanes left unused, the Ping Pong PHY approach isstill beneficial in terms of resource usage, compared to independent widths of 24 bits and 40 bits have a similar situation, while 16 bit, 32 bit, and64 bit memory widths do not suffer this Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide42Figure Pairs of x8 Pin-Pong PHY ControllersPrimary HMCDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile N - 1Address/CommandControl PathDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile NPrimaryInterfaceData BusSecondary HMCDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile N - 4SecondaryInterfaceData BusPrimary HMCDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile N - 3Address/CommandSecondary HMCDBCOData Buffer x12DBC1Data Buffer x12DBC2Data Buffer x12DBC3Data Buffer x12I/O Tile N - 2SecondaryInterfaceData BusPrimaryInterfaceData Intel Stratix 10 Ping Pong PHY CalibrationA Ping Pong PHY interface is calibrated as a regular interface of double of a Ping Pong PHY interface incorporates two sequencers, one on theprimary hard memory controller I/O bank, and one on the secondary hard memorycontroller I/O bank. To ensure that the two sequencers issue instructions on the samememory clock cycle, the Nios II processor configures the sequencer on the primaryhard memory controller to receive a token from the secondary interface, ignoring any2 Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide43commands from the Avalon bus. Additional delays are programmed on the secondaryinterface to allow for the passing of the token from the sequencer on the secondaryhard memory controller tile to the sequencer on the primary hard memory controllertile. During calibration, the Nios II processor assumes that commands are alwaysissued from the sequencer on the primary hard memory controller I/O bank. Aftercalibration, the Nios II processor adjusts the delays for use with the primary andsecondary hard memory Using the Ping Pong PHYThe following steps describe how to use the Ping Pong PHY for Intel Stratix 10 Configure a single memory interface according to your Select Instantiate two controllers sharing a Ping Pong PHY on the Generaltab in the parameter Intel Quartus Prime software replicates the interface, resulting in two memorycontrollers and a shared PHY. The system configures the I/O bank-lane structure,without further input from Ping Pong PHY Simulation Example DesignThe following figure illustrates a top-level block diagram of a generated Ping Pong PHYsimulation example design, using two I/O , the IP interfaces with user traffic separately, as it would with twoindependent memory interfaces. You can also generate synthesizable exampledesigns, where the external memory interface IP interfaces with a traffic Pong PHY Simulation Example DesignLane 3Lane 2Lane 1Lane 0PrimaryHMCTile NLane 3Lane 2Lane 1Lane 0SecondaryHMCTile N - 1EMIFTrafficGenerator 0TrafficGenerator 1SimCheckerMemory0Memory1CS, ODT, CKECAS, RAS, WE, ADDR, BA, BG, ...CS, ODT, CKEDQ, DQS, DMDQ, DQS, DMSimulation Example Intel Stratix 10 EMIF and SmartVIDIntel Stratix 10 EMIF IP can be used with the SmartVID voltage management system,to achieve reduced power Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide44The SmartVID controller allows the FPGA to operate at a reduced Vcc, whilemaintaining performance. Because the SmartVID controller can adjust Vcc up or downin response to power requirements and temperature, it can have an impact onexternal memory interface performance. When used with the SmartVID controller, theEMIF IP implements a handshake protocol to ensure that EMIF calibration does notbegin until after voltage adjustment has extended speed grade devices, voltage adjustment occurs once when the FPGA ispowered up, and no further voltage adjustments occur. The external memorycalibration occurs after this initial voltage adjustment is completed. EMIF specificationsare expected to be slightly lower in extended speed grade devices using SmartVID,than in devices not using industrial speed grade devices, voltage adjustment occurs at power up, and mayalso occur during operation, in response to temperature changes. External memoryinterface calibration does not occur until after the initial voltage adjustment at powerup. However, the external memory interface is not recalibrated in response tosubsequent voltage adjustments that occur during operation. As a result, EMIFspecifications for industrial speed grade devices using SmartVID are expected to belower than for extended speed grade Intel Stratix 10 EMIF IP with SmartVIDTo employIntel Stratix 10 EMIF IP with SmartVID, follow these steps:1. Ensure that the Intel Quartus Prime project and Platform Designer system areconfigured to use VID components. This step exposes thevid_cal_done_persist interface on instantiated EMIF IP, which is required forcommunicating with the SmartVID Instantiate the SmartVID controller, using an I/O PLL IP core to drive the 125MHzvid_clk and the 25MHz jtag_core_clk inputs of the Smart VID : Do not connect the emif_usr_clk signal to either the vid_clk orjtag_core_clk inputs. Doing so would hold both the EMIF IP and theSmartVID controller in a perpetual reset Instantiate the Intel Stratix 10 EMIF the vid_cal_done_persist signal from the EMIF IP with thecal_done_persistent signal on the SmartVID controller. This connectionenables handshaking between the EMIF IP and the SmartVID controller, whichallows the EMIF IP to delay memory calibration until after voltage levels : The EMIF vid_cal_done_persist interface becomes available only whena VID-enabled device is Intel Stratix 10 EMIF IP Product ArchitectureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide453 Intel Stratix 10 EMIF IP End-User Interface and Signal DescriptionsThe following sections describe each of the interfaces and their signals, by protocol,for the Intel Stratix 10 EMIF Intel Stratix 10 EMIF IP Interfaces for DDR3The interfaces in the Intel Stratix 10 External Memory Interface IP each have signalsthat can be connected in Platform Designer (formerly known as Qsys). The followingtable lists the interfaces and corresponding interface types for for DDR3Interface NameInterface TypeDescriptionglobal_reset_nReset InputGlobal reset interfacelocal_reset_reqConduitLocal reset request interfacelocal_reset_statusConduitLocal reset status interfacelocal_reset_req_outConduitIF_LO CAL_RESET_REQ_OUT_DESClocal_reset_status _inConduitIF_LOCAL_RESET_STATUS_IN_DESCp ll_ref_clkClock InputPLL reference clock interfacepll_ref_clk_outClock OutputIF_PLL_REF_CLK_OUT_DESCpll_lockedC onduitIF_PLL_LOCKED_DESCpll_extra_clk_0C lock OutputIF_PLL_EXTRA_CLK_0_DESCpll_extra_c lk_1Clock OutputIF_PLL_EXTRA_CLK_1_DESCpll_extra_c lk_2Clock OutputIF_PLL_EXTRA_CLK_2_DESCpll_extra_c lk_3Clock OutputIF_PLL_EXTRA_CLK_3_DESCoctConduitO CT interfacememConduitInterface between FPGA and external memorystatusConduitPHY calibration status interfaceafi_reset_nReset OutputAFI reset interfaceafi_clkClock OutputAFI clock UG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008RegisteredInterface NameInterface TypeDescriptionafi_half_clkClock OutputAFI half-rate clock interfaceafiConduitAltera PHY Interface (AFI)emif_usr_reset_nReset OutputUser clock domain reset interfaceemif_usr_clkClock OutputUser clock interfaceemif_usr_reset_n_secReset OutputUser clock domain reset interface (for the secondaryinterface in ping-pong configuration)emif_usr_clk_secClock OutputUser clock interface (for the secondary interface in ping-pong configuration)cal_debug_reset_nReset InputUser calibration debug clock domain reset interfacecal_debug_clkClock InputUser calibration debug clock interfacecal_debug_out_reset_nReset OutputUser calibration debug clock domain reset interfacecal_debug_out_clkClock OutputUser calibration debug clock interfaceclks_sharing_master_outConduitC ore clocks sharing master interfaceclks_sharing_slave_inConduitCor e clocks sharing slave interfacectrl_ammAvalon Memory-Mapped SlaveController Avalon Memory-Mapped interfacectrl_ecc_user_interruptConduitC ontroller ECC user interrupt interfacehps_emifConduitConduit between Hard Processor Subsystem and memoryinterfacecal_debugAvalon Memory-Mapped SlaveCalibration debug interfacecal_debug_outAvalon Memory-Mapped MasterCalibration debug interfacegeneric_clkClock InputIF_GENERIC_CLK_DESCgeneric_reset_nR eset global_reset_n for DDR3Global reset interfaceTable : global_reset_nInterface type: Reset InputPort NameDirectionDescriptionglobal_reset_nIn putAsynchronous reset causes the memory interface to bereset and recalibrated. The global reset signal applies to allmemory interfaces placed within an I/O local_reset_req for DDR3Local reset request interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide47Table : local_reset_reqInterface type: ConduitPort NameDirectionDescriptionlocal_reset_reqI nputSignal from user logic to request the memory interface tobe reset and recalibrated. Reset request is sent bytransitioning the local_reset_req signal from low to high,then keeping the signal at the high state for a minimum of 2EMIF core clock cycles, then transitioning the signal fromhigh to low. local_reset_req is asynchronous in that there isno setup/hold timing to meet, but it must meet theminimum pulse width requirement of 2 EMIF core local_reset_status for DDR3Local reset status interfaceTable : local_reset_statusInterface type: ConduitPort NameDirectionDescriptionlocal_reset_done OutputSignal from memory interface to indicate whether it hascompleted a reset sequence, is currently out of reset, and isready for a new reset request. When local_reset_done islow, the memory interface is in local_reset_req_out for DDR3IF_LOCAL_RESET_REQ_OUT_DESCTable : local_reset_req_outInterface type: ConduitPort local_reset_status_in for DDR3IF_LOCAL_RESET_STATUS_IN_DESCTable : local_reset_status_inInterface type: ConduitPort pll_ref_clk for DDR3PLL reference clock interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide48Table : pll_ref_clkInterface type: Clock InputPort NameDirectionDescriptionpll_ref_clkInput PLL reference clock input. Connect this interface to the clockoutput of the clock source that matches the PLL referenceclock frequency value set in the parameter pll_ref_clk_out for DDR3IF_PLL_REF_CLK_OUT_DESCTable : pll_ref_clk_outInterface type: Clock OutputPort pll_locked for DDR3IF_PLL_LOCKED_DESCTable : pll_lockedInterface type: ConduitPort pll_extra_clk_0 for DDR3IF_PLL_EXTRA_CLK_0_DESCTable : pll_extra_clk_0Interface type: Clock OutputPort pll_extra_clk_1 for DDR3IF_PLL_EXTRA_CLK_1_DESCTable : pll_extra_clk_1Interface type: Clock OutputPort pll_extra_clk_2 for DDR3IF_PLL_EXTRA_CLK_2_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide49Table : pll_extra_clk_2Interface type: Clock OutputPort pll_extra_clk_3 for DDR3IF_PLL_EXTRA_CLK_3_DESCTable : pll_extra_clk_3Interface type: Clock OutputPort oct for DDR3OCT interfaceTable : octInterface type: ConduitPort NameDirectionDescriptionoct_rzqinInputCa librated On-Chip Termination (OCT) RZQ input mem for DDR3Interface between FPGA and external memoryTable : memInterface type: ConduitPort NameDirectionDescriptionmem_ckOutputCK clockmem_ck_nOutputCK clock (negative leg)mem_aOutputAddressmem_baOutputBank addressmem_ckeOutputClock enablemem_cs_nOutputChip selectmem_rmOutputRank multiplication for LRDIMM. Typically, mem_rm[0] andmem_rm[1] connect to CS2# and CS3# of the memorybuffer of all LRDIMM terminationmem_ras_nOutputRAS commandmem_cas_nOutputCAS 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide50Port NameDirectionDescriptionmem_we_nOutputWE commandmem_reset_nOutputAsynchronous resetmem_parOutputCommand and address parity. (memory format=RDIMM/LRDIMM)mem_dmOutputWrite data maskmem_dqBidirectionalRead/write datamem_dqsBidirectionalData strobemem_dqs_nBidirectionalData strobe (negative leg)mem_alert_nInputAlert status for DDR3PHY calibration status interfaceTable : statusInterface type: ConduitPort NameDirectionDescriptionlocal_cal_succes sOutputWhen high, indicates that PHY calibration was successfullocal_cal_failOutputWhen high, indicates that PHY calibration has afi_reset_n for DDR3AFI reset interfaceTable : afi_reset_nInterface type: Reset OutputPort NameDirectionDescriptionafi_reset_nOutpu tReset for the AFI clock domain. Asynchronous assertion andsynchronous afi_clk for DDR3AFI clock interfaceTable : afi_clkInterface type: Clock OutputPort NameDirectionDescriptionafi_clkOutputClo ck for the Altera PHY Interface (AFI) afi_half_clk for DDR3AFI half-rate clock interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide51Table : afi_half_clkInterface type: Clock OutputPort NameDirectionDescriptionafi_half_clkOutp utClock running at half the frequency of the AFI clock afi for DDR3Altera PHY Interface (AFI)Table : afiInterface type: ConduitPort NameDirectionDescriptionafi_cal_successO utputSignals calibration successful completionafi_cal_failOutputSignals calibration failureafi_cal_reqInputWhen asserted, the interface is recalibratedafi_rlatOutputLatency in afi_clk cycles between read command and readdata validafi_wlatOutputLatency in afi_clk cycles between write command and writedata validafi_addrInputAddressafi_baInputBank addressafi_ckeInputClock enableafi_cs_nInputChip selectafi_rmInputRank multiplication for LRDIMMafi_odtInputOn-die terminationafi_ras_nInputRAS commandafi_cas_nInputCAS commandafi_we_nInputWE commandafi_rst_nInputAsynchronous resetafi_parInputCommand and address parityafi_dmInputWrite data maskafi_dqs_burstInputAsserted by the controller to enable the output DQS signalafi_wdata_validInputAsserted by the controller to indicate that afi_wdatacontains valid write dataafi_wdataInputWrite dataafi_rdata_en_fullInputAsserted by the controller to indicate the amount of relevantread data expectedafi_rdataOutputRead 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide52Port NameDirectionDescriptionafi_rdata_validO utputAsserted by the PHY to indicate that afi_rdata contains validread dataafi_rrankInputAsserted by the controller to indicate which rank is beingread from, to control shadow register switchingafi_wrankInputAsserted by the controller to indicate which rank is beingwritten to, to control shadow register emif_usr_reset_n for DDR3User clock domain reset interfaceTable : emif_usr_reset_nInterface type: Reset OutputPort NameDirectionDescriptionemif_usr_reset_n OutputReset for the user clock domain. Asynchronous assertionand synchronous emif_usr_clk for DDR3User clock interfaceTable : emif_usr_clkInterface type: Clock OutputPort NameDirectionDescriptionemif_usr_clkOutp utUser clock emif_usr_reset_n_sec for DDR3User clock domain reset interface (for the secondary interface in ping-pongconfiguration)Table : emif_usr_reset_n_secInterface type: Reset OutputPort NameDirectionDescriptionemif_usr_reset_n _secOutputReset for the user clock domain. Asynchronous assertionand synchronous deassertion. Intended for the secondaryinterface in a ping-pong emif_usr_clk_sec for DDR3User clock interface (for the secondary interface in ping-pong configuration)3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide53Table : emif_usr_clk_secInterface type: Clock OutputPort NameDirectionDescriptionemif_usr_clk_sec OutputUser clock domain. Intended for the secondary interface ina ping-pong cal_debug_reset_n for DDR3User calibration debug clock domain reset interfaceTable : cal_debug_reset_nInterface type: Reset InputPort NameDirectionDescriptioncal_debug_reset_ nInputReset for the user clock connecting to the Avalon calibrationdebug bus. Asynchronous assertion and cal_debug_clk for DDR3User calibration debug clock interfaceTable : cal_debug_clkInterface type: Clock InputPort NameDirectionDescriptioncal_debug_clkInp utUser clock cal_debug_out_reset_n for DDR3User calibration debug clock domain reset interfaceTable : cal_debug_out_reset_nInterface type: Reset OutputPort NameDirectionDescriptioncal_debug_out_re set_nOutputReset for the user clock connecting to the Avalon calibrationdebug_out bus. Asynchronous assertion and cal_debug_out_clk for DDR3User calibration debug clock interfaceTable : cal_debug_out_clkInterface type: Clock OutputPort NameDirectionDescriptioncal_debug_out_cl kOutputUser clock domain3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User clks_sharing_master_out for DDR3Core clocks sharing master interfaceTable : clks_sharing_master_outInterface type: ConduitPort NameDirectionDescriptionclks_sharing_mas ter_outOutputThis port should fanout to all the core clocks sharing clks_sharing_slave_in for DDR3Core clocks sharing slave interfaceTable : clks_sharing_slave_inInterface type: ConduitPort NameDirectionDescriptionclks_sharing_sla ve_inInputThis port should be connected to the core clocks ctrl_amm for DDR3Controller Avalon Memory-Mapped interfaceTable : ctrl_ammInterface type: Avalon Memory-Mapped SlavePort NameDirectionDescriptionamm_readyOutputW ait-request is asserted when controller is busyamm_readInputRead request signalamm_writeInputWrite request signalamm_addressInputAddress for the read/write requestamm_readdataOutputRead dataamm_writedataInputWrite dataamm_burstcountInputNumber of transfers in each read/write burstamm_byteenableInputByte-enable for write dataamm_beginbursttransferInputIndicates when a burst is startingamm_readdatavalidOutputIndicates whether read data is ctrl_ecc_user_interrupt for DDR3Controller ECC user interrupt interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide55Table : ctrl_ecc_user_interruptInterface type: ConduitPort NameDirectionDescriptionctrl_ecc_user_in terruptOutputController ECC user interrupt interface for connection to acustom control block that must be notified when eithersingle-bit or double-bit ECC errors hps_emif for DDR3Conduit between Hard Processor Subsystem and memory interfaceTable : hps_emifInterface type: ConduitPort NameDirectionDescriptionhps_to_emifInput Signals coming from Hard Processor Subsystem to thememory interfaceemif_to_hpsOutputSignals going to Hard Processor Subsystem from thememory interfacehps_to_emif_gpInputSignals coming from Hard Processor Subsystem GPIO to thememory interfaceemif_to_hps_gpOutputSignals going to Hard Processor Subsystem GPIO from thememory cal_debug for DDR3Calibration debug interfaceTable : cal_debugInterface type: Avalon Memory-Mapped SlavePort NameDirectionDescriptioncal_debug_waitre questOutputWait-request is asserted when controller is busycal_debug_readInputRead request signalcal_debug_writeInputWrite request signalcal_debug_addrInputAddress for the read/write requestcal_debug_read_dataOutputRead datacal_debug_write_dataInputWrite datacal_debug_byteenableInputByte-enable for write datacal_debug_read_data_validOutputIndic ates whether read data is cal_debug_out for DDR3Calibration debug interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide56Table : cal_debug_outInterface type: Avalon Memory-Mapped MasterPort NameDirectionDescriptioncal_debug_out_wa itrequestInputWait-request is asserted when controller is busycal_debug_out_readOutputRead request signalcal_debug_out_writeOutputWrite request signalcal_debug_out_addrOutputAddress for the read/write requestcal_debug_out_read_dataInputRead datacal_debug_out_write_dataOutputWrite datacal_debug_out_byteenableOutputByte-e nable for write datacal_debug_out_read_data_validInputIn dicates whether read data is generic_clk for DDR3IF_GENERIC_CLK_DESCTable : generic_clkInterface type: Clock InputPort generic_reset_n for DDR3IF_GENERIC_RESET_DESCTable : generic_reset_nInterface type: Reset InputPort generic_conduit_reset_n for DDR3IF_GENERIC_CONDUIT_RESET_DESCTable : generic_conduit_reset_nInterface type: ConduitPort Intel Stratix 10 EMIF IP Interfaces for DDR4The interfaces in the Intel Stratix 10 External Memory Interface IP each have signalsthat can be connected in Platform Designer (formerly known as Qsys). The followingtable lists the interfaces and corresponding interface types for Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide57Table for DDR4Interface NameInterface TypeDescriptionglobal_reset_nReset InputGlobal reset interfacelocal_reset_reqConduitLocal reset request interfacelocal_reset_statusConduitLocal reset status interfacelocal_reset_req_outConduitIF_LO CAL_RESET_REQ_OUT_DESClocal_reset_status _inConduitIF_LOCAL_RESET_STATUS_IN_DESCp ll_ref_clkClock InputPLL reference clock interfacepll_ref_clk_outClock OutputIF_PLL_REF_CLK_OUT_DESCpll_lockedC onduitIF_PLL_LOCKED_DESCpll_extra_clk_0C lock OutputIF_PLL_EXTRA_CLK_0_DESCpll_extra_c lk_1Clock OutputIF_PLL_EXTRA_CLK_1_DESCpll_extra_c lk_2Clock OutputIF_PLL_EXTRA_CLK_2_DESCpll_extra_c lk_3Clock OutputIF_PLL_EXTRA_CLK_3_DESCoctConduitO CT interfacememConduitInterface between FPGA and external memorystatusConduitPHY calibration status interfaceafi_reset_nReset OutputAFI reset interfaceafi_clkClock OutputAFI clock interfaceafi_half_clkClock OutputAFI half-rate clock interfaceafiConduitAltera PHY Interface (AFI)emif_usr_reset_nReset OutputUser clock domain reset interfaceemif_usr_clkClock OutputUser clock interfaceemif_usr_reset_n_secReset OutputUser clock domain reset interface (for the secondaryinterface in ping-pong configuration)emif_usr_clk_secClock OutputUser clock interface (for the secondary interface in ping-pong configuration)cal_debug_reset_nReset InputUser calibration debug clock domain reset interfacecal_debug_clkClock InputUser calibration debug clock interfacecal_debug_out_reset_nReset OutputUser calibration debug clock domain reset interfacecal_debug_out_clkClock OutputUser calibration debug clock interfaceclks_sharing_master_outConduitC ore clocks sharing master interfaceclks_sharing_slave_inConduitCor e clocks sharing slave interfacectrl_ammAvalon Memory-Mapped SlaveController Avalon Memory-Mapped interfacectrl_ecc_user_interruptConduitC ontroller ECC user interrupt interfacehps_emifConduitConduit between Hard Processor Subsystem and 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide58Interface NameInterface TypeDescriptioncal_debugAvalon Memory-Mapped SlaveCalibration debug interfacecal_debug_outAvalon Memory-Mapped MasterCalibration debug interfacegeneric_clkClock InputIF_GENERIC_CLK_DESCgeneric_reset_nR eset global_reset_n for DDR4Global reset interfaceTable : global_reset_nInterface type: Reset InputPort NameDirectionDescriptionglobal_reset_nIn putAsynchronous reset causes the memory interface to bereset and recalibrated. The global reset signal applies to allmemory interfaces placed within an I/O local_reset_req for DDR4Local reset request interfaceTable : local_reset_reqInterface type: ConduitPort NameDirectionDescriptionlocal_reset_reqI nputSignal from user logic to request the memory interface tobe reset and recalibrated. Reset request is sent bytransitioning the local_reset_req signal from low to high,then keeping the signal at the high state for a minimum of 2EMIF core clock cycles, then transitioning the signal fromhigh to low. local_reset_req is asynchronous in that there isno setup/hold timing to meet, but it must meet theminimum pulse width requirement of 2 EMIF core local_reset_status for DDR4Local reset status interfaceTable : local_reset_statusInterface type: ConduitPort NameDirectionDescriptionlocal_reset_done OutputSignal from memory interface to indicate whether it hascompleted a reset sequence, is currently out of reset, and isready for a new reset request. When local_reset_done islow, the memory interface is in Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User local_reset_req_out for DDR4IF_LOCAL_RESET_REQ_OUT_DESCTable : local_reset_req_outInterface type: ConduitPort local_reset_status_in for DDR4IF_LOCAL_RESET_STATUS_IN_DESCTable : local_reset_status_inInterface type: ConduitPort pll_ref_clk for DDR4PLL reference clock interfaceTable : pll_ref_clkInterface type: Clock InputPort NameDirectionDescriptionpll_ref_clkInput PLL reference clock pll_ref_clk_out for DDR4IF_PLL_REF_CLK_OUT_DESCTable : pll_ref_clk_outInterface type: Clock OutputPort pll_locked for DDR4IF_PLL_LOCKED_DESCTable : pll_lockedInterface type: ConduitPort NameDirectionDescriptionpll_lockedOutput PORT_PLL_LOCKED_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User pll_extra_clk_0 for DDR4IF_PLL_EXTRA_CLK_0_DESCTable : pll_extra_clk_0Interface type: Clock OutputPort pll_extra_clk_1 for DDR4IF_PLL_EXTRA_CLK_1_DESCTable : pll_extra_clk_1Interface type: Clock OutputPort pll_extra_clk_2 for DDR4IF_PLL_EXTRA_CLK_2_DESCTable : pll_extra_clk_2Interface type: Clock OutputPort pll_extra_clk_3 for DDR4IF_PLL_EXTRA_CLK_3_DESCTable : pll_extra_clk_3Interface type: Clock OutputPort oct for DDR4OCT interfaceTable : octInterface type: ConduitPort NameDirectionDescriptionoct_rzqinInputCa librated On-Chip Termination (OCT) RZQ input pin3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User mem for DDR4Interface between FPGA and external memoryTable : memInterface type: ConduitPort NameDirectionDescriptionmem_ckOutputCK clockmem_ck_nOutputCK clock (negative leg)mem_aOutputAddressmem_baOutputBank addressmem_bgOutputBank groupmem_ckeOutputClock enablemem_cs_nOutputChip selectmem_odtOutputOn-die terminationmem_reset_nOutputAsynchronous resetmem_act_nOutputActivation commandmem_parOutputCommand and address parity. (memory format=RDIMM/LRDIMM)mem_dqBidirectionalR ead/write datamem_dbi_nBidirectionalActs as either the data bus inversion pin, or the data maskpin, depending on strobemem_dqs_nBidirectionalData strobe (negative leg)mem_alert_nInputAlert status for DDR4PHY calibration status interfaceTable : statusInterface type: ConduitPort NameDirectionDescriptionlocal_cal_succes sOutputWhen high, indicates that PHY calibration was successfullocal_cal_failOutputWhen high, indicates that PHY calibration afi_reset_n for DDR4AFI reset interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide62Table : afi_reset_nInterface type: Reset OutputPort NameDirectionDescriptionafi_reset_nOutpu tReset for the AFI clock domain. Asynchronous assertion andsynchronous afi_clk for DDR4AFI clock interfaceTable : afi_clkInterface type: Clock OutputPort NameDirectionDescriptionafi_clkOutputClo ck for the Altera PHY Interface (AFI) afi_half_clk for DDR4AFI half-rate clock interfaceTable : afi_half_clkInterface type: Clock OutputPort NameDirectionDescriptionafi_half_clkOutp utClock running at half the frequency of the AFI clock afi for DDR4Altera PHY Interface (AFI)Table : afiInterface type: ConduitPort NameDirectionDescriptionafi_cal_successO utputSignals calibration successful completionafi_cal_failOutputSignals calibration failureafi_cal_reqInputWhen asserted, the interface is recalibratedafi_rlatOutputLatency in afi_clk cycles between read command and readdata validafi_wlatOutputLatency in afi_clk cycles between write command and writedata validafi_addrInputAddressafi_baInputBank addressafi_bgInputBank groupafi_ckeInputClock enableafi_cs_nInputChip 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide63Port NameDirectionDescriptionafi_odtInputOn-d ie terminationafi_rst_nInputAsynchronous resetafi_act_nInputActivation commandafi_parInputCommand and address parityafi_dm_nInputWrite data maskafi_dqs_burstInputAsserted by the controller to enable the output DQS signalafi_wdata_validInputAsserted by the controller to indicate that afi_wdatacontains valid write dataafi_wdataInputWrite dataafi_rdata_en_fullInputAsserted by the controller to indicate the amount of relevantread data expectedafi_rdataOutputRead dataafi_rdata_validOutputAsserted by the PHY to indicate that afi_rdata contains validread dataafi_rrankInputAsserted by the controller to indicate which rank is beingread from, to control shadow register switchingafi_wrankInputAsserted by the controller to indicate which rank is beingwritten to, to control shadow register emif_usr_reset_n for DDR4User clock domain reset interfaceTable : emif_usr_reset_nInterface type: Reset OutputPort NameDirectionDescriptionemif_usr_reset_n OutputReset for the user clock domain. Asynchronous assertionand synchronous emif_usr_clk for DDR4User clock interfaceTable : emif_usr_clkInterface type: Clock OutputPort NameDirectionDescriptionemif_usr_clkOutp utUser clock emif_usr_reset_n_sec for DDR4User clock domain reset interface (for the secondary interface in ping-pongconfiguration)3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide64Table : emif_usr_reset_n_secInterface type: Reset OutputPort NameDirectionDescriptionemif_usr_reset_n _secOutputReset for the user clock domain. Asynchronous assertionand synchronous deassertion. Intended for the secondaryinterface in a ping-pong emif_usr_clk_sec for DDR4User clock interface (for the secondary interface in ping-pong configuration)Table : emif_usr_clk_secInterface type: Clock OutputPort NameDirectionDescriptionemif_usr_clk_sec OutputUser clock domain. Intended for the secondary interface ina ping-pong cal_debug_reset_n for DDR4User calibration debug clock domain reset interfaceTable : cal_debug_reset_nInterface type: Reset InputPort NameDirectionDescriptioncal_debug_reset_ nInputReset for the user clock connecting to the Avalon calibrationdebug bus. Asynchronous assertion and cal_debug_clk for DDR4User calibration debug clock interfaceTable : cal_debug_clkInterface type: Clock InputPort NameDirectionDescriptioncal_debug_clkInp utUser clock cal_debug_out_reset_n for DDR4User calibration debug clock domain reset interfaceTable : cal_debug_out_reset_nInterface type: Reset OutputPort NameDirectionDescriptioncal_debug_out_re set_nOutputReset for the user clock connecting to the Avalon calibrationdebug_out bus. Asynchronous assertion and synchronousdeassertion3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User cal_debug_out_clk for DDR4User calibration debug clock interfaceTable : cal_debug_out_clkInterface type: Clock OutputPort NameDirectionDescriptioncal_debug_out_cl kOutputUser clock clks_sharing_master_out for DDR4Core clocks sharing master interfaceTable : clks_sharing_master_outInterface type: ConduitPort NameDirectionDescriptionclks_sharing_mas ter_outOutputThis port should fanout to all the core clocks sharing clks_sharing_slave_in for DDR4Core clocks sharing slave interfaceTable : clks_sharing_slave_inInterface type: ConduitPort NameDirectionDescriptionclks_sharing_sla ve_inInputThis port should be connected to the core clocks ctrl_amm for DDR4Controller Avalon Memory-Mapped interfaceTable : ctrl_ammInterface type: Avalon Memory-Mapped SlavePort NameDirectionDescriptionamm_readyOutputW ait-request is asserted when controller is busyamm_readInputRead request signalamm_writeInputWrite request signalamm_addressInputAddress for the read/write requestamm_readdataOutputRead dataamm_writedataInputWrite dataamm_burstcountInputNumber of transfers in each read/write 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide66Port NameDirectionDescriptionamm_byteenableIn putByte-enable for write dataamm_beginbursttransferInputIndicates when a burst is startingamm_readdatavalidOutputIndicates whether read data is ctrl_ecc_user_interrupt for DDR4Controller ECC user interrupt interfaceTable : ctrl_ecc_user_interruptInterface type: ConduitPort NameDirectionDescriptionctrl_ecc_user_in terruptOutputController ECC user interrupt signal to determine whetherthere is a bit hps_emif for DDR4Conduit between Hard Processor Subsystem and memory interfaceTable : hps_emifInterface type: ConduitPort NameDirectionDescriptionhps_to_emifInput Signals coming from Hard Processor Subsystem to thememory interfaceemif_to_hpsOutputSignals going to Hard Processor Subsystem from thememory interfacehps_to_emif_gpInputSignals coming from Hard Processor Subsystem GPIO to thememory interfaceemif_to_hps_gpOutputSignals going to Hard Processor Subsystem GPIO from thememory cal_debug for DDR4Calibration debug interfaceTable : cal_debugInterface type: Avalon Memory-Mapped SlavePort NameDirectionDescriptioncal_debug_waitre questOutputWait-request is asserted when controller is busycal_debug_readInputRead request signalcal_debug_writeInputWrite request signalcal_debug_addrInputAddress for the read/write requestcal_debug_read_dataOutputRead 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide67Port NameDirectionDescriptioncal_debug_write_ dataInputWrite datacal_debug_byteenableInputByte-enable for write datacal_debug_read_data_validOutputIndic ates whether read data is cal_debug_out for DDR4Calibration debug interfaceTable : cal_debug_outInterface type: Avalon Memory-Mapped MasterPort NameDirectionDescriptioncal_debug_out_wa itrequestInputWait-request is asserted when controller is busycal_debug_out_readOutputRead request signalcal_debug_out_writeOutputWrite request signalcal_debug_out_addrOutputAddress for the read/write requestcal_debug_out_read_dataInputRead datacal_debug_out_write_dataOutputWrite datacal_debug_out_byteenableOutputByte-e nable for write datacal_debug_out_read_data_validInputIn dicates whether read data is generic_clk for DDR4IF_GENERIC_CLK_DESCTable : generic_clkInterface type: Clock InputPort generic_reset_n for DDR4IF_GENERIC_RESET_DESCTable : generic_reset_nInterface type: Reset InputPort generic_conduit_reset_n for DDR4IF_GENERIC_CONDUIT_RESET_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide68Table : generic_conduit_reset_nInterface type: ConduitPort Intel Stratix 10 EMIF IP Interfaces for LPDDR3The interfaces in the Intel Stratix 10 External Memory Interface IP each have signalsthat can be connected in Platform Designer (formerly known as Qsys). The followingtable lists the interfaces and corresponding interface types for for LPDDR3Interface NameInterface TypeDescriptionglobal_reset_nReset InputGlobal reset interfacelocal_reset_reqConduitLocal reset request interfacelocal_reset_statusConduitLocal reset status interfacelocal_reset_req_outConduitIF_LO CAL_RESET_REQ_OUT_DESClocal_reset_status _inConduitIF_LOCAL_RESET_STATUS_IN_DESCp ll_ref_clkClock InputPLL reference clock interfacepll_ref_clk_outClock OutputIF_PLL_REF_CLK_OUT_DESCpll_lockedC onduitIF_PLL_LOCKED_DESCpll_extra_clk_0C lock OutputIF_PLL_EXTRA_CLK_0_DESCpll_extra_c lk_1Clock OutputIF_PLL_EXTRA_CLK_1_DESCpll_extra_c lk_2Clock OutputIF_PLL_EXTRA_CLK_2_DESCpll_extra_c lk_3Clock OutputIF_PLL_EXTRA_CLK_3_DESCoctConduitO CT interfacememConduitInterface between FPGA and external memorystatusConduitPHY calibration status interfaceafi_reset_nReset OutputAFI reset interfaceafi_clkClock OutputAFI clock interfaceafi_half_clkClock OutputAFI half-rate clock interfaceafiConduitAltera PHY Interface (AFI)emif_usr_reset_nReset OutputUser clock domain reset interfaceemif_usr_clkClock OutputUser clock interfacecal_debug_reset_nReset InputUser calibration debug clock domain reset interfacecal_debug_clkClock InputUser calibration debug clock interfacecal_debug_out_reset_nReset OutputUser calibration debug clock domain reset interfacecal_debug_out_clkClock OutputUser calibration debug clock interfaceclks_sharing_master_outConduitC ore clocks sharing master 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide69Interface NameInterface TypeDescriptionclks_sharing_slave_inCond uitCore clocks sharing slave interfacehps_emifConduitConduit between Hard Processor Subsystem and memoryinterfacecal_debugAvalon Memory-Mapped SlaveCalibration debug interfacecal_debug_outAvalon Memory-Mapped MasterCalibration debug interfacegeneric_clkClock InputIF_GENERIC_CLK_DESCgeneric_reset_nR eset global_reset_n for LPDDR3Global reset interfaceTable : global_reset_nInterface type: Reset InputPort NameDirectionDescriptionglobal_reset_nIn putAsynchronous reset causes the memory interface to bereset and recalibrated. The global reset signal applies to allmemory interfaces placed within an I/O local_reset_req for LPDDR3Local reset request interfaceTable : local_reset_reqInterface type: ConduitPort NameDirectionDescriptionlocal_reset_reqI nputSignal from user logic to request the memory interface tobe reset and recalibrated. Reset request is sent bytransitioning the local_reset_req signal from low to high,then keeping the signal at the high state for a minimum of 2EMIF core clock cycles, then transitioning the signal fromhigh to low. local_reset_req is asynchronous in that there isno setup/hold timing to meet, but it must meet theminimum pulse width requirement of 2 EMIF core local_reset_status for LPDDR3Local reset status interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide70Table : local_reset_statusInterface type: ConduitPort NameDirectionDescriptionlocal_reset_done OutputSignal from memory interface to indicate whether it hascompleted a reset sequence, is currently out of reset, and isready for a new reset request. When local_reset_done islow, the memory interface is in local_reset_req_out for LPDDR3IF_LOCAL_RESET_REQ_OUT_DESCTable : local_reset_req_outInterface type: ConduitPort local_reset_status_in for LPDDR3IF_LOCAL_RESET_STATUS_IN_DESCTable : local_reset_status_inInterface type: ConduitPort pll_ref_clk for LPDDR3PLL reference clock interfaceTable : pll_ref_clkInterface type: Clock InputPort NameDirectionDescriptionpll_ref_clkInput PLL reference clock pll_ref_clk_out for LPDDR3IF_PLL_REF_CLK_OUT_DESCTable : pll_ref_clk_outInterface type: Clock OutputPort NameDirectionDescriptionpll_ref_clk_outO utputPORT_PLL_REF_CLK_OUT_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User pll_locked for LPDDR3IF_PLL_LOCKED_DESCTable : pll_lockedInterface type: ConduitPort pll_extra_clk_0 for LPDDR3IF_PLL_EXTRA_CLK_0_DESCTable : pll_extra_clk_0Interface type: Clock OutputPort pll_extra_clk_1 for LPDDR3IF_PLL_EXTRA_CLK_1_DESCTable : pll_extra_clk_1Interface type: Clock OutputPort pll_extra_clk_2 for LPDDR3IF_PLL_EXTRA_CLK_2_DESCTable : pll_extra_clk_2Interface type: Clock OutputPort pll_extra_clk_3 for LPDDR3IF_PLL_EXTRA_CLK_3_DESCTable : pll_extra_clk_3Interface type: Clock OutputPort NameDirectionDescriptionpll_extra_clk_3O utputPORT_PLL_EXTRA_CLK_3_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User oct for LPDDR3OCT interfaceTable : octInterface type: ConduitPort NameDirectionDescriptionoct_rzqinInputCa librated On-Chip Termination (OCT) RZQ input mem for LPDDR3Interface between FPGA and external memoryTable : memInterface type: ConduitPort NameDirectionDescriptionmem_ckOutputCK clockmem_ck_nOutputCK clock (negative leg)mem_aOutputAddressmem_ckeOutputClock enablemem_cs_nOutputChip selectmem_odtOutputOn-die terminationmem_reset_nOutputAsynchronous resetmem_dmOutputWrite data maskmem_dqBidirectionalRead/write datamem_dqsBidirectionalData strobemem_dqs_nBidirectionalData strobe (negative leg) status for LPDDR3PHY calibration status interfaceTable : statusInterface type: ConduitPort NameDirectionDescriptionlocal_cal_succes sOutputWhen high, indicates that PHY calibration was successfullocal_cal_failOutputWhen high, indicates that PHY calibration afi_reset_n for LPDDR3AFI reset interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide73Table : afi_reset_nInterface type: Reset OutputPort NameDirectionDescriptionafi_reset_nOutpu tReset for the AFI clock domain. Asynchronous assertion andsynchronous afi_clk for LPDDR3AFI clock interfaceTable : afi_clkInterface type: Clock OutputPort NameDirectionDescriptionafi_clkOutputClo ck for the Altera PHY Interface (AFI) afi_half_clk for LPDDR3AFI half-rate clock interfaceTable : afi_half_clkInterface type: Clock OutputPort NameDirectionDescriptionafi_half_clkOutp utClock running at half the frequency of the AFI clock afi for LPDDR3Altera PHY Interface (AFI)Table : afiInterface type: ConduitPort NameDirectionDescriptionafi_cal_successO utputSignals calibration successful completionafi_cal_failOutputSignals calibration failureafi_cal_reqInputWhen asserted, the interface is recalibratedafi_rlatOutputLatency in afi_clk cycles between read command and readdata validafi_wlatOutputLatency in afi_clk cycles between write command and writedata validafi_addrInputAddressafi_ckeInputClo ck enableafi_cs_nInputChip selectafi_odtInputOn-die terminationafi_rst_nInputAsynchronous 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide74Port NameDirectionDescriptionafi_dmInputWrite data maskafi_dqs_burstInputAsserted by the controller to enable the output DQS signalafi_wdata_validInputAsserted by the controller to indicate that afi_wdatacontains valid write dataafi_wdataInputWrite dataafi_rdata_en_fullInputAsserted by the controller to indicate the amount of relevantread data expectedafi_rdataOutputRead dataafi_rdata_validOutputAsserted by the PHY to indicate that afi_rdata contains validread dataafi_rrankInputAsserted by the controller to indicate which rank is beingread from, to control shadow register switchingafi_wrankInputAsserted by the controller to indicate which rank is beingwritten to, to control shadow register emif_usr_reset_n for LPDDR3User clock domain reset interfaceTable : emif_usr_reset_nInterface type: Reset OutputPort NameDirectionDescriptionemif_usr_reset_n OutputReset for the user clock domain. Asynchronous assertionand synchronous emif_usr_clk for LPDDR3User clock interfaceTable : emif_usr_clkInterface type: Clock OutputPort NameDirectionDescriptionemif_usr_clkOutp utUser clock cal_debug_reset_n for LPDDR3User calibration debug clock domain reset interfaceTable : cal_debug_reset_nInterface type: Reset InputPort NameDirectionDescriptioncal_debug_reset_ nInputReset for the user clock connecting to the Avalon calibrationdebug bus. Asynchronous assertion and synchronousdeassertion3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User cal_debug_clk for LPDDR3User calibration debug clock interfaceTable : cal_debug_clkInterface type: Clock InputPort NameDirectionDescriptioncal_debug_clkInp utUser clock cal_debug_out_reset_n for LPDDR3User calibration debug clock domain reset interfaceTable : cal_debug_out_reset_nInterface type: Reset OutputPort NameDirectionDescriptioncal_debug_out_re set_nOutputReset for the user clock connecting to the Avalon calibrationdebug_out bus. Asynchronous assertion and cal_debug_out_clk for LPDDR3User calibration debug clock interfaceTable : cal_debug_out_clkInterface type: Clock OutputPort NameDirectionDescriptioncal_debug_out_cl kOutputUser clock clks_sharing_master_out for LPDDR3Core clocks sharing master interfaceTable : clks_sharing_master_outInterface type: ConduitPort NameDirectionDescriptionclks_sharing_mas ter_outOutputThis port should fanout to all the core clocks sharing clks_sharing_slave_in for LPDDR3Core clocks sharing slave interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide76Table : clks_sharing_slave_inInterface type: ConduitPort NameDirectionDescriptionclks_sharing_sla ve_inInputThis port should be connected to the core clocks hps_emif for LPDDR3Conduit between Hard Processor Subsystem and memory interfaceTable : hps_emifInterface type: ConduitPort NameDirectionDescriptionhps_to_emifInput Signals coming from Hard Processor Subsystem to thememory interfaceemif_to_hpsOutputSignals going to Hard Processor Subsystem from thememory interfacehps_to_emif_gpInputSignals coming from Hard Processor Subsystem GPIO to thememory interfaceemif_to_hps_gpOutputSignals going to Hard Processor Subsystem GPIO from thememory cal_debug for LPDDR3Calibration debug interfaceTable : cal_debugInterface type: Avalon Memory-Mapped SlavePort NameDirectionDescriptioncal_debug_waitre questOutputWait-request is asserted when controller is busycal_debug_readInputRead request signalcal_debug_writeInputWrite request signalcal_debug_addrInputAddress for the read/write requestcal_debug_read_dataOutputRead datacal_debug_write_dataInputWrite datacal_debug_byteenableInputByte-enable for write datacal_debug_read_data_validOutputIndic ates whether read data is cal_debug_out for LPDDR3Calibration debug interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide77Table : cal_debug_outInterface type: Avalon Memory-Mapped MasterPort NameDirectionDescriptioncal_debug_out_wa itrequestInputWait-request is asserted when controller is busycal_debug_out_readOutputRead request signalcal_debug_out_writeOutputWrite request signalcal_debug_out_addrOutputAddress for the read/write requestcal_debug_out_read_dataInputRead datacal_debug_out_write_dataOutputWrite datacal_debug_out_byteenableOutputByte-e nable for write datacal_debug_out_read_data_validInputIn dicates whether read data is generic_clk for LPDDR3IF_GENERIC_CLK_DESCTable : generic_clkInterface type: Clock InputPort generic_reset_n for LPDDR3IF_GENERIC_RESET_DESCTable : generic_reset_nInterface type: Reset InputPort generic_conduit_reset_n for LPDDR3IF_GENERIC_CONDUIT_RESET_DESCTable : generic_conduit_reset_nInterface type: ConduitPort Intel Stratix 10 EMIF IP Interfaces for QDR II/II+/II+ XtremeThe interfaces in the Intel Stratix 10 External Memory Interface IP each have signalsthat can be connected in Platform Designer (formerly known as Qsys). The followingtable lists the interfaces and corresponding interface types for QDR II/II+/II+ Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide78Table for QDR II/II+/II+ XtremeInterface NameInterface TypeDescriptionglobal_reset_nReset InputGlobal reset interfacelocal_reset_reqConduitLocal reset request interfacelocal_reset_statusConduitLocal reset status interfacelocal_reset_req_outConduitIF_LO CAL_RESET_REQ_OUT_DESClocal_reset_status _inConduitIF_LOCAL_RESET_STATUS_IN_DESCp ll_ref_clkClock InputPLL reference clock interfacepll_ref_clk_outClock OutputIF_PLL_REF_CLK_OUT_DESCpll_lockedC onduitIF_PLL_LOCKED_DESCpll_extra_clk_0C lock OutputIF_PLL_EXTRA_CLK_0_DESCpll_extra_c lk_1Clock OutputIF_PLL_EXTRA_CLK_1_DESCpll_extra_c lk_2Clock OutputIF_PLL_EXTRA_CLK_2_DESCpll_extra_c lk_3Clock OutputIF_PLL_EXTRA_CLK_3_DESCoctConduitO CT interfacememConduitInterface between FPGA and external memorystatusConduitPHY calibration status interfaceemif_usr_reset_nReset OutputUser clock domain reset interfaceemif_usr_clkClock OutputUser clock interfacecal_debug_reset_nReset InputUser calibration debug clock domain reset interfacecal_debug_clkClock InputUser calibration debug clock interfacecal_debug_out_reset_nReset OutputUser calibration debug clock domain reset interfacecal_debug_out_clkClock OutputUser calibration debug clock interfaceclks_sharing_master_outConduitC ore clocks sharing master interfaceclks_sharing_slave_inConduitCor e clocks sharing slave interfacectrl_ammAvalon Memory-Mapped SlaveController Avalon Memory-Mapped interfacehps_emifConduitConduit between Hard Processor Subsystem and memoryinterfacecal_debugAvalon Memory-Mapped SlaveCalibration debug interfacecal_debug_outAvalon Memory-Mapped MasterCalibration debug interfacegeneric_clkClock InputIF_GENERIC_CLK_DESCgeneric_reset_nR eset global_reset_n for QDR II/II+/II+ XtremeGlobal reset interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide79Table : global_reset_nInterface type: Reset InputPort NameDirectionDescriptionglobal_reset_nIn putAsynchronous reset causes the memory interface to bereset and recalibrated. The global reset signal applies to allmemory interfaces placed within an I/O local_reset_req for QDR II/II+/II+ XtremeLocal reset request interfaceTable : local_reset_reqInterface type: ConduitPort NameDirectionDescriptionlocal_reset_reqI nputSignal from user logic to request the memory interface tobe reset and recalibrated. Reset request is sent bytransitioning the local_reset_req signal from low to high,then keeping the signal at the high state for a minimum of 2EMIF core clock cycles, then transitioning the signal fromhigh to low. local_reset_req is asynchronous in that there isno setup/hold timing to meet, but it must meet theminimum pulse width requirement of 2 EMIF core local_reset_status for QDR II/II+/II+ XtremeLocal reset status interfaceTable : local_reset_statusInterface type: ConduitPort NameDirectionDescriptionlocal_reset_done OutputSignal from memory interface to indicate whether it hascompleted a reset sequence, is currently out of reset, and isready for a new reset request. When local_reset_done islow, the memory interface is in local_reset_req_out for QDR II/II+/II+ XtremeIF_LOCAL_RESET_REQ_OUT_DESCTable : local_reset_req_outInterface type: ConduitPort local_reset_status_in for QDR II/II+/II+ XtremeIF_LOCAL_RESET_STATUS_IN_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide80Table : local_reset_status_inInterface type: ConduitPort pll_ref_clk for QDR II/II+/II+ XtremePLL reference clock interfaceTable : pll_ref_clkInterface type: Clock InputPort NameDirectionDescriptionpll_ref_clkInput PLL reference clock pll_ref_clk_out for QDR II/II+/II+ XtremeIF_PLL_REF_CLK_OUT_DESCTable : pll_ref_clk_outInterface type: Clock OutputPort pll_locked for QDR II/II+/II+ XtremeIF_PLL_LOCKED_DESCTable : pll_lockedInterface type: ConduitPort pll_extra_clk_0 for QDR II/II+/II+ XtremeIF_PLL_EXTRA_CLK_0_DESCTable : pll_extra_clk_0Interface type: Clock OutputPort pll_extra_clk_1 for QDR II/II+/II+ XtremeIF_PLL_EXTRA_CLK_1_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide81Table : pll_extra_clk_1Interface type: Clock OutputPort pll_extra_clk_2 for QDR II/II+/II+ XtremeIF_PLL_EXTRA_CLK_2_DESCTable : pll_extra_clk_2Interface type: Clock OutputPort pll_extra_clk_3 for QDR II/II+/II+ XtremeIF_PLL_EXTRA_CLK_3_DESCTable : pll_extra_clk_3Interface type: Clock OutputPort oct for QDR II/II+/II+ XtremeOCT interfaceTable : octInterface type: ConduitPort NameDirectionDescriptionoct_rzqinInputCa librated On-Chip Termination (OCT) RZQ input mem for QDR II/II+/II+ XtremeInterface between FPGA and external memoryTable : memInterface type: ConduitPort NameDirectionDescriptionmem_ckOutputCK clockmem_ck_nOutputCK clock (negative leg)mem_kOutputK clockmem_k_nOutputK clock (negative leg) 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide82Port NameDirectionDescriptionmem_aOutputAddre ssmem_reset_nOutputAsynchronous resetmem_wps_nOutputWrite port selectmem_rps_nOutputRead port selectmem_doff_nOutputDLL turn offmem_bws_nOutputByte write selectmem_dOutputWrite datamem_qInputRead datamem_cqInputEcho clockmem_cq_nInputEcho clock (negative leg) status for QDR II/II+/II+ XtremePHY calibration status interfaceTable : statusInterface type: ConduitPort NameDirectionDescriptionlocal_cal_succes sOutputWhen high, indicates that PHY calibration was successfullocal_cal_failOutputWhen high, indicates that PHY calibration emif_usr_reset_n for QDR II/II+/II+ XtremeUser clock domain reset interfaceTable : emif_usr_reset_nInterface type: Reset OutputPort NameDirectionDescriptionemif_usr_reset_n OutputReset for the user clock domain. Asynchronous assertionand synchronous emif_usr_clk for QDR II/II+/II+ XtremeUser clock interfaceTable : emif_usr_clkInterface type: Clock OutputPort NameDirectionDescriptionemif_usr_clkOutp utUser clock cal_debug_reset_n for QDR II/II+/II+ XtremeUser calibration debug clock domain reset interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide83Table : cal_debug_reset_nInterface type: Reset InputPort NameDirectionDescriptioncal_debug_reset_ nInputReset for the user clock connecting to the Avalon calibrationdebug bus. Asynchronous assertion and cal_debug_clk for QDR II/II+/II+ XtremeUser calibration debug clock interfaceTable : cal_debug_clkInterface type: Clock InputPort NameDirectionDescriptioncal_debug_clkInp utUser clock cal_debug_out_reset_n for QDR II/II+/II+ XtremeUser calibration debug clock domain reset interfaceTable : cal_debug_out_reset_nInterface type: Reset OutputPort NameDirectionDescriptioncal_debug_out_re set_nOutputReset for the user clock connecting to the Avalon calibrationdebug_out bus. Asynchronous assertion and cal_debug_out_clk for QDR II/II+/II+ XtremeUser calibration debug clock interfaceTable : cal_debug_out_clkInterface type: Clock OutputPort NameDirectionDescriptioncal_debug_out_cl kOutputUser clock clks_sharing_master_out for QDR II/II+/II+ XtremeCore clocks sharing master interfaceTable : clks_sharing_master_outInterface type: ConduitPort NameDirectionDescriptionclks_sharing_mas ter_outOutputThis port should fanout to all the core clocks sharing Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User clks_sharing_slave_in for QDR II/II+/II+ XtremeCore clocks sharing slave interfaceTable : clks_sharing_slave_inInterface type: ConduitPort NameDirectionDescriptionclks_sharing_sla ve_inInputThis port should be connected to the core clocks ctrl_amm for QDR II/II+/II+ XtremeController Avalon Memory-Mapped interfaceTable : ctrl_ammInterface type: Avalon Memory-Mapped SlavePort NameDirectionDescriptionamm_readyOutputW ait-request is asserted when controller is busyamm_readInputRead request signalamm_writeInputWrite request signalamm_addressInputAddress for the read/write requestamm_readdataOutputRead dataamm_writedataInputWrite dataamm_burstcountInputNumber of transfers in each read/write burstamm_byteenableInputByte-enable for write dataamm_beginbursttransferInputIndicates when a burst is startingamm_readdatavalidOutputIndicates whether read data is hps_emif for QDR II/II+/II+ XtremeConduit between Hard Processor Subsystem and memory interfaceTable : hps_emifInterface type: ConduitPort NameDirectionDescriptionhps_to_emifInput Signals coming from Hard Processor Subsystem to thememory interfaceemif_to_hpsOutputSignals going to Hard Processor Subsystem from thememory interfacehps_to_emif_gpInputSignals coming from Hard Processor Subsystem GPIO to thememory interfaceemif_to_hps_gpOutputSignals going to Hard Processor Subsystem GPIO from thememory interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User cal_debug for QDR II/II+/II+ XtremeCalibration debug interfaceTable : cal_debugInterface type: Avalon Memory-Mapped SlavePort NameDirectionDescriptioncal_debug_waitre questOutputWait-request is asserted when controller is busycal_debug_readInputRead request signalcal_debug_writeInputWrite request signalcal_debug_addrInputAddress for the read/write requestcal_debug_read_dataOutputRead datacal_debug_write_dataInputWrite datacal_debug_byteenableInputByte-enable for write datacal_debug_read_data_validOutputIndic ates whether read data is cal_debug_out for QDR II/II+/II+ XtremeCalibration debug interfaceTable : cal_debug_outInterface type: Avalon Memory-Mapped MasterPort NameDirectionDescriptioncal_debug_out_wa itrequestInputWait-request is asserted when controller is busycal_debug_out_readOutputRead request signalcal_debug_out_writeOutputWrite request signalcal_debug_out_addrOutputAddress for the read/write requestcal_debug_out_read_dataInputRead datacal_debug_out_write_dataOutputWrite datacal_debug_out_byteenableOutputByte-e nable for write datacal_debug_out_read_data_validInputIn dicates whether read data is generic_clk for QDR II/II+/II+ XtremeIF_GENERIC_CLK_DESCTable : generic_clkInterface type: Clock InputPort NameDirectionDescriptionclkInputPORT_GEN ERIC_CLK_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User generic_reset_n for QDR II/II+/II+ XtremeIF_GENERIC_RESET_DESCTable : generic_reset_nInterface type: Reset InputPort generic_conduit_reset_n for QDR II/II+/II+ XtremeIF_GENERIC_CONDUIT_RESET_DESCTable : generic_conduit_reset_nInterface type: ConduitPort Intel Stratix 10 EMIF IP Interfaces for QDR-IVThe interfaces in the Intel Stratix 10 External Memory Interface IP each have signalsthat can be connected in Platform Designer (formerly known as Qsys). The followingtable lists the interfaces and corresponding interface types for for QDR-IVInterface NameInterface TypeDescriptionglobal_reset_nReset InputGlobal reset interfacelocal_reset_reqConduitLocal reset request interfacelocal_reset_statusConduitLocal reset status interfacelocal_reset_req_outConduitIF_LO CAL_RESET_REQ_OUT_DESClocal_reset_status _inConduitIF_LOCAL_RESET_STATUS_IN_DESCp ll_ref_clkClock InputPLL reference clock interfacepll_ref_clk_outClock OutputIF_PLL_REF_CLK_OUT_DESCpll_lockedC onduitIF_PLL_LOCKED_DESCpll_extra_clk_0C lock OutputIF_PLL_EXTRA_CLK_0_DESCpll_extra_c lk_1Clock OutputIF_PLL_EXTRA_CLK_1_DESCpll_extra_c lk_2Clock OutputIF_PLL_EXTRA_CLK_2_DESCpll_extra_c lk_3Clock OutputIF_PLL_EXTRA_CLK_3_DESCoctConduitO CT interfacememConduitInterface between FPGA and external memorystatusConduitPHY calibration status 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide87Interface NameInterface TypeDescriptionafi_reset_nReset OutputAFI reset interfaceafi_clkClock OutputAFI clock interfaceafi_half_clkClock OutputAFI half-rate clock interfaceafiConduitAltera PHY Interface (AFI)emif_usr_reset_nReset OutputUser clock domain reset interfaceemif_usr_clkClock OutputUser clock interfacecal_debug_reset_nReset InputUser calibration debug clock domain reset interfacecal_debug_clkClock InputUser calibration debug clock interfacecal_debug_out_reset_nReset OutputUser calibration debug clock domain reset interfacecal_debug_out_clkClock OutputUser calibration debug clock interfaceclks_sharing_master_outConduitC ore clocks sharing master interfaceclks_sharing_slave_inConduitCor e clocks sharing slave interfacectrl_ammAvalon Memory-Mapped SlaveController Avalon Memory-Mapped interfacehps_emifConduitConduit between Hard Processor Subsystem and memoryinterfacecal_debugAvalon Memory-Mapped SlaveCalibration debug interfacecal_debug_outAvalon Memory-Mapped MasterCalibration debug interfacegeneric_clkClock InputIF_GENERIC_CLK_DESCgeneric_reset_nR eset global_reset_n for QDR-IVGlobal reset interfaceTable : global_reset_nInterface type: Reset InputPort NameDirectionDescriptionglobal_reset_nIn putAsynchronous reset causes the memory interface to bereset and recalibrated. The global reset signal applies to allmemory interfaces placed within an I/O local_reset_req for QDR-IVLocal reset request interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide88Table : local_reset_reqInterface type: ConduitPort NameDirectionDescriptionlocal_reset_reqI nputSignal from user logic to request the memory interface tobe reset and recalibrated. Reset request is sent bytransitioning the local_reset_req signal from low to high,then keeping the signal at the high state for a minimum of 2EMIF core clock cycles, then transitioning the signal fromhigh to low. local_reset_req is asynchronous in that there isno setup/hold timing to meet, but it must meet theminimum pulse width requirement of 2 EMIF core local_reset_status for QDR-IVLocal reset status interfaceTable : local_reset_statusInterface type: ConduitPort NameDirectionDescriptionlocal_reset_done OutputSignal from memory interface to indicate whether it hascompleted a reset sequence, is currently out of reset, and isready for a new reset request. When local_reset_done islow, the memory interface is in local_reset_req_out for QDR-IVIF_LOCAL_RESET_REQ_OUT_DESCTable : local_reset_req_outInterface type: ConduitPort local_reset_status_in for QDR-IVIF_LOCAL_RESET_STATUS_IN_DESCTable : local_reset_status_inInterface type: ConduitPort pll_ref_clk for QDR-IVPLL reference clock interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide89Table : pll_ref_clkInterface type: Clock InputPort NameDirectionDescriptionpll_ref_clkInput PLL reference clock pll_ref_clk_out for QDR-IVIF_PLL_REF_CLK_OUT_DESCTable : pll_ref_clk_outInterface type: Clock OutputPort pll_locked for QDR-IVIF_PLL_LOCKED_DESCTable : pll_lockedInterface type: ConduitPort pll_extra_clk_0 for QDR-IVIF_PLL_EXTRA_CLK_0_DESCTable : pll_extra_clk_0Interface type: Clock OutputPort pll_extra_clk_1 for QDR-IVIF_PLL_EXTRA_CLK_1_DESCTable : pll_extra_clk_1Interface type: Clock OutputPort pll_extra_clk_2 for QDR-IVIF_PLL_EXTRA_CLK_2_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide90Table : pll_extra_clk_2Interface type: Clock OutputPort pll_extra_clk_3 for QDR-IVIF_PLL_EXTRA_CLK_3_DESCTable : pll_extra_clk_3Interface type: Clock OutputPort oct for QDR-IVOCT interfaceTable : octInterface type: ConduitPort NameDirectionDescriptionoct_rzqinInputCa librated On-Chip Termination (OCT) RZQ input mem for QDR-IVInterface between FPGA and external memoryTable : memInterface type: ConduitPort NameDirectionDescriptionmem_ckOutputCK clockmem_ck_nOutputCK clock (negative leg)mem_dkaOutputDK clock for port Amem_dka_nOutputDK clock for port A (negative leg)mem_dkbOutputDK clock for port Bmem_dkb_nOutputDK clock for port B (negative leg)mem_aOutputAddressmem_reset_nOutputA synchronous resetmem_lda_nOutputSynchronous load for port Amem_ldb_nOutputSynchronous load for port Bmem_rwa_nOutputSynchronous read/write for port 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide91Port NameDirectionDescriptionmem_rwb_nOutputS ynchronous read/write for port Bmem_lbk0_nOutputLoopback modemem_lbk1_nOutputLoopback modemem_cfg_nOutputConfiguration bitmem_apOutputAddress paritymem_ainvOutputAddress inversionmem_dqaBidirectionalRead/write data for port Amem_dqbBidirectionalRead/write data for port Bmem_dinvaBidirectionalRead/write data inversion for port Amem_dinvbBidirectionalRead/write data inversion for port Bmem_qkaInputRead data clock for port Amem_qka_nInputRead data clock for port A (negative leg)mem_qkbInputRead data clock for port Bmem_qkb_nInputRead data clock for port B (negative leg)mem_pe_nInputAddress parity error status for QDR-IVPHY calibration status interfaceTable : statusInterface type: ConduitPort NameDirectionDescriptionlocal_cal_succes sOutputWhen high, indicates that PHY calibration was successfullocal_cal_failOutputWhen high, indicates that PHY calibration afi_reset_n for QDR-IVAFI reset interfaceTable : afi_reset_nInterface type: Reset OutputPort NameDirectionDescriptionafi_reset_nOutpu tReset for the AFI clock domain. Asynchronous assertion andsynchronous afi_clk for QDR-IVAFI clock interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide92Table : afi_clkInterface type: Clock OutputPort NameDirectionDescriptionafi_clkOutputClo ck for the Altera PHY Interface (AFI) afi_half_clk for QDR-IVAFI half-rate clock interfaceTable : afi_half_clkInterface type: Clock OutputPort NameDirectionDescriptionafi_half_clkOutp utClock running at half the frequency of the AFI clock afi for QDR-IVAltera PHY Interface (AFI)Table : afiInterface type: ConduitPort NameDirectionDescriptionafi_ld_nInputSyn chronous load for port A and Bafi_rw_nInputSynchronous read/write for port A and Bafi_lbk0_nInputLoopback modeafi_lbk1_nInputLoopback modeafi_cfg_nInputConfiguration bitafi_apInputAddress parityafi_ainvInputAddress inversionafi_rdata_dinvOutputData inversion for read dataafi_wdata_dinvInputData inversion for write dataafi_pe_nOutputAddress parity error emif_usr_reset_n for QDR-IVUser clock domain reset interfaceTable : emif_usr_reset_nInterface type: Reset OutputPort NameDirectionDescriptionemif_usr_reset_n OutputReset for the user clock domain. Asynchronous assertionand synchronous deassertion3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User emif_usr_clk for QDR-IVUser clock interfaceTable : emif_usr_clkInterface type: Clock OutputPort NameDirectionDescriptionemif_usr_clkOutp utUser clock cal_debug_reset_n for QDR-IVUser calibration debug clock domain reset interfaceTable : cal_debug_reset_nInterface type: Reset InputPort NameDirectionDescriptioncal_debug_reset_ nInputReset for the user clock connecting to the Avalon calibrationdebug bus. Asynchronous assertion and cal_debug_clk for QDR-IVUser calibration debug clock interfaceTable : cal_debug_clkInterface type: Clock InputPort NameDirectionDescriptioncal_debug_clkInp utUser clock cal_debug_out_reset_n for QDR-IVUser calibration debug clock domain reset interfaceTable : cal_debug_out_reset_nInterface type: Reset OutputPort NameDirectionDescriptioncal_debug_out_re set_nOutputReset for the user clock connecting to the Avalon calibrationdebug_out bus. Asynchronous assertion and cal_debug_out_clk for QDR-IVUser calibration debug clock interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide94Table : cal_debug_out_clkInterface type: Clock OutputPort NameDirectionDescriptioncal_debug_out_cl kOutputUser clock clks_sharing_master_out for QDR-IVCore clocks sharing master interfaceTable : clks_sharing_master_outInterface type: ConduitPort NameDirectionDescriptionclks_sharing_mas ter_outOutputThis port should fanout to all the core clocks sharing clks_sharing_slave_in for QDR-IVCore clocks sharing slave interfaceTable : clks_sharing_slave_inInterface type: ConduitPort NameDirectionDescriptionclks_sharing_sla ve_inInputThis port should be connected to the core clocks ctrl_amm for QDR-IVController Avalon Memory-Mapped interfaceTable : ctrl_ammInterface type: Avalon Memory-Mapped SlavePort NameDirectionDescriptionamm_readyOutputW ait-request is asserted when controller is busyamm_readInputRead request signalamm_writeInputWrite request signalamm_addressInputAddress for the read/write requestamm_readdataOutputRead dataamm_writedataInputWrite dataamm_burstcountInputNumber of transfers in each read/write burstamm_beginbursttransferInputIndicate s when a burst is startingamm_readdatavalidOutputIndicates whether read data is hps_emif for QDR-IVConduit between Hard Processor Subsystem and memory interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide95Table : hps_emifInterface type: ConduitPort NameDirectionDescriptionhps_to_emifInput Signals coming from Hard Processor Subsystem to thememory interfaceemif_to_hpsOutputSignals going to Hard Processor Subsystem from thememory interfacehps_to_emif_gpInputSignals coming from Hard Processor Subsystem GPIO to thememory interfaceemif_to_hps_gpOutputSignals going to Hard Processor Subsystem GPIO from thememory cal_debug for QDR-IVCalibration debug interfaceTable : cal_debugInterface type: Avalon Memory-Mapped SlavePort NameDirectionDescriptioncal_debug_waitre questOutputWait-request is asserted when controller is busycal_debug_readInputRead request signalcal_debug_writeInputWrite request signalcal_debug_addrInputAddress for the read/write requestcal_debug_read_dataOutputRead datacal_debug_write_dataInputWrite datacal_debug_byteenableInputByte-enable for write datacal_debug_read_data_validOutputIndic ates whether read data is cal_debug_out for QDR-IVCalibration debug interfaceTable : cal_debug_outInterface type: Avalon Memory-Mapped MasterPort NameDirectionDescriptioncal_debug_out_wa itrequestInputWait-request is asserted when controller is busycal_debug_out_readOutputRead request signalcal_debug_out_writeOutputWrite request signalcal_debug_out_addrOutputAddress for the read/write requestcal_debug_out_read_dataInputRead 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide96Port NameDirectionDescriptioncal_debug_out_wr ite_dataOutputWrite datacal_debug_out_byteenableOutputByte-e nable for write datacal_debug_out_read_data_validInputIn dicates whether read data is generic_clk for QDR-IVIF_GENERIC_CLK_DESCTable : generic_clkInterface type: Clock InputPort generic_reset_n for QDR-IVIF_GENERIC_RESET_DESCTable : generic_reset_nInterface type: Reset InputPort generic_conduit_reset_n for QDR-IVIF_GENERIC_CONDUIT_RESET_DESCTable : generic_conduit_reset_nInterface type: ConduitPort Intel Stratix 10 EMIF IP Interfaces for RLDRAM 3The interfaces in the Intel Stratix 10 External Memory Interface IP each have signalsthat can be connected in Platform Designer (formerly known as Qsys). The followingtable lists the interfaces and corresponding interface types for RLDRAM for RLDRAM 3Interface NameInterface TypeDescriptionglobal_reset_nReset InputGlobal reset interfacelocal_reset_reqConduitLocal reset request interfacelocal_reset_statusConduitLocal reset status 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide97Interface NameInterface TypeDescriptionlocal_reset_req_outCondui tIF_LOCAL_RESET_REQ_OUT_DESClocal_reset_ status_inConduitIF_LOCAL_RESET_STATUS_IN _DESCpll_ref_clkClock InputPLL reference clock interfacepll_ref_clk_outClock OutputIF_PLL_REF_CLK_OUT_DESCpll_lockedC onduitIF_PLL_LOCKED_DESCpll_extra_clk_0C lock OutputIF_PLL_EXTRA_CLK_0_DESCpll_extra_c lk_1Clock OutputIF_PLL_EXTRA_CLK_1_DESCpll_extra_c lk_2Clock OutputIF_PLL_EXTRA_CLK_2_DESCpll_extra_c lk_3Clock OutputIF_PLL_EXTRA_CLK_3_DESCoctConduitO CT interfacememConduitInterface between FPGA and external memorystatusConduitPHY calibration status interfaceafi_reset_nReset OutputAFI reset interfaceafi_clkClock OutputAFI clock interfaceafi_half_clkClock OutputAFI half-rate clock interfaceafiConduitAltera PHY Interface (AFI)cal_debug_reset_nReset InputUser calibration debug clock domain reset interfacecal_debug_clkClock InputUser calibration debug clock interfacecal_debug_out_reset_nReset OutputUser calibration debug clock domain reset interfacecal_debug_out_clkClock OutputUser calibration debug clock interfaceclks_sharing_master_outConduitC ore clocks sharing master interfaceclks_sharing_slave_inConduitCor e clocks sharing slave interfacehps_emifConduitConduit between Hard Processor Subsystem and memoryinterfacecal_debugAvalon Memory-Mapped SlaveCalibration debug interfacecal_debug_outAvalon Memory-Mapped MasterCalibration debug interfacegeneric_clkClock InputIF_GENERIC_CLK_DESCgeneric_reset_nR eset global_reset_n for RLDRAM 3Global reset interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide98Table : global_reset_nInterface type: Reset InputPort NameDirectionDescriptionglobal_reset_nIn putAsynchronous reset causes the memory interface to bereset and recalibrated. The global reset signal applies to allmemory interfaces placed within an I/O local_reset_req for RLDRAM 3Local reset request interfaceTable : local_reset_reqInterface type: ConduitPort NameDirectionDescriptionlocal_reset_reqI nputSignal from user logic to request the memory interface tobe reset and recalibrated. Reset request is sent bytransitioning the local_reset_req signal from low to high,then keeping the signal at the high state for a minimum of 2EMIF core clock cycles, then transitioning the signal fromhigh to low. local_reset_req is asynchronous in that there isno setup/hold timing to meet, but it must meet theminimum pulse width requirement of 2 EMIF core local_reset_status for RLDRAM 3Local reset status interfaceTable : local_reset_statusInterface type: ConduitPort NameDirectionDescriptionlocal_reset_done OutputSignal from memory interface to indicate whether it hascompleted a reset sequence, is currently out of reset, and isready for a new reset request. When local_reset_done islow, the memory interface is in local_reset_req_out for RLDRAM 3IF_LOCAL_RESET_REQ_OUT_DESCTable : local_reset_req_outInterface type: ConduitPort local_reset_status_in for RLDRAM 3IF_LOCAL_RESET_STATUS_IN_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide99Table : local_reset_status_inInterface type: ConduitPort pll_ref_clk for RLDRAM 3PLL reference clock interfaceTable : pll_ref_clkInterface type: Clock InputPort NameDirectionDescriptionpll_ref_clkInput PLL reference clock pll_ref_clk_out for RLDRAM 3IF_PLL_REF_CLK_OUT_DESCTable : pll_ref_clk_outInterface type: Clock OutputPort pll_locked for RLDRAM 3IF_PLL_LOCKED_DESCTable : pll_lockedInterface type: ConduitPort pll_extra_clk_0 for RLDRAM 3IF_PLL_EXTRA_CLK_0_DESCTable : pll_extra_clk_0Interface type: Clock OutputPort pll_extra_clk_1 for RLDRAM 3IF_PLL_EXTRA_CLK_1_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide100Table : pll_extra_clk_1Interface type: Clock OutputPort pll_extra_clk_2 for RLDRAM 3IF_PLL_EXTRA_CLK_2_DESCTable : pll_extra_clk_2Interface type: Clock OutputPort pll_extra_clk_3 for RLDRAM 3IF_PLL_EXTRA_CLK_3_DESCTable : pll_extra_clk_3Interface type: Clock OutputPort oct for RLDRAM 3OCT interfaceTable : octInterface type: ConduitPort NameDirectionDescriptionoct_rzqinInputCa librated On-Chip Termination (OCT) RZQ input mem for RLDRAM 3Interface between FPGA and external memoryTable : memInterface type: ConduitPort NameDirectionDescriptionmem_ckOutputCK clockmem_ck_nOutputCK clock (negative leg)mem_dkOutputDK clockmem_dk_nOutputDK clock (negative leg) 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide101Port NameDirectionDescriptionmem_aOutputAddre ssmem_baOutputBank addressmem_cs_nOutputChip selectmem_rmOutputRank multiplication for LRDIMM. Typically, mem_rm[0] andmem_rm[1] connect to CS2# and CS3# of the memorybuffer of all LRDIMM commandmem_reset_nOutputAsynchronous resetmem_ref_nOutputREF commandmem_dmOutputWrite data maskmem_dqBidirectionalRead/write datamem_qkInputRead data clockmem_qk_nInputRead data clock (negative leg) status for RLDRAM 3PHY calibration status interfaceTable : statusInterface type: ConduitPort NameDirectionDescriptionlocal_cal_succes sOutputWhen high, indicates that PHY calibration was successfullocal_cal_failOutputWhen high, indicates that PHY calibration afi_reset_n for RLDRAM 3AFI reset interfaceTable : afi_reset_nInterface type: Reset OutputPort NameDirectionDescriptionafi_reset_nOutpu tReset for the AFI clock domain. Asynchronous assertion andsynchronous afi_clk for RLDRAM 3AFI clock interfaceTable : afi_clkInterface type: Clock OutputPort NameDirectionDescriptionafi_clkOutputClo ck for the Altera PHY Interface (AFI)3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User afi_half_clk for RLDRAM 3AFI half-rate clock interfaceTable : afi_half_clkInterface type: Clock OutputPort NameDirectionDescriptionafi_half_clkOutp utClock running at half the frequency of the AFI clock afi for RLDRAM 3Altera PHY Interface (AFI)Table : afiInterface type: ConduitPort NameDirectionDescriptionafi_cal_successO utputSignals calibration successful completionafi_cal_failOutputSignals calibration failureafi_cal_reqInputWhen asserted, the interface is recalibratedafi_rlatOutputLatency in afi_clk cycles between read command and readdata validafi_wlatOutputLatency in afi_clk cycles between write command and writedata validafi_addrInputAddressafi_baInputBank addressafi_cs_nInputChip selectafi_we_nInputWE commandafi_rst_nInputAsynchronous resetafi_ref_nInputREF commandafi_dmInputWrite data maskafi_wdata_validInputAsserted by the controller to indicate that afi_wdatacontains valid write dataafi_wdataInputWrite dataafi_rdata_en_fullInputAsserted by the controller to indicate the amount of relevantread data expectedafi_rdataOutputRead dataafi_rdata_validOutputAsserted by the PHY to indicate that afi_rdata contains validread dataafi_rrankInputAsserted by the controller to indicate which rank is beingread from, to control shadow register switchingafi_wrankInputAsserted by the controller to indicate which rank is beingwritten to, to control shadow register switching3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User cal_debug_reset_n for RLDRAM 3User calibration debug clock domain reset interfaceTable : cal_debug_reset_nInterface type: Reset InputPort NameDirectionDescriptioncal_debug_reset_ nInputReset for the user clock connecting to the Avalon calibrationdebug bus. Asynchronous assertion and cal_debug_clk for RLDRAM 3User calibration debug clock interfaceTable : cal_debug_clkInterface type: Clock InputPort NameDirectionDescriptioncal_debug_clkInp utUser clock cal_debug_out_reset_n for RLDRAM 3User calibration debug clock domain reset interfaceTable : cal_debug_out_reset_nInterface type: Reset OutputPort NameDirectionDescriptioncal_debug_out_re set_nOutputReset for the user clock connecting to the Avalon calibrationdebug_out bus. Asynchronous assertion and cal_debug_out_clk for RLDRAM 3User calibration debug clock interfaceTable : cal_debug_out_clkInterface type: Clock OutputPort NameDirectionDescriptioncal_debug_out_cl kOutputUser clock clks_sharing_master_out for RLDRAM 3Core clocks sharing master interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide104Table : clks_sharing_master_outInterface type: ConduitPort NameDirectionDescriptionclks_sharing_mas ter_outOutputThis port should fanout to all the core clocks sharing clks_sharing_slave_in for RLDRAM 3Core clocks sharing slave interfaceTable : clks_sharing_slave_inInterface type: ConduitPort NameDirectionDescriptionclks_sharing_sla ve_inInputThis port should be connected to the core clocks hps_emif for RLDRAM 3Conduit between Hard Processor Subsystem and memory interfaceTable : hps_emifInterface type: ConduitPort NameDirectionDescriptionhps_to_emifInput Signals coming from Hard Processor Subsystem to thememory interfaceemif_to_hpsOutputSignals going to Hard Processor Subsystem from thememory interfacehps_to_emif_gpInputSignals coming from Hard Processor Subsystem GPIO to thememory interfaceemif_to_hps_gpOutputSignals going to Hard Processor Subsystem GPIO from thememory cal_debug for RLDRAM 3Calibration debug interfaceTable : cal_debugInterface type: Avalon Memory-Mapped SlavePort NameDirectionDescriptioncal_debug_waitre questOutputWait-request is asserted when controller is busycal_debug_readInputRead request signalcal_debug_writeInputWrite request signalcal_debug_addrInputAddress for the read/write requestcal_debug_read_dataOutputRead 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide105Port NameDirectionDescriptioncal_debug_write_ dataInputWrite datacal_debug_byteenableInputByte-enable for write datacal_debug_read_data_validOutputIndic ates whether read data is cal_debug_out for RLDRAM 3Calibration debug interfaceTable : cal_debug_outInterface type: Avalon Memory-Mapped MasterPort NameDirectionDescriptioncal_debug_out_wa itrequestInputWait-request is asserted when controller is busycal_debug_out_readOutputRead request signalcal_debug_out_writeOutputWrite request signalcal_debug_out_addrOutputAddress for the read/write requestcal_debug_out_read_dataInputRead datacal_debug_out_write_dataOutputWrite datacal_debug_out_byteenableOutputByte-e nable for write datacal_debug_out_read_data_validInputIn dicates whether read data is generic_clk for RLDRAM 3IF_GENERIC_CLK_DESCTable : generic_clkInterface type: Clock InputPort generic_reset_n for RLDRAM 3IF_GENERIC_RESET_DESCTable : generic_reset_nInterface type: Reset InputPort generic_conduit_reset_n for RLDRAM 3IF_GENERIC_CONDUIT_RESET_DESC3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide106Table : generic_conduit_reset_nInterface type: ConduitPort AFI SignalsThe following tables list Altera PHY interface (AFI) signals grouped according to each table, the Direction column denotes the direction of the signal relative to thePHY. For example, a signal defined as an output passes out of the PHY to thecontroller. The AFI specification does not include any bidirectional all signals are used for all AFI Clock and Reset SignalsThe AFI interface provides up to two clock signals and an asynchronous reset and Reset Signals Signal NameDirectionWidthDescriptionafi_clkOutp ut1Clock with which all data exchanged on the AFI busis synchronized. In general, this clock is referred toas full-rate, half-rate, or quarter-rate, depending onthe ratio between the frequency of this clock andthe frequency of the memory device signal that runs at half the speed of theafi_clk. The controller uses this signal when thehalf-rate bridge feature is in use. This signal reset output signal. You mustsynchronize this signal to the clock domain in whichyou use AFI Address and Command SignalsThe address and command signals for AFI encode read/write/configurationcommands to send to the memory device. The address and command signals aresingle-data rate and Command Signals Signal NameDirectionWidthDescriptionafi_addrInp utAFI_ADDR_WIDTHAddress or CA bus (LPDDR3 only).ADDR_RATE_RATIO is 2 forLPDDR3 CA group (DDR4 only).afi_baInputAFI_BANKADDR_WIDTHBank address. (Not applicable forLPDDR3.) 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide107Signal NameDirectionWidthDescriptionafi_ckeInpu tAFI_CLK_EN_WIDTHClock select signal. (The number ofchip selects may not match thenumber of ranks; for example,RDIMMs and LRDIMMs require aminimum of 2 chip select signalsfor both single-rank and dual-rankconfigurations. Consult yourmemory device data sheet forinformation about chip select signalwidth.) (Matches the number ofranks for LPDDR3.)afi_ras_nInputAFI_CONTROL_WIDTHR AS# (for DDR3 memory devices.)afi_we_nInputAFI_CONTROL_WIDTHW E# (for DDR3 memory devices.)afi_rw_nInputAFI_CONTROL_WIDTH * 2RWA/B# (QDR-IV).afi_cas_nInputAFI_CONTROL_WIDTH CAS# (for DDR3 memory devices.)afi_act_nInputAFI_CONTROL_WIDTH ACT# (DDR4).afi_rst_nInputAFI_CONTROL_WIDTHRE SET# (for DDR3 and DDR4memory devices.)afi_odtInputAFI_CLK_EN_WIDTHOn- die termination signal for DDR3,and LPDDR3 memory devices. (Donot confuse this memory devicesignal with the FPGA s internal on-chip termination signal.)afi_parInputAFI_CS_WIDTHAddress and command parity input.(DDR4)Address parity input. (QDR-IV)afi_ainvInputAFI_CONTROL_WIDTHAd dress inversion. (QDR-IV)afi_mem_clk_disableInputAFI_CLK_ PAIR_COUNTWhen this signal is asserted,mem_clk and mem_clk_n aredisabled. This signal is used in low-power (for QDR II/II+ memorydevices.)afi_rps_nOutputAFI_CS_WID THRPS (for QDR II/II+ memorydevices.) AFI Write Data SignalsWrite Data Signals for AFI control the data, data mask, and strobe signals passedto the memory device during write Data SignalsSignal NameDirectionWidthDescriptionafi_dqs_bur stInputAFI_RATE_RATIOControls the enable on the strobe(DQS) pins for DDR3 and LPDDR3memory devices. When this signalis asserted, mem_dqs andmem_dqsn are 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide108Signal NameDirectionWidthDescriptionThis signal must be asserted beforeafi_wdata_valid to implement thewrite preamble, and must be drivenfor the correct duration to generatea correctly timed mem_dqs data valid signal. This signalcontrols the output enable on thedata and data mask data signal to send to thememory device at double-datarate. This signal controls the PHY smem_dq mask. This signal controls thePHY s mem_dm signal for DDR3and LPDDR3 memory devices.)Also directly controls the PHY'smem_dbi signal for mem_dm and mem_dbifeatures share the same port onthe memory mask. This signal controls thePHY s mem_bws_n signal forQDR II/II+ memory * 2Data inversion. It directly controlsthe PHY's mem_dinva/b signal forQDR-IV AFI Read Data SignalsRead Data Signals for AFI control the data sent from the memory device duringread Data SignalsSignal NameDirectionWidthDescriptionafi_rdata_e n_fullInputAFI_RATE_RATIORead data enable full. Indicates that thememory controller is currently performinga read operation. This signal is held highfor the entire read this signal isaligned to even clock cycles, it is possibleto use 1-bit even in half-rate mode ( ,AFI_RATE=2).afi_rdataOutputAFI_DQ_WIDTH Read data from the memory device. Thisdata is considered valid only whenafi_rdata_valid is asserted by the data valid. When asserted, thissignal indicates that the afi_rdata bus this signal is aligned to even clockcycles, it is possible to use 1-bit even inhalf-rate mode ( , AFI_RATE=2).3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User AFI Calibration Status SignalsThe PHY instantiates a sequencer which calibrates the memory interface with thememory device and some internal components such as read FIFOs and valid sequencer reports the results of the calibration process to the controller throughthe Calibration Status Signals in the AFI Status SignalsSignal NameDirectionWidthDescriptionafi_cal_suc cessOutput1Asserted to indicate that calibration hascompleted to indicate that calibration a synchronous reset for thesequencer. When this signal is asserted,the sequencer returns to the reset state;when this signal is released, a newcalibration sequence required write latency in afi_clkcycles, between address/command andwrite data being issued at the PHY/controller interface. The afi_wlat valuecan be different for different groups; eachgroup s write latency can range from 0 to63. If write latency is the same for allgroups, only the lowest 6 bits (1)OutputAFI_RLAT_WIDTHThe required read latency in afi_clk cyclesbetween address/command and readdata being returned to the PHY/controllerinterface. Values can range from 0 to to afi_rlat signal is not supported for PHY-only designs. Instead, you can sample the afi_rdata_valid signal todetermine when valid read data is AFI Tracking Management SignalsWhen tracking management is enabled, the sequencer can take control over the interface at given intervals, and issue commands to the memory device to trackthe internal DQS Enable signal alignment to the DQS signal returning from thememory device. The tracking management portion of the AFI interface provides ameans for the sequencer and the controller to exchange handshake Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide110Table Management Signals Signal NameDirectionWidthDescriptionafi_ctl_ref resh_doneInput4Handshaking signal from controller totracking manager, indicating that arefresh has occurred and waiting for signal from sequencer tocontroller, indicating when DQS trackingis in signal from controller totracking manager, indicating that it hasexited low power state without a periodicrefresh, and waiting for AFI Shadow Register Management SignalsShadow registers are a feature that enables high-speed multi-rank support. Shadowregisters allow the sequencer to calibrate each rank separately, and save thecalibrated settings such as deskew delay-chain configurations of each rank in itsown set of shadow a rank-to-rank switch, the correct set of calibrated settings is restored just intime to optimize the data valid window. The PHY relies on additional AFI signals tocontrol which set of shadow registers to Register Management SignalsSignal NameDirectionWidthDescriptionafi_wrankIn putAFI_WRANK_WIDTHSignal from controllerspecifying which rank thewrite data is going to. Thesignal timing is identical tothat of afi_dqs_burst. Thatis, afi_wrank must beasserted at the same timeand must last the sameduration as theafi_dqs_burst from controllerspecifying which rank isbeing read. The signal mustbe asserted at the sametime as the afi_rdata_ensignal when issuing a readcommand, but unlikeafi_rdata_en, afi_rrank isstateful. That is, onceasserted, the signal valuemust remain unchangeduntil the controller issues anew read command to adifferent Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide111Both the afi_wrank and afi_rrank signals encode the rank being accessed using theone-hot scheme ( in a quad-rank interface, 0001, 0010, 0100, 1000 refer to the1st, 2nd, 3rd, 4th rank respectively). The ordering within the bus is the same as otherAFI signals. Specifically the bus is ordered by time slots, for example:Half-rate afi_w/rrank = {T1, T0}Quarter-rate afi_w/rrank = {T3, T2, T1, T0}Where Tx is a number of rank-bit words that one-hot encodes the rank being accessedat the yth full-rate Requirements for Shadow Register SupportTo ensure that the hardware has enough time to switch from one shadow register toanother, the controller must satisfy the following minimum rank-to-rank-switch delays(tRTRS): Two read commands going to different ranks must be separated by a minimum of3 full-rate cycles (in addition to the burst length delay needed to avoid collision ofdata bursts). Two write commands going to different rank must be separated by a minimum of4 full-rate cycles (in addition to the burst length delay needed to avoid collision ofdata bursts).The FPGA device supports a maximum of 4 sets of shadow registers, each for anindependent set of timings. More than 4 ranks are supported if those ranks have fouror fewer sets of independent timing. For example, the rank multiplication mode of anLRDIMM allows more than one physical rank to share a set of timing data as a singlelogical rank. Therefore the device can support up to 4 logical ranks, though thatmeans more than 4 physical AFI Timing AFI Address and Command Timing DiagramsDepending on the ratio between the memory clock and the PHY clock, differentnumbers of bits must be provided per PHY clock on the AFI interface. The followingfigures illustrate the AFI address/command waveforms in full, half and quarter waveforms show how the AFI command phase corresponds to the memorycommand output. AFI command 0 corresponds to the first memory command slot, AFIcommand 1 corresponds to the second memory command slot, and so Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide112Figure Address and Command Full-Ratemem_clkmem_cs_nmem_ckemem_ras_n mem_cas_nmem_we_nafi_clkafi_cs_nafi_ckea fi_ras_nafi_cas_nafi_we_nAFI InterfaceMemory Interface3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide113Figure Address and Command Half-Ratemem_clkmem_cs_nmem_ckemem_ras_n mem_cas_nmem_we_nafi_clkafi_cs_n[1]afi_c s_n[0]afi_cke[1]afi_cke[0]afi_ras_n[1]af i_ras_n[0]afi_cas_n[1]afi_cas_n[0]afi_we _n[1]afi_we_n[0]AFI InterfaceMemory Interface100111111011110111013 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide114Figure Address and Command Quarter-Ratemem_clkmem_cs_nmem_ckemem_ra s_nmem_cas_nmem_we_nafi_clkAFI InterfaceMemory Interfaceafi_cs_n[3]afi_cs_n[2]afi_cs_n[ 1]afi_cs_n[0]01100110afi_cke[3]afi_cke[2 ]afi_cke[1]afi_cke[0]11111111afi_ras_n[3 ]afi_ras_n[2]afi_ras_n[1]afi_ras_n[0]111 10110afi_cas_n[3]afi_cas_n[2]afi_cas_n[1 ]afi_cas_n[0]01101111afi_we_n[3]afi_we_n [2]afi_we_n[1]afi_we_n[0] AFI Write Sequence Timing DiagramsThe following timing diagrams illustrate the relationships between the write commandand corresponding write data and write enable signals, in full, half, and quarter half rate and quarter rate, when the write command is sent on the first memoryclock in a PHY clock (for example, afi_cs_n[0] = 0), that access is called alignedaccess; otherwise it is called unaligned access. You may use either aligned orunaligned access, or you may use both, but you must ensure that the distance3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide115between the write command and the corresponding write data are constant on theAFI interface. For example, if a command is sent on the second memory clock in a PHYclock, the write data must also start at the second memory clock in a PHY sequences with wlat=0Figure Write Data Full-Rate, wlat=0WRWRWRABCDEFMNOPQRafi_clkafi_comma ndafi_wdata_validafi_wdataafi_dmThe following diagrams illustrate both aligned and unaligned access. The first threewrite commands are aligned accesses where they were issued on LSB ofafi_command. The fourth write command is unaligned access where it was issued ona different command slot. AFI signals must be shifted accordingly, based on thecommand Write Data Half-Rate, wlat=0NOPNOPNOPafi_clkafi_command[1]WRWR WRafi_command[0]NOPWR111afi_wdata_valid[ 1]110afi_wdata_valid[0]1101BDGafi_wdata[ 1]ACafi_wdata[0]FEHNPSafi_dm[1]MOafi_dm[ 0]RQT3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide116Figure Write Data Quarter-Rate, wlat=0NOPNOPWRafi_clkafi_command[3]NOPNO PNOPafi_command[2]NOPNOP111afi_wdata_val id[3]110afi_wdata_valid[2]1101DHAafi_wda ta[3]CGafi_wdata[2]LKDPTMafi_dm[3]OSafi_ dm[2]XWPNOPNOPNOPafi_command[1]WRWRNOPaf i_command[0]NOPWR110afi_wdata_valid[1]11 0afi_wdata_valid[0]1111BFCafi_wdata[1]AE afi_wdata[0]JIBNROafi_dm[1]MQafi_dm[0]VU NWrite sequences with wlat=non-zeroThe afi_wlat is a signal from the PHY. The controller must delay afi_dqs_burst,afi_wdata_valid, afi_wdata and afi_dm signals by a number of PHY clock cyclesequal to afi_wlat, which is a static value determined by calibration before the PHYasserts cal_success to the controller. The following figures illustrate the cases whenwlat=1. Note that wlat is in the number of PHY clocks and therefore wlat=1 equals 1,2, and 4 memory clocks delay, respectively, on full, half and quarter Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide117Figure Write Data Full-Rate, wlat=1WRWRWRABCDEFMNOPQRafi_clkafi_comma ndafi_wdata_validafi_wdataafi_dmFigure Write Data Half-Rate, wlat=1NOPNOPNOPafi_clkafi_command[1]WRWR WRafi_command[0]NOPWR111afi_wdata_valid[ 1]110afi_wdata_valid[0]1101BDGafi_wdata[ 1]ACafi_wdata[0]FEHNPSafi_dm[1]MOafi_dm[ 0]RQT3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide118Figure Write Data Quarter-Rate, wlat=1NOPNOPWRafi_clkafi_command[3]NOPNO PNOPafi_command[2]NOPNOP111afi_wdata_val id[3]110afi_wdata_valid[2]1101DHAafi_wda ta[3]CGafi_wdata[2]LKDPTMafi_dm[3]OSafi_ dm[2]XWPNOPNOPNOPafi_command[1]WRWRNOPaf i_command[0]NOPWR110afi_wdata_valid[1]11 0afi_wdata_valid[0]1111BFCafi_wdata[1]AE afi_wdata[0]JIBNROafi_dm[1]MQafi_dm[0]VU NDQS burstThe afi_dqs_burst signal must be asserted one or two complete memory clockcycles earlier to generate DQS preamble. DQS preamble is equal to one-half and one-quarter AFI clock cycles in half and quarter rate, DQS preamble of two is required in DDR4, when the write preamble is set to twoclock following diagrams illustrate how afi_dqs_burst must be asserted in full, half, andquarter-rate Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide119Figure DQS Burst Full-Rate, wlat=1WRWRWRABCDEFMNOPQRafi_clkafi_comma ndafi_wdata_validafi_wdataafi_dmafi_dqs_ burstFigure DQS Burst Half-Rate, wlat=1NOPNOPNOPafi_clkafi_command[1]WRWR WRafi_command[0]NOPWR111afi_wdata_valid[ 1]110afi_wdata_valid[0]1101BDGafi_wdata[ 1]ACafi_wdata[0]FEHNPSafi_dm[1]MOafi_dm[ 0]RQTafi_dqs_burst[1]afi_dqs_burst[0]101 110111111013 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide120Figure DQS Burst Quarter-Rate, wlat=1NOPNOPWRafi_clkafi_command[3]NOPNO PNOPafi_command[2]NOPNOP111afi_wdata_val id[3]110afi_wdata_valid[2]1101DHAafi_wda ta[3]CGafi_wdata[2]LKDPTMafi_dm[3]OSafi_ dm[2]XWPNOPNOPNOPafi_command[1]WRWRNOPaf i_command[0]NOPWR110afi_wdata_valid[1]11 0afi_wdata_valid[0]1111BFCafi_wdata[1]AE afi_wdata[0]JIBNROafi_dm[1]MQafi_dm[0]VU Nafi_dqs_burst[3]afi_dqs_burst[2]1011101 1111101afi_dqs_burst[1]0101101afi_dqs_bu rst[0]0101101Write data sequence with DBI (DDR4 and QDRIV only)The DDR4 write DBI feature is supported in the PHY, and when it is enabled, the PHYsends and receives the DBI signal without any controller involvement. The sequence isidentical to non-DBI scenarios on the AFI Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide121Write data sequence with CRC (DDR4 only)When the CRC feature of the PHY is enabled and used, the controller ensures at leastone memory clock cycle between write commands, during which the PHY inserts theCRC data. Sending back to back write command would cause functional failure. Thefollowing figures show the legal sequences in CRC marked as 0 and RESERVE must be observed by the controller; no informationis allowed on those Write Data with CRC Half-Rate, wlat=2NOPNOPNOPafi_clkafi_command[1]WRWR WRafi_command[0]111afi_wdata_valid[1]110 afi_wdata_valid[0]1101BDGafi_wdata[1]ACa fi_wdata[0]FEHNPafi_dm[1]MOafi_dm[0]afi_ dqs_burst[1]afi_dqs_burst[0]101101111110 110101101111ReserveReserveReserveReserve JHILSRQTReserveReserveVWUX3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide122Figure Write Data with CRC Quarter-Rate, wlat=2NOPNOPNOPafi_clkafi_command[1]WRWR WRafi_command[0]BDGafi_wdata[3]ACafi_wda ta[2]FEHafi_dqs_burst[3]afi_dqs_burst[2] 101101111011010ReserveReserveReserveJMIL afi_dqs_burst[1]0101110afi_dqs_burst[0]0 1011101111afi_wdata_valid[3]afi_wdata_va lid[2]111111011010afi_wdata_valid[1]1111 0afi_wdata_valid[0]11110111BDACKPONReser veReserveafi_wdata[1]afi_wdata[0]BDGafi_ dm[3]ACafi_dm[2]FEHReserveReserveReserve JMILBDACKPONReserveReserveafi_dm[1]afi_d m[0] AFI Read Sequence Timing DiagramsThe following waveforms illustrate the AFI write data waveform in full, half, andquarter-rate, afi_rdata_en_full signal must be asserted for the entire read burstoperation. The afi_rdata_en signal need only be asserted for the intended Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide123Aligned and unaligned access for read commands is similar to write commands;however, the afi_rdata_en_full signal must be sent on the same memory clock ina PHY clock as the read command. That is, if a read command is sent on the secondmemory clock in a PHY clock, afi_rdata_en_full must also be asserted, startingfrom the second memory clock in a PHY Read Data Full-RateRDRDRDABCDEFafi_clkafi_commanda fi_rdata_en_fullafi_rdataafi_rdata_valid The following figure illustrates that the second and third reads require only the firstand second half of data, respectively. The first three read commands are alignedaccesses where they are issued on the LSB of afi_command. The fourth readcommand is unaligned access, where it is issued on a different command slot. AFIsignals must be shifted accordingly, based on command Read Data Half-RateNOPNOPRDafi_clkafi_command[1]RD RDNOPafi_command[0]NOPRD111afi_rdata_en_ full[1]110afi_rdata_en_full[0]1101BDGafi _rdata[1]ACafi_rdata[0]FEH111afi_rdata_v alid[1]11afi_rdata_valid[0]111In the following figure, the first three read commands are aligned accesses wherethey are issued on the LSB of afi_command. The fourth read command is unalignedaccess, where it is issued on a different command slot. AFI signals must be shiftedaccordingly, based on command Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide124Figure Read Data Quarter-RateNOPNOPNOPafi_clkafi_command[ 1]RDRDNOPafi_command[0]NOPRD111afi_rdata _en_full[3]110afi_rdata_en_full[2]1101DH Mafi_rdata[3]CGafi_rdata[2]LKP11afi_rdat a_valid[3]11afi_rdata_valid[2]11NOPNOPNO Pafi_command[2]NOPNOPNOPRDafi_command[3] NOP110afi_rdata_en_full[1]11110afi_rdata _en_full[0]11BFOafi_rdata[1]AEafi_rdata[ 0]JIN11afi_rdata_valid[1]111afi_rdata_va lid[0] AFI Calibration Status Timing DiagramThe controller interacts with the PHY during calibration at power-up and power-up, the PHY holds afi_cal_success and afi_cal_fail 0 until calibrationis done, when it asserts afi_cal_success, indicating to controller that the PHY isready to use and afi_wlat and afi_rlat signals have valid recalibration, the controller asserts afi_cal_req, which triggers the samesequence as at power-up, and forces recalibration of the Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide125Figure WorkingController WorkingPHY StatusCalibratingRe-CalibratingAFI Intel Stratix 10 Memory Mapped Register (MMR) TablesThe address buses to read and write from the MMR registers are 10 bits wide, whilethe read and write data buses are configured to be 32 bits. The Bits Register Linkcolumn in the table below provides the mapping on the width of the data read withinthe 32-bit bus. The reads and writes are always performed using the 32-bit-wide SummaryRegisterAddress 32-bit BusBits Register 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide126RegisterAddress 32-bit BusBits Register Linksideband64932sideband75032sideband85 132sideband95232sideband105332sideband11 5432sideband125532sideband135632sideband 145732dramsts5932niosreserve06832niosres erve16932sideband167932ecc313032ecc41443 2ecc514532ecc614632ecc714732ecc814832Not e: Addresses are in decimal ctrlcfg0address=10(32 bit)FieldBit HighBit LowDescriptionAccesscfg_mem_type30Indica tes memory type. "0000" forDDR3 SDRAM, "0001" for DDR4SDRAM, and "0010" for dimm Command Address ctrlcfg13 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide127address=11(32 bit)FieldBit HighBit the order for addressinterleaving. This is related tomappings between Avalon-MMaddress and the SDRAM address. "00"- chip, row, bank(BG, BA), column;"01" - chip, bank(BG, BA), row,column; "10"-row, chip, bank(BG,BA), the generation and checking the generation and checking the generation and checking the generation and checking the generation and checking bit controls whether thecontroller can reorder operations tooptimize SDRAM bandwidth. It shouldgenerally be set to a bit controls whether thecontroller needs to reorder the readreturn bit controls whether thecontroller needs to reorder the readreturn bit controls whether thecontroller needs to reorder the readreturn bit controls whether thecontroller needs to reorder the readreturn bit controls whether thecontroller needs to reorder the readreturn bit controls whether thecontroller can reorder read the number of DRAM bursttransactions an individual transactionwill allow to reorder ahead of it beforeits priority is raised in the to 1 to enable DRAM operation ifDM pins are to 1 to enable DRAM operation ifDM pins are 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide128FieldBit HighBit LowDescriptionAccesscfg_dbc1_enable_dm28 28Set to 1 to enable DRAM operation ifDM pins are to 1 to enable DRAM operation ifDM pins are to 1 to enable DRAM operation ifDM pins are dramtiming0address=20(32 bit)FieldBit HighBit LowDescriptionAccesscfg_tcl60Memory read caltiming0address=31(32 bit)FieldBit HighBit LowDescriptionAccesscfg_t_param_act_to_r dwr50Activate to Read/Write to to activate timing on to activate timing on differentbanks, for DDR4 same bank to activate timing on differentbank groups, DDR4 caltiming1address=32(32 bit)FieldBit HighBit LowDescriptionAccesscfg_t_param_rd_to_rd 50Read to read command timing onsame to read command timing ondifferent 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide129FieldBit HighBit LowDescriptionAccesscfg_t_param_rd_to_rd _diff_bg1712Read to read command timing ondifferent to read command timing onsame to write command timing ondifferent caltiming2address=33(32 bit)FieldBit HighBit LowDescriptionAccesscfg_t_param_rd_to_wr _diff_bg50Read to write command timing ondifferent bank to precharge command command with autoprecharge todata valid to write command timing onsame to write command timing ondifferent caltiming3address=34(32 bit)FieldBit HighBit LowDescriptionAccesscfg_t_param_wr_to_wr _diff_bg50Write to write command timing ondifferent bank to read command to read command timing ondifferent to read command timing ondifferent bank to precharge command caltiming43 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide130address=35(32 bit)FieldBit HighBit LowDescriptionAccesscfg_t_param_wr_ap_to _valid50Write with autoprecharge to validcommand to valid command all to banks being ready forbank activation Refresh to valid DRAM down to valid bank caltiming9address=40(32 bit)FieldBit HighBit LowDescriptionAccesscfg_t_param_4_act_to _act70The four-activate window dramaddrwaddress=42(32 bit)FieldBit HighBit LowDescriptionAccesscfg_col_addr_width40 The number of column address bitsfor the memory devices in yourmemory number of row address bits forthe memory devices in your number of bank address bits forthe memory devices in your number of bank group addressbits for the memory devices in yourmemory number of chip select addressbits for the memory devices in yourmemory sideband03 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide131address=43(32 bit)FieldBit HighBit LowDescriptionAccessmr_cmd_trigger00Mode Register Command asserted, indicates user requestto execute mode register clears bit to 0 whenoperation is completed. Registeroffset 37h and 38h must be properlyconfigured before requesting ModeRegister Command. Read offset 31hfor Mode Register Command sideband1address=44(32 bit)FieldBit HighBit LowDescriptionAccessmmr_refresh_req30Ran k Refresh Request. Whenasserted, indicates a refresh requestto the specific rank. Controller clearsthis bit to 0 when the refresh sideband2address=45(32 bit)FieldBit HighBit LowDescriptionAccessmmr_zqcal_long_req00 Long ZQ calibration request. Assertingthis bit sends a ZQ calibrationcommand to the memory device. Thisis a self-clearing bit, the controllersets this bit back to 0 when thecommand is sideband3address=46(32 bit)FieldBit HighBit LowDescriptionAccessmmr_zqcal_short_req0 0Short ZQ calibration of this bit sends the ZQcalibration command to the memorydevice. This is a self-clearing bit, thecontroller sets this bit back to 0 oncethe command is sideband43 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide132address=47(32 bit)FieldBit HighBit LowDescriptionAccessmmr_self_rfsh_req30S elf-refresh request. When asserted,indicates a self-refresh request toDRAM. All 4 bits must be asserted orde-asserted at the same time. Userclear to exit self sideband5address=48(32 bit)FieldBit HighBit LowDescriptionAccessmmr_dpd_mps_req00Dee p Power Down/Maximum PowerSaving request. Assertion of this bitinvokes the deep power down/maximum power saving mode. Youshould poll for the acknowledgesignal. When the acknowledge goeshigh, it indicates that the system hasentered deep power down/maximumpower saving mode. You may de-assert this bit to exit deep powerdown/maximum power saving mode,or keep this bit asserted to maintaindeep power down/maximum powersaving sideband6address=49(32 bit)FieldBit HighBit LowDescriptionAccessmr_cmd_ack00Register Command In Progress. Whenasserted, indicates Mode RegisterCommand in sideband7address=50(32 bit)FieldBit HighBit LowDescriptionAccessmmr_refresh_ack00Ref resh In signal for refreshrequest. Indicates that refresh is inprogress. Asserts when refreshrequest is sent out to PHY untiltRFC/t_param_arf_to_valid Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User sideband8address=51(32 bit)FieldBit HighBit LowDescriptionAccessmmr_zqcal_ack00ZQ Calibration in signal for ZQcalibration request. When asserted,indicates that ZQ Calibration is inprogress. Asserts when ZQ Calibrationis sent to the PHY until thetZQoper(t_param_zqcl_period) /tZQCS(t_param_zqcs_period) sideband9address=52(32 bit)FieldBit HighBit LowDescriptionAccessmmr_self_rfsh_ack00S elf-refresh In signal for the self-refresh request. A value of 1 indicatesthat memory is in self refresh sideband10address=53(32 bit)FieldBit HighBit LowDescriptionAccessmmr_dpd_mps_ack00Dee p Power Down/Maximum PowerSaving In Progress. Acknowledgementsignal for the deep power down/maximum power saving request. Avalue of 1 indicates that the memoryis in deep power down/maximumpower saving sideband11address=54(32 bit)FieldBit HighBit LowDescriptionAccessmmr_auto_pd_ack00Aut o Power Down In signal for autopower down. A value of 1 indicatesthat the memory is in auto powerdown Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User sideband12address=55(32 bit)FieldBit HighBit LowDescriptionAccessmr_cmd_type20Registe r command type. Indicates thetype of register - Mode Register Set (DDR3,DDR4, and LPDDR3)Others - Reservedmr_cmd_rank63Register command rank. Indicates therank targeted by the - Chip select 00010 - Chip select 10011 - Chip select 0 and chip select 11111 - all chip selectsMode Register Set - Any combinationof chip sideband13address=56(32 bit)FieldBit HighBit LowDescriptionAccessmr_cmd_opcode310Regi ster Command used for [26:20] Reserved[19:10] falling edge CA[9:0][9:4] rising edge CA[9:4][3:0] ReservedMRW: [19:12] is OP[7:0], [11:4] isMA[7:0]DDR4[26:24] C2:C0[23] ACT[22:21] BG1:BG0[20] Reserved[19:18] BA1 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide135FieldBit HighBit LowDescriptionAccess[17] A17[16] RAS#[15] CAS#[14] WE#[13:0] A13:A0MRS: [22:21] is BG1:BG0, [19:18] isBA1:BA0, [13:0] is Opcode[13:0]DDR3[26:21] Reserved[20:18] BA2:BA0[17] A14[16] RAS#[15] CAS#[14] WE#[13:0] A13:A0MRS: [19:18] is BA1:BA0, [13:0] isOpcode[13:0] sideband14address=57(32 bit)FieldBit HighBit LowDescriptionAccessmmr_refresh_cid31DDR 4 3DS Chip ID Refresh. Whenasserted, indicates the logical rankchip ID for 3DS refresh. (This field isnot applicable for DDR3 or LPDDR3.) dramstsaddress=59(32 bit)FieldBit HighBit LowDescriptionAccessphy_cal_success00Thi s bit is set to 1 if the PHYcalibrates bit is set to 1 if the PHY does notcalibrate niosreserve03 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide136address=68(32 bit)FieldBit HighBit LowDescriptionAccessnios_reserve0150Indi cates interface niosreserve1address=69(32 bit)FieldBit HighBit LowDescriptionAccessnios_reserve1150Indi cates ACDS sideband16address=79(32 bit)FieldBit HighBit LowDescriptionAccessmmr_3ds_refresh_ack3 10DDR4 3DS Refresh asserted, indicatesacklowledgement for the DDR4 [7:0] Refresh acknowledgement forlogical rank [7:0] for physical rank 0.[15:8] Refresh acknowledgement forlogical rank [7:0] for physical rank 1.[23:16] Refresh acknowledgement forlogical rank [7:0] for physical rank 2.[31:24] Refresh acknowledgement forlogical rank [7:0] for physical rank ecc3: ECC Error and Interrupt Configurationaddress=130(32 bit)FieldBit HighBit LowDescriptionAccesscfg_gen_sbe00A value of 1 enables the generate SBEfeature. Generates a single bit errorduring the write value of 1 enables the generateDBE feature. Generates a double biterror during the write value of 1 enables the interruptfeature. The interrupt signal notifies ifan error condition occurs. Thecondition is value of 1 masks the interruptsignal when SBE 3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide137FieldBit HighBit LowDescriptionAccesscfg_mask_dbe_intr44A value of 1 masks the interruptsignal when DBE value of 1 masks the interruptsignal when the auto correctioncommand can t be scheduled, due toback-pressure (FIFO full).Read/Writecfg_mask_hmi_intr66A value of 1 masks the interruptsignal when the hard memoryinterface asserts an interrupt signalvia the hmi_interrupt a vale of 1 to this self-clearingbit clears the interrupt signal, errorstatus, and ecc4: Status and Error Informationaddress=144(32 bit)FieldBit HighBit LowDescriptionAccesssts_ecc_intr00Indica tes the interrupt status; a valueof 1 indicates an interrupt the SBE status; a value of 1indicates SBE the DBE status; a value of 1indicates DBE the status of correctioncommand dropped; a value of 1indicates correction the number of times SBEerror has occurred. The counter the number of times DBEerror has occurred. The counter the number of timescorrection command has counter will ecc5: Address of Most Recent SBE/DBE3 Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide138address=145(32 bit)FieldBit HighBit LowDescriptionAccesssts_err_addr*310Addr ess of the mostrecent single-bit erroror double-bit ecc6: Address of Most Recent Correction Command Droppedaddress=146(32 bit)FieldBit HighBit LowDescriptionAccesssts_corr_dropped_add r310Address of the mostrecent correctioncommand ecc7: Extension for Address of Most Recent SBE/DBEaddress=147(32 bit)FieldBit HighBit LowDescriptionAccesssts_err_addr_ext20Ex tension for addressof the most recentsingle-bit error ordouble-bit ecc8: Extension for Address of Most Recent Correction CommandDroppedaddress=148(32 bit)FieldBit HighBit LowDescriptionAccesssts_corr_dropped_add r_ext20Extension for addressof the most recentcorrection Intel Stratix 10 EMIF IP End-User SignalsUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide1394 Intel Stratix 10 EMIF Simulating Memory IPTo simulate your design you require the following components: A simulator The simulator must be an Intel-supported VHDL or Verilog HDLsimulator: Aldec Riviera-Pro Cadence NC Sim Mentor Graphics* ModelSim Synopsys* VCS/VCS-MX A design using Intel s External Memory Interface (EMIF) IP An example driver or traffic generator (to initiate read and write transactions) A testbench and a suitable memory simulation modelThe Intel External Memory Interface IP is not compatible with the Platform DesignerTestbench System. Instead, use the simulation example design from your generatedIP to validate memory interface operation, or as a reference to create a fullsimulatable design, containing a memory interface, a memory model, and a trafficgenerator. For more information about the EMIF simulation design example, refer tothe Intel Stratix 10 EMIF IP Design Example User Simulation ModelsThere are two types of memory simulation models that you can use: Intel-provided generic memory modelThe Intel Quartus Prime software generates this model with the simulation exampledesign. The model adheres to all the memory protocol specifications, and can beparameterized. Vendor-specific memory modelVendor-specific memory models are simulation models for specific memorycomponents from memory vendors such as Micron and Samsung. You can obtain thesesimulation models from the memory vendor's : Intel does not provide support for vendor-specific memory LinksModifying the Example Driver to Replicate the Failure on page Simulation OptionsThe following simulation options are available with the example testbench to improvesimulation speed:UG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008Registered Full calibration Calibrates the same way as in hardware, and includes all phasesweeps, delay adjustments, and data : Intel Stratix 10 EMIF full calibration simulation will be available in a futurerelease of the Intel Quartus Prime software. Skip calibration Loads memory configuration settings and enters user mode,providing the fastest simulation : For proper simulation of DQS Tracking, you must enable full simulation options represent accurate controller efficiency and do not take intoaccount board skew. This may cause a discrepancy in the simulated interface latencynumbers. For more information regarding simulation assumptions and differencesbetween RTL simulation and post-fit implementation, refer to the Intel Stratix 10 EMIFIP Design Example User Simulation Times Using Intel Stratix 10 EMIF IPCalibration Mode/Run Time (1)Estimated Simulation TimeSmall Interface ( 8 Single Rank)Large Interface ( 72 Quad Rank)Full Full calibration Includes all phase/delay sweepsand centering20 minutes~ 1 daySkip Skip calibration Preloads calculated settings10 minutes25 minutesAbstract PHY Replace PHY and external memorymodel with a single abstract PHYmodel. IMPORTANT: External memorymodel is NOT used in this mode. NoI/O switching occurs to the externalmemory minute5 minutesNote to Table:1. Uses one loop of driver test. One loop of driver is approximately 600 read or write requests, with burst length up to Simulation times shown in this table are approximate measurements made using Synopsys VCS. Simulation times canvary considerably, depending on the IP configuration, the simulator used, and the computer or server LinksSimulation Walkthrough on page Simulation WalkthroughSimulation is a good way to determine the latency of your system. However, thelatency reflected in simulation may be different than the latency found on the boardbecause functional simulation does not take into account board trace delays anddifferent process, voltage, and temperature a given design on a given board, the latency found may differ by one clock cycle(for full-rate designs) or two clock cycles (for half-rate designs) upon resetting theboard. Different boards can also show different latencies even with the same Intel Stratix 10 EMIF Simulating Memory IPUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide141The Intel Stratix 10 EMIF IP supports functional simulation only. Functional simulationis supported at the RTL level after generating a post-fit functional simulation post-fit netlist for designs that contain Intel Stratix 10 EMIF IP is a hybrid of thegate level (for FPGA core) and RTL level (for the external memory interface IP). Youshould validate the functional operation of your design using RTL simulation, and thetiming of your design using timing perform functional simulation for an Intel Stratix 10 EMIF IP example design, locatethe example design files in the \<variation_name>_example_design can use the IP functional simulation model with any supported VHDL or VerilogHDL you have generated the memory IP, view the README. txt file located in the\<variation_name>_example_design directory for instructions on how togenerate the simulation example design for Verilog HDL or VHDL. Simulation filesetsfor both Verilog HDL and VHDL are located in\<variation_name>_example_design\sim. The file also explainshow to run simulation using the ModelSim* - Intel FPGA Edition. Simulation scripts forthe Mentor Graphics, Cadence, Aldec, and Synopsys simulators are provided; however,detailed instructions on how to perform simulation using these third-party simulatorsare not LinksSimulation Options on page Calibration ModesCalibration occurs shortly after the memory device is initialized, to compensate foruncertainties in the hardware system, including silicon PVT variation, circuit boardtrace delays, and skewed arrival times. Such variations are usually not present in anRTL simulation environment, resulting in two simulatable calibration modes: SkipCalibration mode (which is the default), and Full Calibration Calibration ModeIn Skip Calibration mode, the calibration processor assumes an ideal hardwareenvironment, where PVT variations, board delays, and trace skews are all of running the actual calibration routine, the calibration processor calculatesthe expected arrival time of read data based on the memory latency values enteredduring EMIF IP generation, resulting in reduced simulation time. Skip calibration modeis recommended for use during system development, because it allows you to focus oninteracting with the controller and optimizing your memory access patterns, thusfacilitating rapid RTL Calibration ModeFull Calibration mode simulates every stage of the calibration algorithm immediatelyafter memory device initialization. The calibration algorithm processes each datagroup sequentially and each pin in each group individually, causing simulation time toincrease with the number of data pins in your interface. You can observe how thecalibration algorithm compensates for various delays in the system by incorporatingyour own board delay model based on trace delays from your PCB design tools. Due tothe large simulation overhead, Full Calibration simulation mode is not recommendedfor rapid development of IP Intel Stratix 10 EMIF Simulating Memory IPUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide142VHDL SupportVHDL support for mixed-language simulators is implemented by generating the top-level wrapper for the core in VHDL, while all submodules are provided as clear textSystemVerilog set of precompiled device libraries is provided for use with the ModelSim - IntelFPGA Edition simulator, which is supplied with the Intel Quartus Prime normally provided as cleartext SystemVerilog files are encrypted usingIEEE Verilog HDL encryption for ModelSim - Intel FPGA Abstract PHY SimulationThe abstract PHY is a simulation model of the EMIF PHY that can decrease simulationtime by 3-10 times. The abstract PHY replaces the lane and the external memorymodel with a single model containing an internal memory array. No switching of theI/Os to the external memory model occurs when simulating with the abstract PHY reduces simulation time by two mechanisms: The Nios processor has been disabled and is replaced by HDL forces that areapplied at the beginning of simulation. The HDL forces are a minimum set ofregisters that configures the memory interface for simulation. The write and readlatency values applied by the HDL forces are not representative of the post-calibration values applied to the memory interface running on hardware. However,as long as the customer logic is Avalon and AFI-compliant, these values allow forsuccessful RTL simulation. The abstract PHY eliminates the need for full-speed clocks and thereforesimulation of the abstract PHY does not require full-speed clock simulation use the abstract PHY, enable Simulation Options Abstract PHY for fastsimulation on the Diagnostic tab during EMIF IP generation. When you enableAbstract PHY, the EMIF IP is configured as shown below. The PHY RTL and externalmemory model are disconnected from the data path and in their place is the abstractPHY containing an internal memory PHY Abstract PHYPHYRTLMemoryArrayExternalMemoryMemory ControllerCustomLogicExternal Memory Interface IPNote: You cannot observe the external memory device signals when you are using Intel Stratix 10 EMIF Simulating Memory IPUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide143Note: Abstract PHY does not reflect accurate latency Simulation ScriptsThe Intel Quartus Prime software generates three simulation scripts during projectgeneration for four different third party simulation tools Cadence, Synopsys, Aldec,and Mentor simulation scripts are located under the <project directory>\<varitation_name>_sim directory, in separate folders named after eachsupported simulator. The example designs also provide equivalent scripts after you runthe .tcl script from the project located in the\<variation_name>_example_design\sim Functional Simulation with Verilog HDLSimulation scripts for the Synopsys, Cadence, Aldec, and Mentor Graphics simulatorsare provided for you to run the example simulation scripts are located in the following main folder locations:Simulation scripts in the simulation folders are located as follows: <variation_name>_example_design\sim\mentor\ <variation_name>_example_design\sim\synopsys\vcs\ <variation_name>_example_design\sim\synopsys\vcsmx\ <variation_name>_example_design\sim\aldec\ <variation_name>_example_design\sim\cadence\ scripts in the <>_sim_folder are located as follows: <variation_name>_sim\mentor\ <variation_name>_sim\cadence\ <variation_name>_sim\synopsys\vcs\ <variation_name>_sim\synopsys\vcsmx\ <variation_name>_sim\aldec\ more information about simulating Verilog HDL or VHDL designs using commandlines, refer to the Mentor Graphics ModelSim and QuestaSim Support chapter involume 3 of the Intel Quartus Prime LinksModelSim - Intel FPGA Edition, ModelSim, and QuestaSim Functional Simulation with VHDLThe EMIF VHDL fileset is provided for customers that wish to generate the top-levelRTL instance of their EMIF IP cores in Intel Stratix 10 EMIF Simulating Memory IPUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide144Prior to Intel Quartus Prime version , the VHDL fileset was comprised entirely ofVHDL files. Beginning with Intel Quartus Prime version , only the top-level IPinstance file is guaranteed to be written in VHDL; submodules can still be deployed asVerilog/SystemVerilog (encrypted or plaintext) files, or VHDL files. Note that theModelSim - Intel FPGA Edition is no longer restricted to a single HDL language as ofIntel Quartus Prime ; however, some files may still be encrypted in order to beexcluded from the maximum unencrypted module limit of this the VHDL fileset consists of both VHDL and Verilog files, you must followcertain mixed-language simulation guidelines. The general guideline for mixed-language simulation is that you must always link the Verilog files (whether encryptedor not) against the Verilog version of the libraries, and the VHDL files (whetherSimGen-generated or pure VHDL) against the VHDL scripts for the Synopsys, Cadence, Aldec, and Mentor Graphics simulatorsare provided for you to run the example design. These simulation scripts are located inthe following main folder locations:Simulation scripts in the simulation folders are located as follows: <variation_name>_example_design\sim\mentor\ <variation_name>_example_design\sim\synopsys\vcsmx\ <variation_name>_example_design\sim\synopsys\vcs\ <variation_name>_example_design\sim\cadence\ <variation_name>_example_design\sim\aldec\ scripts in the <>_sim_folder are located as follows: <variation_name>_sim\mentor\ <variation_name>_sim\cadence\ <variation_name>_sim\synopsys\vcsmx\ <variation_name>_sim\aldec\ more information about simulating Verilog HDL or VHDL designs using commandlines, refer to the Mentor Graphics ModelSim and QuestaSim Support chapter involume 3 of the Intel Quartus Prime LinksModelSim - Intel FPGA Edition, ModelSim, and QuestaSim Simulating the Example DesignThis topic describes how to simulate the example design in Cadence, Synopsys,Mentor Graphics, and Aldec Intel Stratix 10 EMIF Simulating Memory IPUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide145To simulate the example design in the Intel Quartus Prime software using the Cadencesimulator, follow these steps:1. At the Linux* shell command prompt, change directory to<name>_example_design\sim\cadence2. Run the simulation by typing the following command at the command prompt:sh simulate the example design in the Intel Quartus Prime software using theSynopsys simulator, follow these steps:1. At the Linux shell command prompt, change directory to<name>_example_design\sim\synopsys\vcsmx2. Run the simulation by typing the following command at the command prompt:sh simulate the example design in the Intel Quartus Prime software using the MentorGraphics simulator, follow these steps:1. At the Linux or Windows shell command prompt, change directory to<name>_example_design\sim\mentor 2. Execute the script that automatically compiles and runs thesimulation by typing the following command at the Linux or Windows commandprompt:vsim -do the following command at the ModelSim command prompt:do : Intel does not provide the file for the example design with the EMIF simulate the example design in the Intel Quartus Prime software using the Aldecsimulator, follow these steps:1. At the Linux or Windows shell command prompt, change directory to<name>_example_design\sim\aldec 2. Execute the script that automatically compiles and runs thesimulation by typing the following command at the Linux or Windows commandprompt:vsim -do compile and elaborate the design after the script loads, type run -all to run the more information about simulation, refer to the Simulating Designs chapter involume 3 of the Intel Quartus Prime your Intel Quartus Prime project appears to be configured correctly but the exampletestbench still fails, check the known issues on the Intel FPGA Knowledge Base beforefiling a service Intel Stratix 10 EMIF Simulating Memory IPUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide146Related Links Simulating Intel FPGA Designs Intel FPGA Knowledge Base4 Intel Stratix 10 EMIF Simulating Memory IPUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide1475 Intel Stratix 10 EMIF IP for DDR3This chapter contains IP parameter descriptions, board skew equations, pin planninginformation, and board design guidance for Intel Stratix 10 external memoryinterfaces for Parameter DescriptionsThe following topics describe the parameters available on each tab of the IP parametereditor, which you can use to configure your Intel Stratix 10 EMIF IP DDR3 Parameters: GeneralTable : General / InterfaceDisplay NameDescriptionConfigurationSpecifies the configuration of the memory interface. The available optionsdepend on the protocol in use. Options include Hard PHY and HardController, Hard PHY and Soft Controller, or Hard PHY only. If youselect Hard PHY only, the AFI interface is exported to allow connection ofa custom memory controller or third-party IP. (Identifier:PHY_DDR3_CONFIG_ENUM)Instant iate two controllers sharing aPing Pong PHYSpecifies the instantiation of two identical memory controllers that share anaddress/command bus through the use of Ping Pong PHY. This parameter isavailable only if you specify the Hard PHY and Hard Controller this parameter is enabled, the IP exposes two independent Avaloninterfaces to the user logic, and a single external memory interface withdouble width for the data bus and the CS#, CKE, ODT, and CK/CK# signals.(Identifier: PHY_DDR3_USER_PING_PONG_EN)Table : General / ClocksDisplay NameDescriptionMemory clock frequencySpecifies the operating frequency of the memory interface in MHz. If youchange the memory frequency, you should update the memory latencyparameters on the Memory tab and the memory timing parameters on theMem Timing tab. (Identifier: PHY_DDR3_MEM_CLK_FREQ_MHZ)Use recommended PLL reference clockfrequencySpecifies that the PLL reference clock frequency is automatically calculatedfor best performance. If you want to specify a different PLL reference clockfrequency, uncheck the check box for this parameter. (Identifier:PHY_DDR3_DEFAULT_REF_CLK_FRE Q)PLL reference clock frequencyThis parameter tells the IP what PLL reference clock frequency the user willsupply. Users must select a valid PLL reference clock frequency from thelist. The values in the list can change when the memory interface frequencychanges and/or the clock rate of user logic changes. It is recommended UG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008RegisteredDisplay NameDescriptionuse the fastest possible PLL reference clock frequency because it leads tobetter jitter performance. Selection is required only if the user does notcheck the "Use recommended PLL reference clock frequency" option.(Identifier: PHY_DDR3_USER_REF_CLK_FREQ_MHZ)PLL reference clock jitterSpecifies the peak-to-peak jitter on the PLL reference clock source. Theclock source of the PLL reference clock must meet or exceed the followingjitter requirements: 10ps peak to peak, or RMS at 1e-12 BER, at 1e-16 BER. (Identifier: PHY_DDR3_REF_CLK_JITTER_PS)Clock rate of user logicSpecifies the relationship between the user logic clock frequency and thememory clock frequency. For example, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz, a quarter-rate interfacemeans that the user logic in the FPGA runs at 200MHz. (Identifier:PHY_DDR3_RATE_ENUM)Core clocks sharingWhen a design contains multiple interfaces of the same protocol, rate,frequency, and PLL reference clock source, they can share a common set ofcore clock domains. By sharing core clock domains, they reduce clocknetwork usage and avoid clock synchronization logic between share core clocks, denote one of the interfaces as "Master", and theremaining interfaces as "Slave". In the RTL, connect theclks_sharing_master_out signal from the master interface to theclks_sharing_slave_in signal of all the slave master and slave interfaces still expose their own output clock ports inthe RTL (for example, emif_usr_clk, afi_clk), but the physical signalsare equivalent, hence it does not matter whether a clock port from a masteror a slave is used. As the combined width of all interfaces sharing the samecore clock increases, you may encounter timing closure difficulty fortransfers between the FPGA core and the periphery.(Identifier: PHY_DDR3_CORE_CLKS_SHARING_ENUM)Specify additional core clocks based onexisting PLLDisplays additional parameters allowing you to create additional outputclocks based on the existing PLL. This parameter provides an alternativeclock-generation mechanism for when your design exhaustsavailable PLL resources. The additional output clocks that you create canbe fed into the core. Clock signals created with this parameter aresynchronous to each other, but asynchronous to the memory interface coreclock domains (such as emif_usr_clk or afi_clk). You must followproper clock-domain-crossing techniques when transferring data betweenclock domains. (Identifier: PLL_ADD_EXTRA_CLKS)Table : General / Clocks / Additional Core ClocksDisplay NameDescriptionNumber of additional core clocksSpecifies the number of additional output clocks to create from the PLL.(Identifier: PLL_USER_NUM_OF_EXTRA_CLKS)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_0Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_5)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_5)5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide149Table : General / Clocks / Additional Core Clocks / pll_extra_clk_1Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_6)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_6)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_2Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_7)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_7)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_3Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_8)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_8) Intel Stratix 10 EMIF IP DDR3 Parameters: MemoryTable : Memory / TopologyDisplay NameDescriptionMemory formatSpecifies the format of the external memory device. The following formatsare supported: Component - a Discrete memory device; UDIMM -Unregistered/Unbuffered DIMM where address/control, clock, and data areunbuffered; RDIMM - Registered DIMM where address/control and clockare buffered; LRDIMM - Load Reduction DIMM where address/control,clock, and data are buffered. LRDIMM reduces the load to increase memoryspeed and supports higher densities than RDIMM; SODIMM - Small OutlineDIMM is similar to UDIMM but smaller in size and is typically used forsystems with limited space. Some memory protocols may not be availablein all formats. (Identifier: MEM_DDR3_FORMAT_ENUM)DQ widthSpecifies the total number of data pins in the interface. The maximumsupported width is 144, or 72 in Ping Pong PHY mode. (Identifier:MEM_DDR3_DQ_WIDTH)DQ pins per DQS groupSpecifies the total number of DQ pins per DQS group. (Identifier:MEM_DDR3_DQ_PER_DQS)Number of clocksSpecifies the number of CK/CK# clock pairs exposed by the memoryinterface. Usually more than 1 pair is required for RDIMM/LRDIMM value of this parameter depends on the memory device selected; referto the data sheet for your memory device. (Identifier:MEM_DDR3_CK_WIDTH)Number of chip selectsSpecifies the total number of chip selects in the interface, up to a maximumof 4. This parameter applies to discrete components only. (Identifier:MEM_DDR3_DISCRETE_CS_WIDTH)N umber of DIMMsTotal number of DIMMs. (Identifier: MEM_DDR3_NUM_OF_DIMMS) 5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide150Display NameDescriptionNumber of physical ranks per DIMMNumber of ranks per DIMM. For LRDIMM, this represents the number ofphysical ranks on the DIMM behind the memory buffer (Identifier:MEM_DDR3_RANKS_PER_DIMM)Numb er of clock enables per DIMMNumber of clock enables ( CKE) per DIMM. Only applicable to registeredand load-reduced DIMMs. (Identifier: MEM_DDR3_CKE_PER_DIMM)Row address widthSpecifies the number of row address pins. Refer to the data sheet for yourmemory device. The density of the selected memory device determines thenumber of address pins needed for access to all available rows. (Identifier:MEM_DDR3_ROW_ADDR_WIDTH)Colu mn address widthSpecifies the number of column address pins. Refer to the data sheet foryour memory device. The density of the selected memory devicedetermines the number of address pins needed for access to all availablecolumns. (Identifier: MEM_DDR3_COL_ADDR_WIDTH)Bank address widthSpecifies the number of bank address pins. Refer to the data sheet for yourmemory device. The density of the selected memory device determines thenumber of bank address pins needed for access to all available banks.(Identifier: MEM_DDR3_BANK_ADDR_WIDTH)Enable DM pinsIndicates whether the interface uses data mask (DM) pins. This featureallows specified portions of the data bus to be written to memory (notavailable in x4 mode). One DM pin exists per DQS group. (Identifier:MEM_DDR3_DM_EN)Enable address mirroring for odd chip-selectsEnabling address mirroring for multi-CS discrete components. Typically usedwhen components are arranged in a clamshell layout. (Identifier:MEM_DDR3_DISCRETE_MIRROR_ADD RESSING_EN)Enable address mirroring for odd ranksEnabling address mirroring for dual-rank or quad-rank DIMM. (Identifier:MEM_DDR3_MIRROR_ADDRESSING_E N)ALERT# pin placementSpecifies placement for the mem_alert_n signal. If you select "I/O Lanewith Address/Command Pins", you can pick the I/O lane and pin indexin the add/cmd bank with the subsequent drop down menus. If you select"I/O Lane with DQS Group", you can specify the DQS group with whichto place the mem_alert_n pin. If you select "Automatically select alocation", the IP automatically selects a pin for the mem_alert_nsignal. If you select this option, no additional location constraints can beapplied to the mem_alert_n pin, or a fitter error will result duringcompilation. For optimum signal integrity, you should choose "I/O Lanewith Address/Command Pins". For interfaces containing multiplememory devices, it is recommended to connect the ALERT# pins togetherto the ALERT# pin on the FPGA. (Identifier:MEM_DDR3_ALERT_N_PLACEMENT_E NUM)DQS group of ALERT#Select the DQS group with which the ALERT# pin is placed. (Identifier:MEM_DDR3_ALERT_N_DQS_GROUP)T able : Memory / Latency and BurstDisplay NameDescriptionMemory CAS latency settingSpecifies the number of clock cycles between the read command and theavailability of the first bit of output data at the memory device. Overall readlatency equals the additive latency (AL) + the CAS latency (CL). Overallread latency depends on the memory device selected; refer to thedatasheet for your device. (Identifier: MEM_DDR3_TCL)Memory write CAS latency settingSpecifies the number of clock cycles from the release of internal write tothe latching of the first data in at the memory device. This value dependson the memory device selected; refer to the datasheet for your device.(Identifier: MEM_DDR3_WTCL)Memory additive CAS latency settingDetermines the posted CAS additive latency of the memory device. Enablethis feature to improve command and bus efficiency, and increasesystem bandwidth. (Identifier: MEM_DDR3_ATCL_ENUM)5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide151Table : Memory / Mode Register SettingsDisplay NameDescriptionHide advanced mode register settingsShow or hide advanced mode register settings. Changing advanced moderegister settings to non-default values is strongly discouraged. (Identifier:MEM_DDR3_HIDE_ADV_MR_SETTING S)Burst LengthSpecifies the DRAM burst length which determines how many consecutiveaddresses should be accessed for a given read/write command. (Identifier:MEM_DDR3_BL_ENUM)Read Burst TypeIndicates whether accesses within a given burst are in sequential orinterleaved order. Select sequential if you are using the Intel-providedmemory controller. (Identifier: MEM_DDR3_BT_ENUM)DLL precharge power downSpecifies whether the DLL in the memory device is off or on duringprecharge power-down (Identifier: MEM_DDR3_PD_ENUM)Enable the DLL in memory deviceEnable the DLL in memory device (Identifier: MEM_DDR3_DLL_EN)Auto self-refresh methodIndicates whether to enable or disable auto self-refresh. Auto self-refreshallows the controller to issue self-refresh requests, rather than manuallyissuing self-refresh in order for memory to retain data. (Identifier:MEM_DDR3_ASR_ENUM)Self-refre sh temperatureSpecifies the self-refresh temperature as "Normal" or "Extended" information on Normal and Extended temperature modes can befound in the memory device datasheet. (Identifier: MEM_DDR3_SRT_ENUM)DDR3 RDIMM/LRDIMM control wordsEach 4-bit/8-bit setting can be obtained from the manufacturer's data sheetand should be entered in hexadecimal, starting with the 8-bit setting RCBxon the left and continuing to RC1x followed by the 4-bit setting RCOF andending with RC00 on the right (Identifier: MEM_DDR3_RDIMM_CONFIG)DDR3 LRDIMM additional control wordsEach 4-bit setting can be obtained from the manufacturer's data sheet andshould be entered in hexadecimal, starting with BC0F on the left and endingwith BC00 on the right (Identifier:MEM_DDR3_LRDIMM_EXTENDED_CON FIG) Intel Stratix 10 EMIF IP DDR3 Parameters: Mem I/OTable : Mem I/O / Memory I/O SettingsDisplay NameDescriptionOutput drive strength settingSpecifies the output driver impedance setting at the memory device. Toobtain optimum signal integrity performance, select option based on boardsimulation results. (Identifier: MEM_DDR3_DRV_STR_ENUM)ODT Rtt nominal valueDetermines the nominal on-die termination value applied to the DRAM. Thetermination is applied any time that ODT is asserted. If you specify adifferent value for RTT_WR, that value takes precedence over the valuesmentioned here. For optimum signal integrity performance, select youroption based on board simulation results. (Identifier:MEM_DDR3_RTT_NOM_ENUM)Dynami c ODT (Rtt_WR) valueSpecifies the mode of the dynamic on-die termination (ODT) during writesto the memory device (used for multi-rank configurations). For optimumsignal integrity performance, select this option based on board simulationresults. (Identifier: MEM_DDR3_RTT_WR_ENUM)5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide152Table : Mem I/O / ODT ActivationDisplay NameDescriptionUse Default ODT Assertion TablesEnables the default ODT assertion pattern as determined from vendorguidelines. These settings are provided as a default only; you shouldsimulate your memory interface to determine the optimal ODT settings andassertion patterns. (Identifier: MEM_DDR3_USE_DEFAULT_ODT) Intel Stratix 10 EMIF IP DDR3 Parameters: FPGA I/OYou should use Hyperlynx* or similar simulators to determine the best settings foryour board. Refer to the EMIF Simulation Guidance wiki page for : FPGA I/O / FPGA I/O SettingsDisplay NameDescriptionVoltageThe voltage level for the I/O pins driving the signals between the memorydevice and the FPGA memory interface. (Identifier:PHY_DDR3_IO_VOLTAGE)Periodic OCT re-calibrationSpecifies that the system periodically recalibrate on-chip termination (OCT)to minimize variations in termination value caused by changing operatingconditions (such as changes in temperature). By recalibrating OCT, I/Otiming margins are improved. When enabled, this parameter causes thePHY to halt user traffic about every seconds for about 1900 memoryclock cycles, to perform OCT recalibration. Efficiency is reduced byabout 1% when this option is enabled. (Identifier:PHY_DDR3_USER_PERIODIC_OCT_R ECAL_ENUM)Use default I/O settingsSpecifies that a legal set of I/O settings are automatically selected. Thedefault I/O settings are not necessarily optimized for a specific board. Toachieve optimal signal integrity, perform I/O simulations with IBIS modelsand enter the I/O settings manually, based on simulation results.(Identifier: PHY_DDR3_DEFAULT_IO)Table : FPGA I/O / FPGA I/O Settings / Address/CommandDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the address/command pins of thememory interface. The selected I/O standard configures the circuit withinthe I/O buffer to match the industry standard. (Identifier:PHY_DDR3_USER_AC_IO_STD_ENUM )Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_DDR3_USER_AC_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_DDR3_USER_AC_SLEW_RATE_ENUM)5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide153Table : FPGA I/O / FPGA I/O Settings / Memory ClockDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the memory clock pins. Theselected I/O standard configures the circuit within the I/O buffer to matchthe industry standard. (Identifier: PHY_DDR3_USER_CK_IO_STD_ENUM)Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_DDR3_USER_CK_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_DDR3_USER_CK_SLEW_RATE_ENUM)Table : FPGA I/O / FPGA I/O Settings / Data BusDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the data and data clock/strobe pinsof the memory interface. The selected I/O standard option configures thecircuit within the I/O buffer to match the industry standard. (Identifier:PHY_DDR3_USER_DATA_IO_STD_EN UM)Output modeThis parameter allows you to change the output current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_DDR3_USER_DATA_OUT_MODE_ENUM)Input modeThis parameter allows you to change the input termination settings for theselected I/O standard. Perform board simulation with IBIS models todetermine the best settings for your design. (Identifier:PHY_DDR3_USER_DATA_IN_MODE_E NUM)Use recommended initial VrefinSpecifies that the initial Vrefin setting is calculated automatically, to areasonable value based on termination settings. (Identifier:PHY_DDR3_USER_AUTO_STARTING_ VREFIN_EN)Initial VrefinSpecifies the initial value for the reference voltage on the datapins(Vrefin). This value is entered as a percentage of the supply voltagelevel on the I/O pins. The specified value serves as a starting point and maybe overridden by calibration to provide better timing margins. If you chooseto skip Vref calibration (Diagnostics tab), this is the value that is usedas the Vref for the interface. (Identifier:PHY_DDR3_USER_STARTING_VREFI N)Table : FPGA I/O / FPGA I/O Settings / PHY InputsDisplay NameDescriptionPLL reference clock I/O standardSpecifies the I/O standard for the PLL reference clock of the memoryinterface. (Identifier: PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM)RZ Q I/O standardSpecifies the I/O standard for the RZQ pin used in the memory interface.(Identifier: PHY_DDR3_USER_RZQ_IO_STD_ENUM) Intel Stratix 10 EMIF IP DDR3 Parameters: Mem TimingThese parameters should be read from the table in the datasheet associated with thespeed bin of the memory device (not necessarily the frequency at which the interfaceis running).5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide154Table : Mem Timing / Parameters dependent on Speed BinDisplay NameDescriptionSpeed binThe speed grade of the memory device used. This parameter refers to themaximum rate at which the memory device is specified to run. (Identifier:MEM_DDR3_SPEEDBIN_ENUM)tIS (base)tIS (base) refers to the setup time for the Address/Command/Control(A) bus to the rising edge of CK. (Identifier: MEM_DDR3_TIS_PS)tIS (base) AC leveltIS (base) AC level refers to the voltage level which the address/command signal must cross and remain above during the setupmargin window. The signal is considered stable only if it remains abovethis voltage level (for a logic 1) or below this voltage level (for a logic 0) forthe entire setup period. (Identifier: MEM_DDR3_TIS_AC_MV)tIH (base)tIH (base) refers to the hold time for the Address/Command (A) busafter the rising edge of CK. Depending on what AC level the user haschosen for a design, the hold margin can vary (this variance will beautomatically determined when the user chooses the "tIH (base) AClevel"). (Identifier: MEM_DDR3_TIH_PS)tIH (base) DC leveltIH (base) DC level refers to the voltage level which the address/command signal must not cross during the hold window. The signal isconsidered stable only if it remains above this voltage level (for a logic 1) orbelow this voltage level (for a logic 0) for the entire hold period. (Identifier:MEM_DDR3_TIH_DC_MV)tDS (base)tDS(base) refers to the setup time for the Data(DQ) bus before therising edge of the DQS strobe. (Identifier: MEM_DDR3_TDS_PS)tDS (base) AC leveltDS (base) AC level refers to the voltage level which the data bus mustcross and remain above during the setup margin window. The signalis considered stable only if it remains above this voltage level (for a logic 1)or below this voltage level (for a logic 0) for the entire setup period.(Identifier: MEM_DDR3_TDS_AC_MV)tDH (base)tDH (base) refers to the hold time for the Data (DQ) bus after the risingedge of CK. (Identifier: MEM_DDR3_TDH_PS)tDH (base) DC leveltDH (base) DC level refers to the voltage level which the data bus mustnot cross during the hold window. The signal is considered stable only ifit remains above this voltage level (for a logic 1) or below this voltage level(for a logic 0) for the entire hold period. (Identifier:MEM_DDR3_TDH_DC_MV)tDQSQtDQS Q describes the latest valid transition of the associated DQ pinsfor a READ. tDQSQ specifically refers to the DQS, DQS# to DQ skew. It isthe length of time between the DQS, DQS# crossing to the last validtransition of the slowest DQ pin in the DQ group associated with that DQSstrobe. (Identifier: MEM_DDR3_TDQSQ_PS)tQHtQH specifies the output hold time for the DQ in relation to DQS,DQS#. It is the length of time between the DQS, DQS# crossing to theearliest invalid transition of the fastest DQ pin in the DQ group associatedwith that DQS strobe. (Identifier: MEM_DDR3_TQH_CYC)tDQSCKtDQSCK describes the skew between the memory clock (CK) and theinput data strobes (DQS) used for reads. It is the time between therising data strobe edge (DQS, DQS#) relative to the rising CK edge.(Identifier: MEM_DDR3_TDQSCK_PS)tDQSStDQSS describes the skew between the memory clock (CK) and theoutput data strobes used for writes. It is the time between the risingdata strobe edge (DQS, DQS#) relative to the rising CK edge. (Identifier:MEM_DDR3_TDQSS_CYC)tQSHtQSH refers to the differential High Pulse Width, which is measured as apercentage of tCK. It is the time during which the DQS is high for aread. (Identifier: MEM_DDR3_TQSH_CYC) 5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide155Display NameDescriptiontDSHtDSH specifies the write DQS hold time. This is the time differencebetween the rising CK edge and the falling edge of DQS, measured as apercentage of tCK. (Identifier: MEM_DDR3_TDSH_CYC)tWLStWLS describes the write leveling setup time. It is measured from therising edge of CK to the rising edge of DQS. (Identifier:MEM_DDR3_TWLS_PS)tWLHtWLH describes the write leveling hold time. It is measured from therising edge of DQS to the rising edge of CK (Identifier:MEM_DDR3_TWLH_PS)tDSStDSS describes the time between the falling edge of DQS to the risingedge of the next CK transition. (Identifier: MEM_DDR3_TDSS_CYC)tINITtINIT describes the time duration of the memory initialization after adevice power-up. After RESET_n is de-asserted, wait for another 500usuntil CKE becomes active. During this time, the DRAM starts internalinitialization; this happens independently of external clocks. (Identifier:MEM_DDR3_TINIT_US)tMRDThe mode register set command cycle time, tMRD is the minimum timeperiod required between two MRS commands. (Identifier:MEM_DDR3_TMRD_CK_CYC)tRAStRA S describes the activate to precharge duration. A row cannot bedeactivated until the tRAS time has been met. Therefore tRAS determineshow long the memory has to wait after a activate command before aprecharge command can be issued to close the row. (Identifier:MEM_DDR3_TRAS_NS)tRCDtRCD, row command delay, describes the active to read/write time. Itis the amount of delay between the activation of a row through the RAScommand and the access to the data through the CAS command.(Identifier: MEM_DDR3_TRCD_NS)tRPtRP refers to the Precharge (PRE) command period. It describes howlong it takes for the memory to disable access to a row by precharging andbefore it is ready to activate a different row. (Identifier:MEM_DDR3_TRP_NS)tWRtWR refers to the Write Recovery time. It specifies the amount of clockcycles needed to complete a write before a precharge command can beissued. (Identifier: MEM_DDR3_TWR_NS)Table : Mem Timing / Parameters dependent on Speed Bin, OperatingFrequency, and Page SizeDisplay NameDescriptiontRRDtRRD refers to the Row Active to Row Active Delay. It is the minimumtime interval (measured in memory clock cycles) between two activatecommands to rows in different banks in the same rank (Identifier:MEM_DDR3_TRRD_CYC)tFAWtFAW refers to the four activate window time. It describes the period oftime during which only four banks can be active. (Identifier:MEM_DDR3_TFAW_NS)tWTRtWTR or Write Timing Parameter describes the delay from start ofinternal write transaction to internal read command, for accesses tothe same bank. The delay is measured from the first rising memory clockedge after the last write data is received to the rising memory clock edgewhen a read command is received. (Identifier: MEM_DDR3_TWTR_CYC)tRTPtRTP refers to the internal READ Command to PRECHARGE Commanddelay. It is the number of memory clock cycles that is needed between aread command and a precharge command to the same rank. (Identifier:MEM_DDR3_TRTP_CYC)5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide156Table : Mem Timing / Parameters dependent on Density and TemperatureDisplay NameDescriptiontRFCtRFC refers to the Refresh Cycle Time. It is the amount of delay after arefresh command before an activate command can be accepted by thememory. This parameter is dependent on the memory density and isnecessary for proper hardware functionality. (Identifier:MEM_DDR3_TRFC_NS)tREFItREFI refers to the average periodic refresh interval. It is the maximumamount of time the memory can tolerate in between each refresh command(Identifier: MEM_DDR3_TREFI_US) Intel Stratix 10 EMIF IP DDR3 Parameters: BoardTable : Board / Intersymbol Interference/CrosstalkDisplay NameDescriptionUse default ISI/crosstalk valuesYou can enable this option to use default intersymbol interference andcrosstalk values for your topology. Note that the default values are notoptimized for your board. For optimal signal integrity, it is recommendedthat you do not enable this parameter, but instead perform I/O simulationusing IBIS models and Hyperlynx*, and manually enter values based onyour simulation results, instead of using the default values. (Identifier:BOARD_DDR3_USE_DEFAULT_ISI_V ALUES)Address and command ISI/crosstalkThe address and command window reduction due to ISI and crosstalkeffects. The number to be entered is the total loss of margin on both thesetup and hold sides (measured loss on the setup side + measuredloss on the hold side). Refer to the EMIF Simulation Guidance wiki pagefor additional information. (Identifier: BOARD_DDR3_USER_AC_ISI_NS)Read DQS/DQS# ISI/crosstalkThe reduction of the read data window due to ISI and crosstalk effects onthe DQS/DQS# signal when driven by the memory device during a number to be entered is the total loss of margin on the setup andhold sides (measured loss on the setup side + measured loss on thehold side). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_DDR3_USER_RCLK_ISI_NS)Read DQ ISI/crosstalkThe reduction of the read data window due to ISI and crosstalk effects onthe DQ signal when driven by the memory device during a read. Thenumber to be entered is the total loss of margin on the setup and holdside (measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_DDR3_USER_RDATA_ISI_NS)Write DQS/DQS# ISI/crosstalkThe reduction of the write data window due to ISI and crosstalk effects onthe DQS/DQS# signal when driven by the FPGA during a write. The numberto be entered is the total loss of margin on the setup and hold sides(measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_DDR3_USER_WCLK_ISI_NS)Write DQ ISI/crosstalkThe reduction of the write data window due to ISI and crosstalk effects onthe DQ signal when driven by the FPGA during a write. The number to beentered is the total loss of margin on the setup and hold sides(measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_DDR3_USER_WDATA_ISI_NS)5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide157Table : Board / Board and Package SkewsDisplay NameDescriptionPackage deskewed with board layout(DQS group)Enable this parameter if you are compensating for package skew on the DQ,DQS, and DM buses in the board layout. Include package skew incalculating the following board skew parameters. (Identifier:BOARD_DDR3_IS_SKEW_WITHIN_DQ S_DESKEWED)Maximum board skew within DQS groupThe largest skew between all DQ and DM pins in a DQS group. This valueaffects the read capture and write margins. (Identifier:BOARD_DDR3_BRD_SKEW_WITHIN_D QS_NS)Maximum system skew within DQSgroupThe largest skew between all DQ and DM pins in a DQS group. Entercombined board and package skew. This value affects the read capture andwrite margins. (Identifier:BOARD_DDR3_PKG_BRD_SKEW_WITH IN_DQS_NS)Package deskewed with board layout(address/command bus)Enable this parameter if you are compensating for package skew on theaddress, command, control, and memory clock buses in the board package skew in calculating the following board skewparameters. (Identifier:BOARD_DDR3_IS_SKEW_WITHIN_AC _DESKEWED)Maximum board skew within address/command busThe largest skew between the address and command signals. Enter theboard skew only; package skew is calculated automatically, based on thememory interface configuration, and added to this value. (Identifier:BOARD_DDR3_BRD_SKEW_WITHIN_A C_NS)Maximum system skew within address/command busMaximum system skew within address/command bus refers to the largestskew between the address and command signals. (Identifier:BOARD_DDR3_PKG_BRD_SKEW_WITH IN_AC_NS)Average delay difference between DQSand CKThe average delay difference between the DQS signals and the CK signal,calculated by averaging the longest and smallest DQS trace delay minus theCK trace delay. Positive values represent DQS signals that are longer thanCK signals and negative values represent DQS signals that are shorter thanCK signals. (Identifier: BOARD_DDR3_DQS_TO_CK_SKEW_NS)Maximum delay difference betweenDIMMs/devicesThe largest propagation delay on DQ signals between ranks (applicable onlywhen there is more than one rank).For example: when you configure two ranks using one DIMM there is ashort distance between the ranks for the same DQ pin; when youimplement two ranks using two DIMMs the distance is larger.(Identifier: BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS)Maximum skew between DQS groupsThe largest skew between DQS signals. (Identifier:BOARD_DDR3_SKEW_BETWEEN_DQS_ NS)Average delay difference betweenaddress/command and CKThe average delay difference between the address/command signals andthe CK signal, calculated by averaging the longest and smallest address/command signal trace delay minus the maximum CK trace delay. Positivevalues represent address and command signals that are longer than CKsignals and negative values represent address and command signals thatare shorter than CK signals. (Identifier:BOARD_DDR3_AC_TO_CK_SKEW_NS) Maximum CK delay to DIMM/deviceThe delay of the longest CK trace from the FPGA to any DIMM/device.(Identifier: BOARD_DDR3_MAX_CK_DELAY_NS)Maximum DQS delay to DIMM/deviceThe delay of the longest DQS trace from the FPGA to any DIMM/device(Identifier: BOARD_DDR3_MAX_DQS_DELAY_NS) Intel Stratix 10 EMIF IP DDR3 Parameters: Controller5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide158Table : Controller / Avalon InterfaceDisplay NameDescriptionAvalon InterfaceSelects the Avalon Interface through which the controller interacts with userlogic (Identifier: CTRL_DDR3_AVL_PROTOCOL_ENUM)Table : Controller / Low Power ModeDisplay NameDescriptionEnable Self-Refresh ControlSelect this option to enable the self-refresh control on the controller toplevel. The control signal allows you to place the memory device into self-refresh mode, on a per chip-select basis. (Identifier:CTRL_DDR3_SELF_REFRESH_EN)En able Auto Power-DownEnable this parameter to have the controller automatically place thememory device into power-down mode after a specified number of idlecontroller clock cycles. The idle wait time is configurable. All ranks mustbe idle to enter auto power-down. (Identifier:CTRL_DDR3_AUTO_POWER_DOWN_EN )Auto Power-Down CyclesSpecifies the number of idle controller cycles after which the memorydevice is placed into power-down mode. You can configure the idle waitingtime. The supported range for number of cycles is from 1 to 65534.(Identifier: CTRL_DDR3_AUTO_POWER_DOWN_CYCS)Table : Controller / EfficiencyDisplay NameDescriptionEnable User Refresh ControlWhen enabled, user logic has complete control and is responsible for issuingadaquate refresh commands to the memory devices, via the MMR feature provides increased control over worst-case read latency andenables you to issue refresh bursts during idle periods. (Identifier:CTRL_DDR3_USER_REFRESH_EN)En able Auto-Precharge ControlSelect this parameter to enable the auto-precharge control on the controllertop level. If you assert the auto-precharge control signal while requesting aread or write burst, you can specify whether the controller should close(auto-precharge) the currently open page at the end of the read or writeburst, potentially making a future access to a different page of the samebank faster. (Identifier: CTRL_DDR3_AUTO_PRECHARGE_EN)Address OrderingControls the mapping between Avalon addresses and memory deviceaddresses. By changing the value of this parameter, you can change themappings between the Avalon-MM address and the DRAM address.(Identifier: CTRL_DDR3_ADDR_ORDER_ENUM)Enable ReorderingEnable this parameter to allow the controller to perform command and datareordering. Reordering can improve efficiency by reducing busturnaround time and row/bank switching time. Data reordering allowsthe single-port memory controller to change the order of read and writecommands to achieve highest efficiency. Command reordering allows thecontroller to issue bank management commands early based on incomingpatterns, so that the desired row in memory is already open when thecommand reaches the memory interface. For more information, refer to theData Reordering topic in the EMIF Handbook. (Identifier:CTRL_DDR3_REORDER_EN)Starvat ion limit for each commandSpecifies the number of commands that can be served before awaiting command is served. The controller employs a counter to ensurethat all requests are served after a pre-defined interval -- this ensures thatlow priority requests are not ignored, when doing data reordering 5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide159Display NameDescriptionefficiency. The valid range for this parameter is from 1 to 63. For moreinformation, refer to the Starvation Control topic in the EMIF Handbook.(Identifier: CTRL_DDR3_STARVE_LIMIT)Enable Command Priority ControlSelect this parameter to enable user-requested command priority control onthe controller top level. This parameter instructs the controller to treat aread or write request as high-priority. The controller attempts to fill high-priority requests sooner, to reduce latency. Connect this interface to theconduit of your logic block that determines when the externalmemory interface IP treats the read or write request as a high-priority command. (Identifier: CTRL_DDR3_USER_PRIORITY_EN)Table : Controller / Configuration, Status and Error HandlingDisplay NameDescriptionEnable Memory-Mapped Configurationand Status Register (MMR) InterfaceEnable this parameter to change or read memory timing parameters,memory address size, mode register settings, controller status, and requestsideband operations. (Identifier: CTRL_DDR3_MMR_EN)Enable Error Detection and CorrectionLogic with ECCEnables error-correction code (ECC) for single-bit error correction anddouble-bit error detection. Your memory interface must have a width of16, 24, 40, or 72 bits to use ECC. ECC is implemented as soft logic.(Identifier: CTRL_DDR3_ECC_EN)Enable Auto Error Correction toExternal MemorySpecifies that the controller automatically schedule and perform a writeback to the external memory when a single-bit error is detected. Regardlessof whether the option is enabled or disabled, the ECC feature alwayscorrects single-bit errors before returning the read data to user logic.(Identifier: CTRL_DDR3_ECC_AUTO_CORRECTION_EN)Table : Controller / Data Bus Turnaround TimeDisplay NameDescriptionAdditional read-to-write turnaroundtime (same rank)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a read to a write within the same logicalrank. This can help resolve bus contention problems specific to your boardtopology. The value is added to the default which is calculatedautomatically. Use the default setting unless you suspect a problem exists.(Identifier: CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS) Additional write-to-read turnaroundtime (same rank)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a write to a read within the same logicalrank. This can help resolve bus contention problems specific to your boardtopology. The value is added to the default which is calculatedautomatically. Use the default setting unless you suspect a problem exists.(Identifier: CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS) Additional read-to-read turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a read of one logical rank to a read ofanother logical rank. This can resolve bus contention problems specific toyour board topology. The value is added to the default which is calculatedautomatically. Use the default setting unless you suspect a problem exists.(Identifier: CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS) Additional read-to-write turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a read of one logical rank to a write ofanother logical rank. This can help resolve bus contention problemsspecific to your board topology. The value is added to the default which iscalculated automatically. Use the default setting unless you suspect aproblem exists. (Identifier:CTRL_DDR3_RD_TO_WR_DIFF_CHIP _DELTA_CYCS)Additional write-to-write turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a write of one logical rank to a write ofanother logical rank. This can help resolve bus contention 5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide160Display NameDescriptionspecific to your board topology. The value is added to the default which iscalculated automatically. Use the default setting unless you suspect aproblem exists. (Identifier:CTRL_DDR3_WR_TO_WR_DIFF_CHIP _DELTA_CYCS)Additional write-to-read turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a write of one logical rank to a read ofanother logical rank. This can help resolve bus contention problemsspecific to your board topology. The value is added to the default which iscalculated automatically. Use the default setting unless you suspect aproblem exists. (Identifier:CTRL_DDR3_WR_TO_RD_DIFF_CHIP _DELTA_CYCS) Intel Stratix 10 EMIF IP DDR3 Parameters: DiagnosticsTable : Diagnostics / Simulation OptionsDisplay NameDescriptionCalibration modeSpecifies whether to skip memory interface calibration duringsimulation, or to simulate the full calibration the full calibration process can take hours (or even days),depending on the width and depth of the memory interface. You canachieve much faster simulation times by skipping the calibration process,but that is only expected to work when the memory model is ideal and theinterconnect delays are you enable this parameter, the interface still performs some memoryinitialization before starting normal operations. Abstract PHY is supportedwith skip calibration.(Identifier: DIAG_DDR3_SIM_CAL_MODE_ENUM)Abstract phy for fast simulationSpecifies that the system use Abstract PHY for simulation. Abstract PHYreplaces the PHY with a model for fast simulation and can reducesimulation time by 2-3 times. Abstract PHY is available for certainprotocols and device families, and only when you select Skip Calibration.(Identifier: DIAG_DDR3_ABSTRACT_PHY)Table : Diagnostics / Calibration Debug OptionsDisplay NameDescriptionQuartus Prime EMIF Debug Toolkit/On-Chip Debug PortSpecifies the connectivity of an Avalon slave interface for use by theQuartus Prime EMIF Debug Toolkit or user core you set this parameter to "Disabled", no debug features are enabled. Ifyou set this parameter to "Export", an Avalon slave interface named"cal_debug" is exported from the IP. To use this interface with the EMIFDebug Toolkit, you must instantiate and connect an EMIF debug interface IPcore to it, or connect it to the cal_debug_out interface of another EMIFcore. If you select "Add EMIF Debug Interface", an EMIF debug interfacecomponent containing a JTAG Avalon Master is connected to the debug port,allowing the core to be accessed by the EMIF Debug one EMIF debug interface should be instantiated per I/O column. Youcan chain additional EMIF or PHYLite cores to the first by enabling the"Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option for all cores in the chain, and selecting "Export"for the "Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port"option on all cores after the first.(Identifier: DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE)Enable Daisy-Chaining for QuartusPrime EMIF Debug Toolkit/On-ChipDebug PortSpecifies that the IP export an Avalon-MM master interface(cal_debug_out) which can connect to the cal_debug interface of otherEMIF cores residing in the same I/O column. This parameter applies 5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide161Display NameDescriptionif the EMIF Debug Toolkit or On-Chip Debug Port is enabled. Refer tothe Debugging Multiple EMIFs wiki page for more information aboutdebugging multiple EMIFs. (Identifier:DIAG_DDR3_EXPORT_SEQ_AVALON_ MASTER)Interface IDIdentifies interfaces within the I/O column, for use by the EMIF DebugToolkit and the On-Chip Debug Port. Interface IDs should be unique amongEMIF cores within the same I/O column. If the Quartus Prime EMIFDebug Toolkit/On-Chip Debug Port parameter is set to Disabled, theinterface ID is unused. (Identifier: DIAG_DDR3_INTERFACE_ID)Use Soft NIOS Processor for On-ChipDebugEnables a soft Nios processor as a peripheral component to access the On-Chip Debug Port. Only one interface in a column can activate this option.(Identifier: DIAG_SOFT_NIOS_MODE)Table : Diagnostics / Example DesignDisplay NameDescriptionNumber of core clocks sharing slaves toinstantiate in the example designSpecifies the number of core clock sharing slaves to instantiate in theexample design. This parameter applies only if you set the "Core clockssharing" parameter in the "General" tab to "Master" or "Slave".(Identifier: DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES)Enable In-System-Sources-and-ProbesEnables In-System-Sources-and-Probes in the example design for commondebug signals, such as calibration status or example traffic generator per-bit status. This parameter must be enabled if you want to do drivermargining. (Identifier: DIAG_DDR3_EX_DESIGN_ISSP_EN)Table : Diagnostics / Traffic GeneratorDisplay NameDescriptionUse configurable Avalon trafficgenerator option allows users to add the new configurable Avalon trafficgenerator to the example design. (Identifier: DIAG_DDR3_USE_TG_AVL_2)Bypass the default traffic patternSpecifies that the controller/interface bypass the traffic generator pattern after reset. If you do not enable this parameter, the trafficgenerator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_DDR3_BYPASS_DEFAULT_PATTERN)Bypass the user-configured traffic stageSpecifies that the controller/interface bypass the user-configured trafficgenerator's pattern after reset. If you do not enable this parameter, thetraffic generator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration can be done by connecting to the traffic generator via theEMIF Debug Toolkit, or by using custom logic connected to the Avalon-MMconfiguration slave port on the traffic generator. Configuration can also besimulated using the example testbench provided in file.(Identifier: DIAG_DDR3_BYPASS_USER_STAGE)Bypass the traffic generator repeated-writes/repeated-reads test patternSpecifies that the controller/interface bypass the traffic generator's repeattest stage. If you do not enable this parameter, every write and read isrepeated several times. (Identifier: DIAG_DDR3_BYPASS_REPEAT_STAGE)Bypass the traffic generator stresspatternSpecifies that the controller/interface bypass the traffic generator's stresspattern stage. (Stress patterns are meant to create worst-case signalintegrity patterns on the data pins.) If you do not enable this parameter,the traffic generator does not assert a pass or fail status until the generatoris configured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_DDR3_BYPASS_STRESS_STAGE)Export Traffic Generator interfaceSpecifies that the IP export an Avalon-MM slave port for configuring theTraffic Generator. This is required only if you are configuring the trafficgenerator through user logic and not through through the EMIF DebugToolkit. (Identifier: DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE)5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide162Table : Diagnostics / PerformanceDisplay NameDescriptionEnable Efficiency MonitorAdds an Efficiency Monitor component to the Avalon-MM interface of thememory controller, allowing you to view efficiency statistics of the can access the efficiency statistics using the EMIF Debug Toolkit.(Identifier: DIAG_DDR3_EFFICIENCY_MONITOR)Table : Diagnostics / MiscellaneousDisplay NameDescriptionUse short Qsys interface namesSpecifies the use of short interface names, for improved usability andconsistency with other Qsys components. If this parameter is disabled, thenames of Qsys interfaces exposed by the IP will include the type anddirection of the interface. Long interface names are supported forbackward-compatibility and will be removed in a future release. (Identifier:SHORT_QSYS_INTERFACE_NAMES) Intel Stratix 10 EMIF IP DDR3 Parameters: Example DesignsTable : Example Designs / Available Example DesignsDisplay NameDescriptionSelect designSpecifies the creation of a full Quartus Prime project, instantiating anexternal memory interface and an example traffic generator, according toyour parameterization. After the design is created, you can specify thetarget device and pin location assignments, run a full compilation, verifytiming closure, and test the interface on your board using the programmingfile created by the Quartus Prime assembler. The 'Generate ExampleDesign' button lets you generate simulation or synthesis file sets.(Identifier: EX_DESIGN_GUI_DDR3_SEL_DESIGN)Table : Example Designs / Example Design FilesDisplay NameDescriptionSimulationSpecifies that the 'Generate Example Design' button create all necessaryfile sets for simulation. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, simulation file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the simulation example design, and file with other corresponding tcl files. You canrun from a command line to generate thesimulation example design. The generated example designs for varioussimulators are stored in the /sim sub-directory. (Identifier:EX_DESIGN_GUI_DDR3_GEN_SIM)S ynthesisSpecifies that the 'Generate Example Design' button create all necessaryfile sets for synthesis. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, synthesis file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the synthesis example design, and script with other corresponding tcl files. You canrun from a command line to generate thesynthesis example design. The generated example design is stored inthe /qii sub-directory. (Identifier: EX_DESIGN_GUI_DDR3_GEN_SYNTH)5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide163Table : Example Designs / Generated HDL FormatDisplay NameDescriptionSimulation HDL formatThis option lets you choose the format of HDL in which generatedsimulation files are created. (Identifier:EX_DESIGN_GUI_DDR3_HDL_FORMA T)Table : Example Designs / Target Development KitDisplay NameDescriptionSelect boardSpecifies that when you select a development kit with a memory module,the generated example design contains all settings and fixed pinassignments to run on the selected board. You must select a developmentkit preset to generate a working example design for the specifieddevelopment kit. Any IP settings not applied directly from a developmentkit preset will not have guaranteed results when testing the developmentkit. To exclude hardware support of the example design, select 'none' fromthe 'Select board' pull down menu. When you apply a development kitpreset, all IP parameters are automatically set appropriately to match theselected preset. If you want to save your current settings, you should do sobefore you apply the preset. You can save your settings under a differentname using File->Save as. (Identifier:EX_DESIGN_GUI_DDR3_TARGET_DE V_KIT) Board Skew EquationsThe following table presents the underlying equations for the board skew Equations for DDR3 Board Skew ParametersTable Skew Parameter EquationsParameterDescription/EquationMa ximum CK delay toDIMM/deviceThe delay of the longest CK trace from the FPGA to any n is the number of memory clock and r is the number rank of DIMM/device. Forexample in dual-rank DIMM implementation, if there are 2 pairs of memory clocks in eachrank DIMM, the maximum CK delay is expressed by the following equation:maxCK1PathDelayrank1,CK2PathDel ayrank1,CK1PathDelayrank2,CK2PathDelayra nk2Maximum DQS delay toDIMM/deviceThe delay of the longest DQS trace from the FPGA to the n is the number of DQS and r isthe number of rank of DIMM/device. For example indual-rank DIMM implementation, if there are 2 DQS in each rank DIMM, the maximum DQSdelay is expressed by the following equation:maxDQS1PathDelayrank1,DQS2PathD elayrank1,DQS1PathDelayrank2,DQS2PathDel ayrank2Average delay differencebetween DQS and CKThe average delay difference between the DQS signals and the CK signal, calculated byaveraging the longest and smallest DQS delay minus the CK delay. Positive valuesrepresent DQS signals that are longer than CK signals and negative values represent DQSsignals that are shorter than CK signals. The Quartus Prime software uses this skew tooptimize the delay of the DQS signals for appropriate setup and hold 5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide164ParameterDescription/Equationmax rmaxn,mDQSm_rDelay CKn_rDelay+ minrminn,mDQSm_rDelay CKn_rDelay2Where n is the number of memory clock, m is the number of DQS, and r is the number ofrank of using discete components, the calculation differs slightly. Find the minimum andmaximum values for (DQS-CK) over all groups and then divide by 2. Calculate the (DQS-CK) for each DQS group, by using the appropriate CLK for that example, in a configuration with 5 x16 components, with each component having twoDQS groups: To find the minimum and maximum, calculate the minimum and maximum of(DQS0 CK0, DQS1 CK0, DQS2 CK1, DQS3 CK1, and so forth) and then divide theresult by Board skew withinDQS groupThe largest skew between all DQ and DM pins in a DQS group. Enter your board skew skew is calculated automatically, based on the memory interface configuration,and added to this value. This value affects the read capture and write minDQgMaximum skew betweenDQS groupsThe largest skew between DQS signals in different DQS groupsMingDQSgMaximum system skewwithin address/commandbusMaxAC MinACThe largest skew between the address and command signals. Enter combined board andpackage skew. In the case of a component, find the maximum address/command andminimum address/command values across all component address delay differencebetween address/commandand CKA value equal to the average of the longest and smallest address/command signal delays,minus the delay of the CK signal. The value can be positive or average delay difference between the address/command and CK is expressed by thefollowing equation: n=nn= 1LongestACPathDelay+ShortestACPathDelay2 CKnPathDelaynwhere n is the number of memory delay differencebetween DIMMs/devicesThe largest propagation delay on DQ signals betweek ranks. For example, in a two-rankconfiguration where you place DIMMs in different slots there is also a propagation delay forDQ signals going to and coming back from the furthest DIMM compared to the nearestDIMM. This parameter is applicable only when there is more than one { maxn,m [(DQn_r path delay DQn_r+1 path delay), (DQSm_r path delay DQSm_r+1 path delay)]}Where n is the number of DQ, m is the number of DQS and r is number of rank of DIMM/device . Pin and Resource PlanningThe following topics provide guidelines on pin placement for external Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide165Typically, all external memory interfaces require the following FPGA resources: Interface pins PLL and clock network Other FPGA resources for example, core fabric logic, and on-chip termination(OCT) calibration blocksOnce all the requirements are known for your external memory interface, you canbegin planning your Interface PinsAny I/O banks that do not support transceiver operations in Intel Stratix 10 devicessupport external memory interfaces. However, DQS (data strobe or data clock) andDQ (data) pins are listed in the device pin tables and are fixed at specific locations inthe device. You must adhere to these pin locations to optimize routing, minimize skew,and maximize margins. Always check the pin table for the actual locations of the DQSand DQ : Maximum interface width varies from device to device depending on the number ofI/O pins and DQS or DQ groups available. Achievable interface width also depends onthe number of address and command pins that the design requires. To ensureadequate PLL, clock, and device routing resources are available, you should alwaystest fit any IP in the Intel Quartus Prime Prime software before PCB devices do not limit the width of external memory interfaces beyond thefollowing requirements: Maximum possible interface width in any particular device is limited by thenumber of DQS groups available. Sufficient clock networks are available to the interface PLL as required by the IP. Sufficient spare pins exist within the chosen bank or side of the device to includeall other address and command, and clock pin placement requirements. The greater the number of banks, the greater the skew, hence Intel recommendsthat you always generate a test project of your desired configuration and confirmthat it meets Estimating Pin RequirementsYou should use the Intel Quartus Prime software for final pin fitting. However, you canestimate whether you have enough pins for your memory interface using the EMIFDevice Selector on , or perform the following steps:1. Determine how many read/write data pins are associated per data strobe or Calculate the number of other memory interface pins needed, including any otherclocks (write clock or memory system clock), address, command, and RZQ. Referto the External Memory Interface Pin Table to determine necessary Address/Command/Clock pins based on your desired Calculate the total number of I/O banks required to implement the memoryinterface, given that an I/O bank supports up to 48 GPIO Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide166You should test the proposed pin-outs with the rest of your design in the Intel QuartusPrime software (with the correct I/O standard and OCT connections) before finalizingthe pin-outs. There can be interactions between modules that are illegal in the IntelQuartus Prime software that you might not know about unless you compile the designand use the Intel Quartus Prime Pin LinksExternal Memory Interfaces Support DIMM OptionsUnbuffered DIMMs (UDIMMs) require one set of chip-select (CS#), on-die termination(ODT), clock-enable (CKE), and clock pair (CK/CKn) for every physical rank on theDIMM. Registered DIMMs use only one pair of clocks. DDR3 registered DIMMs requirea minimum of two chip-select signals, while DDR4 requires only to the unbuffered DIMMs (UDIMM), registered and load-reduced DIMMs(RDIMMs and LRDIMMs, respectively) use at least two chip-select signals CS#[1:0] inDDR3 and DDR4. Both RDIMMs and LRDIMMs require an additional parity signal foraddress, RAS#, CAS#, and WE# signals. A parity error signal is asserted by the modulewhenever a parity error is expand on the operation of RDIMMs by buffering the DQ/DQS bus. Only oneelectrical load is presented to the controller regardless of the number of ranks,therefore only one clock enable (CKE) and ODT signal are required for LRDIMMs,regardless of the number of physical ranks. Because the number of physical ranksmay exceed the number of physical chip-select signals, DDR3 LRDIMMs provide afeature known as rank multiplication, which aggregates two or four physical ranks intoone larger logical rank. Refer to LRDIMM buffer documentation for details on following table shows UDIMM and RDIMM pin options for and RDIMM Pin Options for DDR3PinsUDIMM Pins (SingleRank)UDIMM Pins(Dual Rank)RDIMM Pins (SingleRank)RDIMM Pins(Dual Rank)Data72 bit DQ[71:0] ={CB[7:0], DQ[63:0]}72 bit DQ[71:0] ={CB[7:0], DQ[63:0]}72 bit DQ[71:0] ={CB[7:0], DQ[63:0]}72 bit DQ[71:0]={CB[7:0], DQ[63:0]}Data MaskDM[8:0]DM[8:0]DM[8:0]DM[8:0]Data StrobeDQS[8:0] andDQS#[8:0]DQS[8:0] andDQS#[8:0]DQS[8:0] andDQS#[8:0]DQS[8:0] andDQS#[8:0]AddressBA[2:0], A[15:0] 2 GB: A[13:0]4 GB: A[14:0]8 GB: A[15:0]BA[2:0], A[15:0] 2 GB: A[13:0]4 GB: A[14:0]8 GB: A[15:0]BA[2:0], A[15:0] 2 GB: A[13:0]4 GB: A[14:0]8 GB: A[15:0]BA[2:0], A[15:0] 2 GB: A[13:0]4 GB: A[14:0]8 GB: A[15:0]ClockCK0/CK0#CK0/CK0#, CK1/CK1#CK0/CK0#CK0/CK0# 5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide167PinsUDIMM Pins (SingleRank)UDIMM Pins(Dual Rank)RDIMM Pins (SingleRank)RDIMM Pins(Dual Rank)CommandODT, CS#, CKE, RAS#,CAS#, WE#ODT[1:0], CS#[1:0],CKE[1:0], RAS#, CAS#,WE#ODT, CS#[1:0], CKE,RAS#, CAS#, WE# 2ODT[1:0], CS#[1:0],CKE[1:0], RAS#,CAS#, WE#Parity PAR, ALERTPAR, ALERTOther PinsSA[2:0], SDA, SCL,EVENT#, RESET#SA[2:0], SDA, SCL,EVENT#, RESET#SA[2:0], SDA, SCL,EVENT#, RESET#SA[2:0], SDA, SCL,EVENT#, RESET#The following table shows LRDIMM pin options for Pin Options for DDR3PinsLRDIMMPins (x4,2R)LRDIMM(x4, 4R,RMF=1) 3LRDIMMPins (x4,4R, RMF=2)LRDIMMPins (x4,8R, RMF=2)LRDIMMPins (x4,8R, RMF=4)LRDIMM(x8, 4R,RMF=1) 3LRDIMMPins (x8,4R, RMF=2)Data72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}Data Mask DM[8:0]DM[8:0]Data StrobeDQS[17:0]andDQS#[17:0]DQS[17:0]and DQS#[17:0]DQS[17:0]andDQS#[17:0]DQS[17:0 ]andDQS#[17:0]DQS[17:0]andDQS#[17:0]DQS[ 8:0]andDQS#[8:0]DQS[8:0]andDQS#[8:0]Addr essBA[2:0], A[15:0]-2GB:A[13:0] 4GB:A[14:0]8GB:A[15:0] BA[2:0], A[15:0]-2GB:A[13:0] 4GB:A[14:0]8GB:A[15:0]BA[2:0], A[16:0]-4GB:A[14:0] 8GB:A[15:0]16GB:A[16:0]BA[2:0], A[16:0]-4GB:A[14:0] 8GB:A[15:0]16GB:A[16:0] BA[2:0], A[17:0]-16GB:A[15:0] 32GB:A[16:0]64GB:A[17:0] BA[2:0], A[15:0]-2GB:A[13:0] 4GB:A[14:0]8GB:A[15:0]BA[2:0], A[16:0]-4GB:A[14:0] 8GB:A[15:0]16GB:A[16:0]ClockCK0/CK0#CK0/ CK0#CK0/CK0#CK0/CK0#CK0/CK0#CK0/CK0#CK0/ CK0#CommandODT,CS[1:0]#,CKE,RAS#,CAS#, WE#ODT,CS[3:0]#,CKE,RAS#,CAS#, WE#ODT,CS[2:0]#,CKE,RAS#,CAS#, WE#ODT,CS[3:0]#,CKE,RAS#,CAS#, WE#ODT,CS[3:0]#,CKE,RAS#,CAS#, WE#ODT,CS[3:0]#,CKE,RAS#,CAS#, WE#ODT,CS[2:0]#,CKE,RAS#,CAS#, WE#ParityPAR, ALERTPAR, ALERTPAR, ALERTPAR, ALERTPAR, ALERTPAR, ALERTPAR, ALERTOther PinsSA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#Notes to Table:1. DM pins are not used for LRDIMMs that are constructed using 4 S#[2] is treated as A[16] (whose corresponding pins are labeled as CS#[2] or RM[0]) and S#[3] is treated as A[17](whose corresponding pins are labeled as CS#[3] or RM[1]) for certain rank multiplication = rank, RMF = rank multiplication following table shows UDIMM, RDIMM, and LRDIMM pin options for Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide168Table , RDIMM, and LRDIMM Pin Options for DDR4PinsUDIMM Pins(Single Rank)UDIMM Pins(Dual Rank)RDIMM Pins(Single Rank)RDIMM Pins(Dual Rank)LRDIMM Pins(Dual Rank)LRDIMM Pins(Quad Rank)Data72 bitDQ[71:0]={CB[7:0],DQ[63:0]}72 bitDQ[71:0]={CB[7:0],DQ[63:0]}72 bitDQ[71:0]={CB[7:0],DQ[63:0]}72 bitDQ[71:0]={CB[7:0],DQ[63:0]}72 bitDQ[71:0]={CB[7:0],DQ[63:0]}72 bitDQ[71:0]={CB[7:0],DQ[63:0]}Data MaskDM#/DBI#[8:0] (1)DM#/DBI#[8:0](1)DM#/DBI#[8:0](1)DM#/D BI#[8:0](1) Data Strobex8:DQS[8:0] andDQS#[8:0]x8:DQS[8:0] andDQS#[8:0]x8:DQS[8:0] andDQS#[8:0]x4:DQS[17:0]andDQS#[17:0]x8: DQS[8:0] andDQS#[8:0]x4:DQS[17:0]andDQS#[17:0]x4: DQS[17:0]andDQS#[17:0]x4:DQS[17:0]andDQS #[17:0]AddressBA[1:0],BG[1:0],A[16:0] -4GB:A[14:0]8GB: A[15:0]16GB:A[16:0] (2)BA[1:0],BG[1:0],A[16:0] -8GB: A[14:0]16GB:A[15:0]32GB:A[16:0] (2)BA[1:0],BG[1:0], x8:A[16:0] -4GB:A[14:0]8GB: A[15:0]16GB:A[16:0] (2)32GB:A[17:0] (3)BA[1:0],BG[1:0],x8:A[16:0] x4:A[17:0] -8GB: A[14:0]16GB:A[15:0]32GB:A[16:0] (2)64GB:A[17:0] (3)BA[1:0],BG[1:0],A[17:0] -16GB:A[15:0]32GB:A[16:0] (2)64GB:A[17:0] (3)BA[1:0],BG[1:0],A[17:0] -32GB:A[15:0]64GB:A[16:0] (2)128GB:A[17:0] (3)ClockCK0/CK0#CK0/CK0#,CK1/CK1#CK0/CK0 #CK0/CK0#CK0/CK0#CK0/CK0#CommandODT, CS#,CKE, ACT#,RAS#/A16,CAS#/A15,WE#/A14ODT[1:0],C S#[1:0],CKE[1:0],ACT#, RAS#/A16, CAS#/A15,WE#/A14ODT, CS#,CKE, ACT#,RAS#/A16,CAS#/A15,WE#/A14ODT[1:0],C S#[1:0],CKE, ACT#,RAS#/A16,CAS#/A15,WE#/A14ODT,CS#[1: 0],CKE, ACT#,RAS#/A16,CAS#/A15,WE#/A14ODT,CS#[3: 0],CKE, ACT#,RAS#/A16,CAS#/A15,WE#/A14ParityPAR, ALERT#PAR, ALERT#PAR, ALERT#PAR, ALERT#PAR, ALERT#PAR, ALERT#Other PinsSA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#Notes to Table:1. DM/DBI pins are available only for DIMMs constructed using x8 or greater This density requires 4Gb x4 or 2Gb x8 DRAM This density requires 8Gb x4 DRAM This table assumes a single slot configuration. The Intel Stratix 10 memory controller can support up to 4 ranks perchannel. A single slot interface may have up to 4 ranks, and a dual slot interface may have up to 2 ranks per slot. Ineither cse, the total number of ranks, calculated as the number of slots multipled by the number of ranks per slot, mustbe less than or equal to Maximum Number of InterfacesThe maximum number of interfaces supported for a given memory protocol varies,depending on the FPGA in Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide169Unless otherwise noted, the calculation for the maximum number of interfaces isbased on independent interfaces where the address or command pins are not : You may need to share PLL clock outputs depending on your clock network interface information for Intel Stratix 10, consult the EMIF Device Selector closure depends on device resource and routing utilization. For moreinformation about timing closure, refer to the Area and Timing OptimizationTechniques chapter in the Intel Quartus Prime Links External Memory Interfaces Support Center Intel Stratix 10 EMIF Architecture: PLL Reference Clock Networks on page 20 External Memory Interface Device Selector Intel Quartus Prime Pro Edition FPGA ResourcesThe Intel FPGA memory interface IP uses FPGA fabric, including registers and theMemory Block to implement the memory OCT calibration block is used if you are using the FPGA OCT feature in thememory interface. The OCT calibration block uses a single pin (RZQ). You can selectany of the available OCT calibration block as you do not need to place this block in thesame bank or device side of your memory interface. The only requirement is that theI/O bank where you place the OCT calibration block uses the same VCCIO voltage asthe memory interface. You can share multiple memory interfaces with the same OCTcalibration block if the VCCIO voltage is the OCTIf the memory interface uses any FPGA OCT calibrated series, parallel, or dynamictermination for any I/O in your design, you need a calibration block for the OCTcircuitry. This calibration block is not required to be within the same bank or side ofthe device as the memory interface RZQ pin in Intel Stratix 10 devices can be used as a general purpose I/O pin whenit is not used to support OCT, provided the signal conforms to the bank PLLWhen using PLL for external memory interfaces, you must consider the followingguidelines:5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide170 For the clock source, use the clock input pin specifically dedicated to the PLL thatyou want to use with your external memory interface. The input and output pinsare only fully compensated when you use the dedicated PLL clock input pin. If theclock source for the PLL is not a dedicated clock input pin for the dedicated PLL,you would need an additional clock network to connect the clock source to the PLLblock. Using additional clock network may increase clock jitter and degrade thetiming margin. Pick a PLL and PLL input clock pin that are located on the same side of the deviceas the memory interface pins. Share the DLL and PLL static clocks for multiple memory interfaces provided thecontrollers are on the same or adjacent side of the device and run at the samememory clock frequency. If your design uses a dedicated PLL to only generate a DLL input reference clock,you must set the PLL mode to No Compensation in the Intel Quartus Primesoftware to minimize the jitter, or the software forces this setting PLL does not generate other output, so it does not need to compensate forany clock Pin Guidelines for Intel Stratix 10 EMIF IPThe Intel Stratix 10 device contains up to three I/O columns that can be used byexternal memory Intel Stratix 10 I/O subsystem resides in the I/Ocolumns. Each column contains multiple I/O banks, each of which consists of four I/Olanes. An I/O lane is a group of twelve I/O I/O column, I/O bank, I/O lane, adjacent I/O bank, and pairing pin for everyphysical I/O pin can be uniquely identified using the Bank Number and Indexwithin I/O Bank values which are defined in each Intel Stratix 10 device pin-outfile. The numeric component of the Bank Number value identifies the I/O column,while the letter represents the I/O bank. The Index within I/O Bank value falls within one of the following ranges: 0 to11, 12 to 23, 24 to 35, or 36 to 47, and represents I/O lanes 1, 2, 3, and 4,respectively. The adjacent I/O bank is defined as the I/O bank with same column number butthe letter is either before or after the respective I/O bank letter in the A-Z system. The pairing pin for an I/O pin is located in the same I/O bank. You can identify thepairing pin by adding one to its Index within I/O Bank number (if it is aneven number), or by subtracting one from its Index within I/O Bank number(if it is an odd number).For example, a physical pin with a Bank Number of 2M and Index within I/OBank of 22, indicates that the pin resides in I/O lane 2, in I/O bank 2M, in column adjacent I/O banks are 2L and 2N. The pairing pin for this physical pin is the pinwith an Index within I/O Bank of 23 and Bank Number of General GuidelinesYou should follow the recommended guidelines when performing pin placement for allexternal memory interface pins targeting Intel Stratix 10 devices, whether you areusing the hard memory controller or your own Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide171If you are using the hard memory controller, you should employ the relative pinlocations defined in the <variation_name>/altera_emif_arch_nd_versionnumber/<synth|sim>/<variation_name>_altera_emif_arch_nd_versionnumber_<unique ID> file, w+ted with your : 1. EMIF IP pin-out requirements for the Intel Stratix 10 Hard Processor Subsystem(HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IPdefines a fixed pin-out in the Intel Quartus Prime IP file (.qip), based on the IPconfiguration. When targeting Intel Stratix 10 HPS, you do not need to makelocation assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the IntelQuartus Prime software. Alternatively, consult the device handbook or the devicepin-out files. For information on how you can customize the HPS EMIF pin-out,refer to Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP with Ping Pong PHY, PHY only, RLDRAMx , QDRx and LPDDR3 are not supported the following general guidelines when placing pins for your Intel Stratix 10external memory interface:1. Ensure that the pins of a single external memory interface reside within a singleI/O An external memory interface can occupy one or more banks in the same I/Ocolumn. When an interface must occupy multiple banks, ensure that those banksare adjacent to one Any pin in the same bank that is not used by an external memory interface isavailable for use as a general purpose I/O of compatible voltage and All address and command pins and their associated clock pins (CK and CK#) mustreside within a single bank. The bank containing the address and command pins isidentified as the address and command To minimize latency, when the interface uses more than two banks, you mustselect the center bank of the interface as the address and command The address and command pins and their associated clock pins in the address andcommand bank must follow a fixed pin-out scheme, as defined in the Intel Stratix10 External Memory Interface Pin Information File, which is available do not have to place every address and command pin manually. If you assignthe location for one address and command pin, the Fitter automatically places theremaining address and command : The pin-out scheme is a hardware requirement that you must follow, andcan vary according to the topology of the memory device. Some schemesrequire three lanes to implement address and command pins, while othersrequire four lanes. To determine which scheme to follow, refer to themessages window during parameterization of your IP, or to the<variation_name>/altera_emif_arch_nd_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nd_<version>_<uniqueID> file after you have generated your Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide1727. An unused I/O lane in the address and command bank can serve to implement adata group, such as a x8 DQS group. The data group must be from the samecontroller as the address and command An I/O lane must not be used by both address and command pins and data Place read data groups according to the DQS grouping in the pin table and PinPlanner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQand CQ# / QK and QK#) must reside at physical pins capable of functioning asDQS/CQ and DQSn/CQn for a specific read data group size. You must place theassociated read data pins (such as DQ and Q), within the same : other device families, there is no need to swap CQ/CQ# pins incertain QDR II and QDR II+ latency requires that the polarity of all QKB/QKB# pins be swapped withrespect to the polarity of the differential buffer inputs on the FPGA toensure correct data capture on port B. All QKB pins on the memorydevice must be connected to the negative pins of the input buffers onthe FPGA side, and all QKB# pins on the memory device must beconnected to the positive pins of the input buffers on the FPGA that the port names at the top-level of the IP already reflect thisswap (that is, mem_qkb is assigned to the negative buffer leg, andmem_qkb_n is assigned to the positive buffer leg).10. You can implement two x4 DQS groups with a single I/O lane. The pin tablespecifies which pins within an I/O lane can be used for the two pairs of DQS andDQS# signals. In addition, for x4 DQS groups you must observe the followingrules:5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide173 There must be an even number of x4 groups in an external memory interface. DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly,DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS groupX and DQS group X+1 must be in the same I/O lane, where X is an evennumber. When placing DQ pins in x4 mode, it is important to stay within a nibble whenswapping pin locations. In other words, you may swap DQ pins within a givenDQS group, but you may not swap pins across DQS groups. The followingtable illustrates an example, where DATA_A and DATA_B are swap groups,meaning that any pin in that index can move within that range of Within LaneDQS x4 Locations11DATA_B[3:0]10DATA_B[3:0]9DQS_ Bn8DQS_Bp7DATA_B[3:0]6DATA_B[3:0]5DQS_An 4DQS_Ap3DATA_A[3:0]2DATA_A[3:0]1DATA_A[3 :0]0DATA_A[3:0]11. You should place the write data groups according to the DQS grouping in the pintable and Pin Planner. Output-only data clocks for QDR II, QDR II+, and QDR II+Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, butmust be placed on a differential pin pair. They must be placed in the same I/Obank as the corresponding DQS : For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced toDK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.12. For protocols and topologies with bidirectional data pins where a write data groupconsists of multiple read data groups, you should place the data groups and theirrespective write and read clock in the same bank to improve I/O do not need to specify the location of every data pin manually. If you assignthe location for the read capture strobe/clock pin pairs, the Fitter willautomatically place the remaining data Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/Opin and another in the pairing pin for that I/O pin. It is recommended though notrequired that you follow the same rule for DBI pins, so that at a later date youhave the freedom to repurpose the pin as Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide174Note: 1. x4 mode does not support DM/DBI, or Intel Stratix 10 EMIF IP for If you are using an Intel Stratix 10 EMIF IP-based RLDRAM 3 external memoryinterface, you should ensure that all the pins in a DQS group (that is, DQ, DM, DK,and QK) are placed in the same I/O bank. This requirement facilitates timingclosure and is necessary for successful compilation of your Interfaces in the Same I/O ColumnTo place multiple interfaces in the same I/O column, you must ensure that the globalreset signals (global_reset_n) for each individual interface all come from the sameinput pin or Banks Selection For each memory interface, select consecutive I/O banks. (That is, select banksthat contain the same column number and letter before or after the respective I/Obank letter.) A memory interface can only span across I/O banks in the same I/O column. The number of I/O banks that you require depends on the memory interfacewidth. In some device packages, the number of I/O pins in some LVDS I/O banks is lessthat 48 Pins Location All address/command pins for a controller must be in a single I/O bank. If your interface uses multiple I/O banks, the address/command pins must use themiddle bank. If the number of banks used by the interface is even, any of the twomiddle I/O banks can be used for address/command pins. Address/command pins and data pins cannot share an I/O lane but can share anI/O bank. The address/command pin locations for the soft and hard memory controllers arepredefined. In the External Memory Interface Pin Information for Devicesspreadsheet, each index in the "Index within I/O bank" column denotes adedicated address/command pin function for a given protocol. The index numberof the pin specifies to which I/O lane the pin belongs: I/O lane 0 Pins with index 0 to 11 I/O lane 1 Pins with index 12 to 23 I/O lane 2 Pins with index 24 to 35 I/O lane 3 Pins with index 36 to 47 For memory topologies and protocols that require only three I/O lanes for theaddress/command pins, use I/O lanes 0, 1, and 2. Unused address/command pins in an I/O lane can be used as general-purpose Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide175CK Pins AssignmentAssign the clock pin (CK pin) according to the number of I/O banks in an interface: If the number of I/O banks is odd, assign one CK pin to the middle I/O bank. If the number of I/O banks is even, assign the CK pin to either of the middle twoI/O the Fitter can automatically select the required I/O banks, Intel recommendsthat you make the selection manually to reduce the pre-fit run Reference Clock Pin PlacementPlace the PLL reference clock pin in the address/command bank. Other I/O banks maynot have free pins that you can use as the PLL reference clock pin: If you are sharing the PLL reference clock pin between several interfaces, the I/Obanks must be adjacent. (That is, the banks must contain the same columnnumber and letter before or after the respective I/O bank letter.)The Intel Stratix 10 external memory interface IP does not support PLL Pin PlacementYou may place the RZQ pin in any I/O bank in an I/O column with the correct VCCIO andVCCPT for the memory interface I/O standard in use. However, the recommendedlocation is in the address/command I/O bank, for greater flexibility during debug if anarrower interface project is required for and DQS Pins AssignmentIntel recommends that you assign the DQS pins to the remaining I/O lanes in the I/Obanks as required: Constrain the DQ and DQS signals of the same DQS group to the same I/O lane. You cannot constrain DQ signals from two different DQS groups to the same you do not specify the DQS pins assignment, the Fitter selects the DQS an I/O Bank Across Multiple InterfacesIf you are sharing an I/O bank across multiple external memory interfaces, followthese guidelines: The interfaces must use the same protocol, voltage, data rate, frequency, and PLLreference clock. You cannot use an I/O bank as the address/command bank for more than oneinterface. The memory controller and sequencer cannot be shared. You cannot share an I/O lane. There is only one DQS input per I/O lane, and anI/O lane can connect to only one memory Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Command and Address SignalsCommand and address signals in SDRAM devices are clocked into the memory deviceusing the CK or CK# signal. These pins operate at single data rate (SDR) using onlyone clock edge. The number of address pins depends on the SDRAM device address pins are multiplexed, so two clock cycles are required to send the row,column, and bank DDR3, the CS#, RAS#, CAS#, WE#, CKE, and ODT pins are SDRAM command andcontrol pins. For DDR3 SDRAM, certain topologies such as RDIMM and LRDIMM includeRESET#, PAR ( LVCMOS I/O standard), and ALERT# (SSTL-15 I/O standard).Although DDR4 operates in fundamentally the same way as other SDRAM, there areno longer dedicated pins for RAS#, CAS#, and WE#, as those are now shared withhigher-order address pins. DDR4 still has CS#, CKE, ODT, and RESET# pins, similar toDDR3. DDR4 introduces some additional pins, including the ACT# (activate) pin andBG (bank group) pins. Depending on the memory format and the functions enabled,the following pins might also exist in DDR4: PAR (address command parity) pin andthe ALERT# Clock SignalsDDR3 and DDR4 SDRAM devices use CK and CK# signals to clock the address andcommand signals into the memory. Furthermore, the memory uses these clock signalsto generate the DQS signal during a read through the DLL inside the memory. TheSDRAM data sheet specifies the following timings: tDQSCK is the skew between the CK or CK# signals and the SDRAM-generated DQSsignal tDSH is the DQS falling edge from CK rising edge hold time tDSS is the DQS falling edge from CK rising edge setup time tDQSS is the positive DQS latching edge to CK rising edgeSDRAM have a write requirement (tDQSS) that states the positive edge of the DQSsignal on writes must be within 25% ( 90 ) of the positive edge of the SDRAMclock input. Therefore, you should generate the CK and CK# signals using the DDRregisters in the IOE to match with the DQS signal and reduce any variations acrossprocess, voltage, and temperature. The positive edge of the SDRAM clock, CK, isaligned with the DQS write to satisfy SDRAM can use a daisy-chained control address command (CAC) topology, inwhich the memory clock must arrive at each chip at a different time. To compensatefor the flight-time skew between devices when using the CAC topology, you shouldemploy write Data, Data Strobes, DM/DBI, and Optional ECC SignalsDDR3 and DDR4 SDRAM use bidirectional differential data strobes. Differential DQSoperation enables improved system timing due to reduced crosstalk and lesssimultaneous switching noise on the strobe output drivers. The DQ pins are pins in DDR3 and DDR4 SDRAM interfaces can operate in either 4 or 8 modeDQS groups, depending on your chosen memory device or DIMM, regardless ofinterface width. The 4 and 8 configurations use one pair of bidirectional data strobe5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide177signals, DQS and DQSn, to capture input data. However, two pairs of data strobes,UDQS and UDQS# (upper byte) and LDQS and LDQS# (lower byte), are required bythe 16 configuration devices. A group of DQ pins must remain associated with itsrespective DQS and DQSn DQ signals are edge-aligned with the DQS signal during a read from the memoryand are center-aligned with the DQS signal during a write to the memory. Thememory controller shifts the DQ signals by 90 degrees during a write operation tocenter align the DQ and DQS signals. The PHY IP delays the DQS signal during a read,so that the DQ and DQS signals are center aligned at the capture register. Inteldevices use a phase-locked loop (PLL) to center-align the DQS signal with respect tothe DQ signals during writes and Intel devices use dedicated DQS phase-shift circuitryto shift the incoming DQS signal during reads. The following figure shows an examplewhere the DQS signal is shifted by 90 degrees for a read from the DDR3 DQ and DQS Relationship During a DDR3 SDRAM Read in Burst-of-Four ModeDQS at DQIOE registersDQS at FPGA PinDQ at DQIOE registersDQ atFPGA PinDQS phase shiftPreamblePostambleThe following figure shows an example of the relationship between the data and datastrobe during a burst-of-four and DQS Relationship During a DDR3 SDRAM Write in Burst-of-Four ModeDQS atFPGA PinDQ atFPGA PinThe memory device's setup (tDS) and hold times (tDH) for the DQ and DM pins duringwrites are relative to the edges of DQS write signals and not the CK or CK# and hold requirements are not necessarily balanced in DDR3 DQS signal is generated on the positive edge of the system clock to meet thetDQSS requirement. DQ and DM signals use a clock shifted 90 degrees from thesystem clock, so that the DQS edges are centered on the DQ or DM signals when theyarrive at the DDR3 SDRAM. The DQS, DQ, and DM board trace lengths need to betightly matched (within 20 ps).The SDRAM uses the DM pins during a write operation. Driving the DM pins low showsthat the write is valid. The memory masks the DQ signals if the DM pins are drivenhigh. To generate the DM signal, Intel recommends that you use the spare DQ pinwithin the same DQS group as the respective data, to minimize Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide178The DM signal's timing requirements at the SDRAM input are identical to those for DQdata. The DDR registers, clocked by the 90 degree shifted clock, create the supports DM similarly to other SDRAM, except that in DDR4 DM is active LOWand bidirectional, because it supports Data Bus Inversion (DBI) through the same is multiplexed with DBI by a Mode Register setting whereby only one function canbe enabled at a time. DBI is an input/output identifying whether to store/output thetrue or inverted data. When enabled, if DBI is LOW, during a write operation the datais inverted and stored inside the DDR4 SDRAM; during a read operation, the data isinverted and output. The data is not inverted if DBI is HIGH. For Intel Stratix 10interfaces, the DM (for DDR3) pins in each DQS group must be paired with a DQ pinfor proper operation. DM/DBI (for DDR4) do not need to be paired with a DQ SDRAM modules support error correction coding (ECC) to allow the controller todetect and automatically correct error in data transmission. The 72-bit SDRAMmodules contain eight extra data pins in addition to 64 data pins. The eight extra ECCpins should be connected to a single DQS or DQ group on the Resource Sharing Guidelines (Multiple Interfaces)In Intel Cyclone 10Intel Stratix 10 external memory interface IP, different externalmemory interfaces can share PLL reference clock pins, core clock networks, I/O banks,and hard Nios processors. Each I/O bank has DLL and PLL resources, therefore thesedo not need to be shared. The Intel Quartus Prime Fitter automatically merges DLLand PLL resources when a bank is shared by different external memory interfaces, andduplicates them for a multi-I/O-bank external memory Reference Clock PinTo conserve pin usage and enable core clock network and I/O bank sharing, you canshare a PLL reference clock pin between multiple external memory interfaces; theinterfaces must be of the same protocol, rate, and frequency. Sharing of a PLLreference clock pin also implies sharing of the reference clock the following guidelines for sharing the PLL reference clock share a PLL reference clock pin, connect the same signal to the pll_ref_clkport of multiple external memory interfaces in the RTL Place related external memory interfaces in the same I/O Place related external memory interfaces in adjacent I/O banks. If you leave anunused I/O bank between the I/O banks used by the external memory interfaces,that I/O bank cannot be used by any other external memory interface with adifferent PLL reference clock : You can place the pll_ref_clk pin in the address and command I/O bank or in adata I/O bank, there is no impact on timing. However, for greatest flexibility duringdebug (such as when creating designs with narrower interfaces), the recommendedplacement is in the address and command I/O Clock NetworkTo access all external memory interfaces synchronously and to reduce global clocknetwork usage, you may share the same core clock network with other externalmemory Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide179Observe the following guidelines for sharing the core clock share a core clock network, connect the clks_sharing_master_out of themaster to the clks_sharing_slave_in of all slaves in the RTL Place related external memory interfaces in the same I/O Related external memory interface must have the same rate, memory clockfrequency, and PLL reference BankTo reduce I/O bank utilization, you may share an I/O Bank with other externalmemory the following guidelines for sharing an I/O Bank:1. Related external memory interfaces must have the same protocol, rate, memoryclock frequency, and PLL reference You cannot use a given I/O bank as the address and command bank for more thanone external memory You cannot share an I/O lane between external memory interfaces, but an unusedpin can serve as a general purpose I/O pin, of compatible voltage and Nios ProcessorAll external memory interfaces residing in the same I/O column will share the samehard Nios processor. The shared hard Nios processor calibrates the external memoryinterfaces Ping-Pong PHY ImplementationThe Ping Pong PHY feature instantiates two hard memory controllers one for theprimary interface and one for the secondary interface. The hard memory controller I/Obank of the primary interface is used for address and command and is always adjacentand above the hard memory controller I/O bank of the secondary interface. All fourlanes of the primary hard memory controller I/O bank are used for address you use Ping Pong PHY, the EMIF IP exposes two independent Avalon-MMinterfaces to user logic; these interfaces correspond to the two hard memorycontrollers inside the interface. Each Avalon-MM interface has its own set of clock andreset signals. Refer to Platform Designer Interfaces for more information on theadditional signals exposed by Ping Pong PHY pin allocation information for Intel Stratix 10 devices, refer to External MemoryInterface Pin Information for Intel Stratix 10 Devices on Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide180Additional Requirements for DDR3 and DDR4 Ping-Pong PHY InterfacesIf you are using Ping Pong PHY with a DDR3 or DDR4 external memory interface on anIntel Stratix 10 device, follow these guidelines: The address and command I/O bank must not contain any DQS group. I/O banks that are above the address and command I/O bank must contain onlydata pins of the primary interface that is, the interface with the lower DQS groupindices. The I/O bank immediately below the address and command I/O bank must containat least one DQS group of the secondary interface that is, the interface with thehigher DQS group indices. This I/O bank can, but is not required to, contain DQSgroups of the primary interface. I/O banks that are two or more banks below the address and command I/O bankmust contain only data pins of the secondary Links Pin-Out Files for Intel FPGA Devices Functional Description Intel Stratix 10 EMIF IP External Memory Interface Pin Information for Intel Stratix 10 Devices Restrictions on I/O Bank Usage for Stratix 10 EMIF IP with DDR3 Board Design GuidelinesThe following topics provide guidelines for improving the signal integrity of yoursystem and for successfully implementing a DDR3 SDRAM interface on your following areas are discussed: comparison of various types of termination schemes, and their effects on thesignal quality on the receiver proper drive strength setting on the FPGA to optimize the signal integrity at thereceiver effects of different loading types, such as components versus DIMM configuration,on signal qualityIt is important to understand the trade-offs between different types of terminationschemes, the effects of output drive strengths, and different loading types, so thatyou can swiftly navigate through the multiple combinations and choose the bestpossible settings for your following key factors affect signal quality at the receiver: Leveling and dynamic ODT Proper use of termination Layout guidelinesAs memory interface performance increases, board designers must pay closerattention to the quality of the signal seen at the receiver because poorly transmittedsignals can dramatically reduce the overall data-valid margin at the receiver. Thefollowing figure shows the differences between an ideal and real signal seen by Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide181Figure and Real Signal at the ReceiverIdealRealVoltageVoltageVIHVIHVIL VILTimeTimeRelated Terminations for DDR3 and DDR4 with Intel Stratix 10 DevicesThe following topics describe considerations specific to DDR3 and DDR4 externalmemory interface protocols on Intel Stratix 10 Dynamic On-Chip Termination (OCT) in Intel Stratix 10 DevicesDepending upon the Rs (series) and Rt (parallel) OCT values that you want, youshould choose appropriate values for the RZQ resistor and connect this resistor to theRZQ pin of the FPGA. Select a 240-ohm reference resistor to ground to implement Rs OCT values of 34-ohm, 40-ohm, 48-ohm, 60-ohm, and 80-ohm, and Rt OCT resistance values of 20-ohm, 30-ohm, 34-ohm, 40-ohm, 60-ohm, 80-ohm, 120-ohm and 240 ohm. Select a 100-ohm reference resistor to ground to implement Rs OCT values of 25-ohm and 50-ohm, and an RT OCT resistance of the FPGA I/O tab of the parameter editor to determine the I/O standards andtermination values supported for data, address and command, and memory LinksChoosing Terminations on Intel Stratix 10 Devices on page Choosing Terminations on Intel Stratix 10 DevicesTo determine optimal on-chip termination (OCT) and on-die termination (ODT) valuesfor best signal integrity, you should simulate your memory interface in HyperLynx or asimilar the optimal OCT and ODT termination values as determined by simulation are notavailable in the list of available values in the parameter editor, select the closestavailable termination values for OCT and information about available ODT choices, refer to your memory vendor data Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide182Related LinksDynamic On-Chip Termination (OCT) in Intel Stratix 10 Devices on page On-Chip Termination Recommendations for Intel Stratix 10 Devices Output mode (drive strength) for Address/Command/Clock and Data Signals:Depending upon the I/O standard that you have selected, you would have a rangeof selections expressed in terms of ohms or miliamps. A value of 34 to 40 ohms or12 mA is a good starting point for output mode drive strength. Input mode (parallel termination) for Data and Data Strobe signals: A value of 40or 60 ohms is a good starting point for FPGA side input Channel Signal Integrity MeasurementAs external memory interface data rates increase, so does the importance of properchannel signal integrity measuring the actual channel loss during thelayout process and including that data in your parameterization, a realistic assessmentof margins is Importance of Accurate Channel Signal Integrity InformationDefault values for channel loss (or eye reductoin) can be used when calculating timingmargins, however those default values may not accurately reflect the channel loss inyour the channel loss in your system is different than the default values, thecalculated timing margins will vary your actual channel loss is greater than the default channel loss, and if you rely ondefault values, the available timing margins for the entire system will be lower thanthe values calculated during compilation. By relying on default values that do notaccurately reflect your system, you may be lead to believe that you have good timingmargin, while in reality, your design may require changes to achieve good channelsignal Understanding Channel Signal Integrity MeasurementTo measure channel signal integrity you need to measure the channel loss for a particular signal or signal trace, channel loss is defined as loss of the eyewidth at +/- VIH(ac and dc) +/- VIL(ac and dc). VIH/VIL above or below VREF is used toalign with various requirements of the timing model for memory example below shows a reference eye diagram where the channel loss on thesetup- or leading-side of the eye is equal to the channel loss on the hold- or lagging-side of the eye; howevever, it does not necessarily have to be that way. BecauseIntel's calibrating PHY will calibrate to the center of the read and write eye, the BoardSettings tab has parameters for the total extra channel loss for Write DQ and ReadDQ. For address and command signals which are not-calibrated, the Board Settingstab allows you to enter setup- and hold-side channel losses that are not equal,allowing the Intel Quartus Prime software to place the clock statically within the centerof the address and command Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide183Figure Setup and Hold-side How to Enter Calculated Channel Signal Integrity ValuesYou should enter calculated channel loss values in the Channel Signal Integritysection of the Board (or Board Timing) tab of the parameter Intel Stratix 10 external memory interfaces, the default channel loss displayed inthe parameter editor is based on the selected configuration (different values for singlerank versus dual rank), and on internal Intel reference boards. You should replace thedefault value with the value that you Guidelines for Calculating DDR3 Channel Signal IntegrityAddress and Command ISI and CrosstalkSimulate the address/command and control signals and capture eye at the DRAM pins,using the memory clock as the trgger for the memory interface's address/commandand control signals. Measure the setup and hold channel losses at the voltagethresholds mentioned in the memory vendor's data and command channel loss = Measured loss on the setup side + measuredloss on the hold = VDD/2 = mV for DDR3You should select the VIH and VIL voltage levels appropriately for the DDR3L memorydevice that you are using. Check with your memory vendor for the correct voltagelevels, as the levels may vary for different speed grades of following figure illustrates a DDR3 example where VIH(AC)/ VIL(AC) is +/- 150 mVand VIH(DC)/ VIL(DC) is +/- 100 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide184Figure DQ ISI and CrosstalkSimulate the write DQ signals and capture eye at the DRAM pins, using DQ Strobe(DQS) as a trigger for the DQ signals of the memory interface simulation. Measure thesetup and hold channel lossses at the VIH and VIL mentioned in the memory vendor'sdata sheet. The following figure illustrates a DDR3 example where VIH(AC)/ VIL(AC) is+/- 150 mV and VIH(DC)/ VIL(DC) is +/- 100 Channel Loss = Measured Loss on the Setup side + Measured Loss on the HoldsideVREF = VDD/2 = mV for DDR3Figure Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide185Read DQ ISI and CrosstalkSimulate read DQ signals and capture eye at the FPGA die. Do not measure at the pin,because you might see unwanted reflections that could create a false representation ofthe eye opening at the input buffer of the FPGA. Use DQ Strobe (DQS) as a trigger forthe DQ signals of your memory interface simulation. Measure the eye opening at +/-70 mV (VIH/VIL) with respect to Channel Loss = (UI) - (Eye opening at +/- 70 mV with respect to VREF)UI = Unit interval. For example, if you are running your interface at 800 Mhz, theeffective data is 1600 Mbps, giving a unit interval of 1/1600 = 625 psVREF = VDD/2 = mV for DDR3Figure DQS ISI and CrosstalkSimulate the Write/Read DQS and capture eye, and measure the uncertainty at = VDD/2 = mV for DDR35 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide186Figure Layout ApproachFor all practical purposes, you can regard the Timing Analyzer report on your memoryinterface as definitive for a given set of memory and board timing will find timing under Report DDR in the Timing Analyzer and on the TimingAnalysis tab in the parameter following flowchart illustrates the recommended process to follow during theboard design phase, to determine timing margin and make iterative improvements toyour Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide187Primary LayoutCalculate Setupand Hold DeratingCalculate ChannelSignal IntegrityCalculate BoardSkewsFind MemoryTiming ParametersGenerate an IP Core that Accurately Represents Your Memory Subsystem, Including pin-out and Accurate Parameters in the Parameter Editor s Board Settings TabRun Quartus Prime Compilation with the Generated IP CoreAny Non-Core TimingViolations in the ReportDDR Panel?yesnoDoneAdjust Layout to Improve: Trace Length Mis-Match Signal Reflections (ISI) Cross Talk Memory Speed GradeBoard SkewFor information on calculating board skew parameters, refer to Board Skew Equations,in this Board Skew Parameter Tool is an interactive tool that can help you calculate boardskew parameters if you know the absolute delay values for all the memory Timing ParametersFor information on the memory timing parameters to be entered into the parametereditor, refer to the datasheet for your external memory LinksBoard Skew Parameter Design Layout GuidelinesThe general layout guidelines in the following topic apply to DDR3 and DDR4 guidelines will help you plan your board layout, but are not meant as strict rulesthat must be adhered to. Intel recommends that you perform your own board-levelsimulations to ensure that the layout you choose for your board allows you to achieveyour desired Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide188For more information about how the memory manufacturers route these address andcontrol signals on their DIMMs, refer to the Cadence PCB browser from the Cadencewebsite, at The various JEDEC* example DIMM layouts areavailable from the JEDEC website, at assistance in calculating board skew parameters, refer to the board skewcalculator tool, which is available at the Intel : 1. The following layout guidelines include several +/- length based rules. Theselength based guidelines are for first order timing approximations if you cannotsimulate the actual delay characteristic of the interface. They do not include anymargin for To ensure reliable timing closure to and from the periphery of the device, signalsto and from the periphery should be registered before any further logic recommends that you get accurate time base skew numbers for your designwhen you simulate the specific Links Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits) on page195 Board Skew Parameter Tool General Layout GuidelinesThe following table lists general board design layout guidelines. These guidelines areIntel recommendations, and should not be considered as hard requirements. Youshould perform signal integrity simulation on all the traces to verify the signal integrityof the interface. You should extract the slew rate and propagation delay information,enter it into the IP and compile the design to ensure that timing requirements Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide189Table Layout GuidelinesParameterGuidelinesImpedance All unused via pads must be removed, because they cause unwantedcapacitance. Trace impedance plays an important role in the signal integrity. You mustperform board level simulation to determine the best characteristic impedancefor your PCB. For example, it is possible that for multi rank systems 40 ohmscould yield better results than a traditional 50 ohm characteristic Parameter Use uF in 0402 size to minimize inductance Make VTT voltage decoupling close to termination resistors Connect decoupling caps between VTT and ground Use a uF cap for every other VTT pin and uF cap for every VDD andVDDQ pin Verify the capacitive decoupling using the Intel Power Distribution NetworkDesign ToolPower Route GND and VCC as planes Route VCCIO for memories in a single split plane with at least a 20-mil( inches, or mm) gap of separation Route VTT as islands or 250-mil ( ) power traces Route oscillators and PLL power as islands or 100-mil ( ) power tracesGeneral RoutingAll specified delay matching requirements include PCB trace delays, different layerpropagation velocity variance, and crosstalk. To minimize PCB layer propogationvariance, Intel recommends that signals from the same net group always berouted on the same layer. Use 45 angles (not 90 corners) Avoid T-Junctions for critical nets or clocks Avoid T-junctions greater than 250 mils ( mm) Disallow signals across split planes Restrict routing other signals close to system reset signals Avoid routing memory signals closer than inch ( mm) to PCI orsystem clocksRelated LinksPower Distribution Layout GuidelinesThe following table lists layout otherwise specified, the guidelines in the following table apply to the followingtopologies: DIMM UDIMM topology DIMM RDIMM topology DIMM LRDIMM topology Not all versions of the Intel Quartus Prime software support LRDIMM. Discrete components laid out in UDIMM topology Discrete components laid out in RDIMM topologyThese guidelines are recommendations, and should not be considered as hardrequirements. You should perform signal integrity simulation on all the traces to verifythe signal integrity of the Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide190For supported frequencies and topologies, refer to the External Memory Interface SpecEstimator frequencies greater than 800 MHz, when you are calculating the delay associatedwith a trace, you must take the FPGA package delays into Guidelines (1)ParameterGuidelinesDecoupling Parameter Make VTT voltage decoupling close to the components and pull-up resistors. Connect decoupling caps between VTT and VDD using a F cap for everyother VTT pin. Use a uF cap and uF cap for every VDDQ Trace Length Even though there are no hard requirements for minimum trace length, youneed to simulate the trace to ensure the signal integrity. Shorter routes resultin better timing. For DIMM topology only: Maximum trace length for all signals from FPGA to the first DIMM slot is Maximum trace length for all signals from DIMM slot to DIMM slot is For discrete components only: Maximum trace length for address, command, control, and clock from FPGA tothe first component must not be more than 7 inches. Maximum trace length for DQ, DQS, DQS#, and DM from FPGA to the firstcomponent is 5 Routing Route over appropriate VCC and GND planes. Keep signal routing layers close to GND and power Guidelines Avoid routing two signal layers next to each other. Always make sure that thesignals related to memory interface are routed between appropriate GND orpower layers. For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) for these traces. (Where H is the vertical distance to the closest returnpath for that particular trace.) For Address/Command/Control traces: Maintain at least 3H spacing betweenthe edges (air-gap) these traces. (Where H is the vertical distance to theclosest return path for that particular trace.) For Clock traces: Maintain at least 5H spacing between two clock pair or aclock pair and any other memory interface trace. (Where H is the verticaldistance to the closest return path for that particular trace.)Clock Routing Route clocks on inner layers with outer-layer run lengths held to under 500mils ( mm). Route clock signals in a daisy chain topology from the first SDRAM to the lastSDRAM. The maximum length of the first SDRAM to the last SDRAM must notexceed tCK for DDR3 and tCK for DDR4. For different DIMMconfigurations, check the appropriate JEDEC specification. These signals should maintain the following spacings: Clocks should maintain a length-matching between clock pairs of 5 ps. Clocks should maintain a length-matching between positive (p) and negative(n) signals of 2 ps, routed in parallel. Space between different pairs should be at least two times the trace width ofthe differential pair to minimize loss and maximize interconnect density. To avoid mismatched transmission line to via, Intel recommends that you useGround Signal Signal Ground (GSSG) topology for your clock pattern GND|CLKP|CKLN|GND. Route all addresses and commands to match the clock signals to within 20 psto each discrete memory component. Refer to the following 5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide191ParameterGuidelinesAddress and Command Routing Route address and command signals in a daisy chain topology from the firstSDRAM to the last SDRAM. The maximum length of the first SDRAM to the lastSDRAM must not be more than tCK for DDR3 and tCK for DDR4. Fordifferent DIMM configurations, check the appropriate JEDEC specifications. UDIMMs are more susceptible to cross-talk and are generally noisier thanbuffered DIMMs. Therefore, route address and command signals of UDIMMs ona different layer than data signals (DQ) and data mask signals (DM) and withgreater spacing. Do not route differential clock (CK) and clock enable (CKE) signals close toaddress signals. Route all addresses and commands to match the clock signals to within 20 psto each discrete memory component. Refer to the following , DM, and DQS Routing Rules All the trace length matching requirements are from the FPGA package ball tothe SDRAM package ball, which means you must consider trace mismatchingon different DIMM raw cards. Match in length all DQ, DQS, and DM signals within a given byte-lane groupwith a maximum deviation of 10 ps. Ensure to route all DQ, DQS, and DM signals within a given byte-lane group onthe same layer to avoid layer to layer transmission velocity differences, whichotherwise increase the skew within the group. Do not count on FPGAs to deskew for more than 20 ps of DQ group skew. Theskew algorithm only removes the following possible uncertainties: Minimum and maximum die IOE skew or delay mismatch Minimum and maximum device package skew or mismatch Board delay mismatch of 20 ps Memory component DQ skew mismatch Increasing any of these four parameters runs the risk of the deskewalgorithm limiting, failing to correct for the total observed system skew. Ifthe algorithm cannot compensate without limiting the correction, timinganalysis shows reduced margins. For memory interfaces with leveling, the timing between the DQS and clocksignals on each device calibrates dynamically to meet tDQSS. To make surethe skew is not too large for the leveling circuit s capability, follow these rules: Propagation delay of clock signal must not be shorter than propagationdelay of DQS signal at every device: (CKi) DQSi > 0; 0 < i < number ofcomponents 1 . For DIMMs, ensure that the CK trace is longer than thelongest DQS trace at the DIMM connector. Total skew of CLK and DQS signal between groups is less than one clockcycle: (CKi+ DQSi) max (CKi+ DQSi) min < 1 tCK(If you are using aDIMM topology, your delay and skew must take into consideration valuesfor the actual DIMM.) 5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide192ParameterGuidelinesSpacing Guidelines Avoid routing two signal layers next to each other. Always ensure that thesignals related to the memory interface are routed between appropriate GNDor power layers. For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) of these traces, where H is the vertical distance to the closest return pathfor that particular trace. For Address/Command/Control traces: Maintain at least 3H spacing betweenthe edges (air-gap) of these traces, where H is the vertical distance to theclosest return path for that particular trace. For Clock traces: Maintain at least 5H spacing between two clock pairs or aclock pair and any other memory interface trace, where H is the verticaldistance to the closest return path for that particular Quartus Prime Software Settingsfor Board Layout To perform timing analyses on board and I/O buffers, use a third-partysimulation tool to simulate all timing information such as skew, ISI, crosstalk,and type the simulation result into the Board Settings tab in the parametereditor. Do not use advanced I/O timing model (AIOT) or board trace model unless youdo not have access to any third party tool. AIOT provides reasonable accuracybut tools like HyperLynx provide better to Table:1. For point-to-point and DIMM interface designs, refer to the Micron website, Links Package Deskew on page 198 External Memory Interface Spec Estimator Length Matching RulesThe following topics provide guidance on length matching for different types of all addresses and commands to match the clock signals to within 20 ps toeach discrete memory component. The following figure shows the component routingguidelines for address and command Component Address and Command Routing GuidelinesIf using discrete components:x = y 20 psx + x1 = y + y1 20 psx + x1 + x2 = y + y1 + y2 20 psaddress andcommandclockxyx1y1x2y2x3y3If using a DIMM topology: x=y +/- 20 psPropagation delay < for DDR3 VTTVTTSDRAMComponentSDRAMComponentSDRAMComponentSDRAMComponentFPGAx + x1 + x2 + x3 = y + y1 + y2 +y3 20 pstCKPropagation delay < for DDR4 tCK5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide193The timing between the DQS and clock signals on each device calibrates dynamicallyto meet tDQSS. The following figure shows the delay requirements to align DQS andclock signals. To ensure that the skew is not too large for the leveling circuit scapability, follow these rules: Propagation delay of clock signal must not be shorter than propagation delay ofDQS signal at every device:CKi DQSi > 0; 0 < i < number of components 1 Total skew of CLK and DQS signal between groups is less than one clock cycle:(CKi + DQSi) max (CKi + DQSi) min < 1 tCKFigure DQS Signal to Align DQS and ClockVTTSDRAMComponentDQ Group 0CKCK0CK1DSQiCKiCKi = Clock signal propagation delay to device iFPGASDRAMComponentSDRAMComponentDQ Group 1DQ Group iDQSi = DQ/DQS signals propagation delay to group iClk pair matching If you are using a DIMM (UDIMM, RDIMM, or LRDIMM) topology,match the trace lengths up to the DIMM connector. If you are using discretecomponents, match the lengths for all the memory components connected in the fly-by group length matching If you are using a DIMM (UDIMM, RDIMM, or LRDIMM)topology, apply the DQ group trace matching rules described in the guideline tableearlier up to the DIMM connector. If you are using discrete components, match thelengths up to the respective memory you are using DIMMs, it is assumed that lengths are tightly matched within theDIMM itself. You should check that appropriate traces are length-matched within Spacing GuidelinesThis topic provides recommendations for minimum spacing between board traces forvarious signal Guidelines for DQ, DQS, and DM TracesMaintain a minimum of 3H spacing between the edges (air-gap) of these traces.(Where H is the vertical distance to the closest return path for that particular trace.) GND or Power3HHGND or PowerH5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide194Spacing Guidelines for Address and Command and Control TracesMaintain at least 3H spacing between the edges (air-gap) of these traces. (Where H isthe vertical distance to the closest return path for that particular trace.) GND or Power3HHGND or PowerHSpacing Guidelines for Clock TracesMaintain at least 5H spacing between two clock pair or a clock pair and any othermemory interface trace. (Where H is the vertical distance to the closest return path forthat particular trace.) 5HGND or PowerHHGND or Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits)The following topics discuss different ways to lay out a wider DDR3 or DDR4 SDRAMinterface to the FPGA. Choose the topology based on board trace simulation and thetiming budget of your EMIF IP supports up to a 144-bit wide DDR3 interface. You can use discretecomponents or DIMMs to implement a wide interface (any interface wider than 72bits). Intel recommends using leveling when you implement a wide interface withDDR3 you lay out for a wider interface, all rules and constraints discussed in theprevious sections still apply. The DQS, DQ, and DM signals are point-to-point, and allthe same rules discussed in Design Layout Guidelines main challenge for the design of the fly-by network topology for the clock,command, and address signals is to avoid signal integrity issues, and to make sureyou route the DQS, DQ, and DM signals with the chosen LinksDesign Layout Guidelines on page Fly-By Network Design for Clock, Command, and Address SignalsThe EMIF IP requires the flight-time skew between the first SDRAM component andthe last SDRAM component to be less than tCK for memory clocks. Thisconstraint limits the number of components you can have for each fly-by you design with discrete components, you can choose to use one or more fly-bynetworks for the clock, command, and address following figure shows an example of a single fly-by network Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide195Figure Fly-By Network TopologyVTTFPGADDR3SDRAMDDR3SDRAMDDR3SDR AMDDR3SDRAMDDR3SDRAMDDR3SDRAMLess than tCKEvery SDRAM component connected to the signal is a small load that causesdiscontinuity and degrades the signal. When using a single fly-by network topology, tominimize signal distortion, follow these guidelines: Use 16 device instead 4 or 8 to minimize the number of devices connected tothe trace. Keep the stubs as short as possible. Even with added loads from additional components, keep the total trace lengthshort; keep the distance between the FPGA and the first SDRAM component lessthan 5 inches. Simulate clock signals to ensure a decent following figure shows an example of a double fly-by network topology. Thistopology is not rigid but you can use it as an alternative option. The advantage ofusing this topology is that you can have more SDRAM components in a system withoutviolating the tCK rule. However, as the signals branch out, the components stillcreate Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide196Figure Fly-By Network TopologyDDR3SDRAMDDR3SDRAMDDR3SDRAMDDR3S DRAMDDR3SDRAMDDR3SDRAMLess than tFPGADDR3SDRAMDDR3SDRAMDDR3SDRAMDDR3SDRA MDDR3SDRAMDDR3SDRAMLess than tVTTVTTCKCKYou must perform simulations to find the location of the split, and the best impedancefor the traces before and after the following figure shows a way to minimize the discontinuity effect. In this example,keep TL2 and TL3 matches in length. Keep TL1 longer than TL2 and TL3, so that it iseasier to route all the signals during Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide197Figure Discontinuity EffectSplitting PointTL3, ZQ = 50 TL1, ZQ = 25 TL2, ZQ = 50 You can also consider using a DIMM on each branch to replace the the trade impedance on the DIMM card is 40-ohm to 60-ohm, perform aboard trace simulation to control the reflection to within the level your system the fly-by daisy chain topology increases the complexity of the datapath andcontroller design to achieve leveling, but also greatly improves performance and easesboard layout for SDRAM can also use the SDRAM components without leveling in a design if it may resultin a more optimal solution, or use with devices that support the required electricalinterface standard, but do not support the required read and write Package DeskewTrace lengths inside the device package are not uniform for all package pins. Thenonuniformity of package traces can affect system timing for high frequencies. Apackage deskew option is available in the Intel Quartus Prime you do not enable the package deskew option, the Intel Quartus Prime softwareuses the package delay numbers to adjust skews on the appropriate signals; you donot need to adjust for package delays on the board traces. If you do enable thepackage deskew option, the Intel Quartus Prime software does not use the packagedelay numbers for timing analysis, and you must deskew the package delays with theboard traces for the appropriate signals for your LinksLayout Guidelines on page DQ/DQS/DM DeskewTo get the package delay information, follow these steps:5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide1981. Select the FPGA DQ/DQS Package Skews Deskewed on Board checkbox onthe Board Settings tab of the parameter Generate your Instantiate your IP in the Compile your Refer to the All Package Pins compilation report, or find the pin delays displayedin the <core_name>.pin Address and Command DeskewDeskew address and command delays as follows:1. Select the FPGA Address/Command Package Skews Deskewed on Boardcheckbox on the Board Settings tab of the parameter Generate your Instantiate your IP in the Compile your Refer to the All Package Pins compilation report, or find the pin delays displayedin the <core_name>.pin Package Deskew Recommendations for Intel Stratix 10 DevicesThe following table shows package deskew recommendations for Intel Stratix operating frequencies increase, it becomes increasingly critical to perform packagedeskew. The frequencies listed in the table are the minimum frequencies for which youmust perform package you plan to use a listed protocol at the specified frequency or higher, you mustperform package Frequency (MHz) for Which to Perform Package DeskewSingle RankDual RankQuad RankDDR4933800667DDR3933800667LPDDR36675 33Not requiredQDR IV933Not applicableNot applicableRLDRAM 3933667Not applicableQDR II, II+, II+ XtremeNot requiredNot applicableNot Deskew ExampleConsider an example where you want to deskew an interface with 4 DQ pins, 1 DQSpin, and 1 DQSn Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide199Let s assume an operating frequency of 667 MHz, and the package lengths for the pinsreported in the .pin file as follows:dq[0] = 120 psdq[1] = 120 psdq[2] = 100 psdq[3] = 100 psdqs = 80 psdqs_n = 80 psThe following figure illustrates this ExampleFPGA mem_dq[0]mem_dq[1]mem_dq[2]mem_dq[3]mem_ dqsmem_dqs_nmem_dq[0]mem_dq[1]mem_dq[2]m em_dq[3]mem_dqsmem_dqs_nMemory120 ps120 ps100 ps100 ps80 ps80 psABCDEFWhen you perform length matching for all the traces in the DQS group, you must takepackage delays into consideration. Because the package delays of traces A and B are40 ps longer than the package delays of traces E and F, you would need to make theboard traces for E and F 40 ps longer than the board traces for A and similar methodology would apply to traces C and D, which should be 20 ps longerthan the lengths of traces A and following figure shows this scenario with the length of trace A at 450 Example with Trace Delay CalculationsFPGAmem_dq[0]mem_dq[1]mem_dq [2]mem_dq[3]mem_dqsmem_dqs_nmem_dq[0]mem _dq[1]mem_dq[2]mem_dq[3]mem_dqsmem_dqs_n Memory120 ps120 ps100 ps100 ps80 ps80 psA=450psB=A=450psC=A+20ps=470psC=A+20ps =470psC=A+40ps=490psC=A+40ps=490ps5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide200When you enter the board skews into the Board Settings tab of the DDR3 parametereditor, you should calculate the board skew parameters as the sums of board delayand corresponding package delay. If a pin does not have a package delay (such asaddress and command pins), you should use the board delay example of the preceding figure shows an ideal case where board skews areperfectly matched. In reality, you should allow plus or minus 10 ps of skew mismatchwithin a DQS group (DQ/DQS/DM).5 Intel Stratix 10 EMIF IP for DDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide2016 Intel Stratix 10 EMIF IP for DDR4This chapter contains IP parameter descriptions, board skew equations, pin planninginformation, and board design guidance for Intel Stratix 10 external memoryinterfaces for Parameter DescriptionsThe following topics describe the parameters available on each tab of the IP parametereditor, which you can use to configure your Intel Stratix 10 EMIF IP DDR4 Parameters: GeneralTable : General / InterfaceDisplay NameDescriptionConfigurationSpecifies the configuration of the memory interface. The available optionsdepend on the protocol in use. Options include Hard PHY and HardController, Hard PHY and Soft Controller, or Hard PHY only. If youselect Hard PHY only, the AFI interface is exported to allow connection ofa custom memory controller or third-party IP. (Identifier:PHY_DDR4_CONFIG_ENUM)Instant iate two controllers sharing aPing Pong PHYSpecifies the instantiation of two identical memory controllers that share anaddress/command bus through the use of Ping Pong PHY. This parameter isavailable only if you specify the Hard PHY and Hard Controller this parameter is enabled, the IP exposes two independent Avaloninterfaces to the user logic, and a single external memory interface withdouble width for the data bus and the CS#, CKE, ODT, and CK/CK# signals.(Identifier: PHY_DDR4_USER_PING_PONG_EN)Table : General / ClocksDisplay NameDescriptionMemory clock frequencySpecifies the operating frequency of the memory interface in MHz. If youchange the memory frequency, you should update the memory latencyparameters on the Memory tab and the memory timing parameters on theMem Timing tab. (Identifier: PHY_DDR4_MEM_CLK_FREQ_MHZ)Use recommended PLL reference clockfrequencySpecifies that the PLL reference clock frequency is automatically calculatedfor best performance. If you want to specify a different PLL reference clockfrequency, uncheck the check box for this parameter. (Identifier:PHY_DDR4_DEFAULT_REF_CLK_FRE Q)PLL reference clock frequencyThis parameter tells the IP what PLL reference clock frequency the user willsupply. Users must select a valid PLL reference clock frequency from thelist. The values in the list can change when the memory interface frequencychanges and/or the clock rate of user logic changes. It is recommended UG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008RegisteredDisplay NameDescriptionuse the fastest possible PLL reference clock frequency because it leads tobetter jitter performance. Selection is required only if the user does notcheck the "Use recommended PLL reference clock frequency" option.(Identifier: PHY_DDR4_USER_REF_CLK_FREQ_MHZ)PLL reference clock jitterSpecifies the peak-to-peak jitter on the PLL reference clock source. Theclock source of the PLL reference clock must meet or exceed the followingjitter requirements: 10ps peak to peak, or RMS at 1e-12 BER, at 1e-16 BER. (Identifier: PHY_DDR4_REF_CLK_JITTER_PS)Clock rate of user logicSpecifies the relationship between the user logic clock frequency and thememory clock frequency. For example, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz, a quarter-rate interfacemeans that the user logic in the FPGA runs at 200MHz. (Identifier:PHY_DDR4_RATE_ENUM)Core clocks sharingWhen a design contains multiple interfaces of the same protocol, rate,frequency, and PLL reference clock source, they can share a common set ofcore clock domains. By sharing core clock domains, they reduce clocknetwork usage and avoid clock synchronization logic between share core clocks, denote one of the interfaces as "Master", and theremaining interfaces as "Slave". In the RTL, connect theclks_sharing_master_out signal from the master interface to theclks_sharing_slave_in signal of all the slave master and slave interfaces still expose their own output clock ports inthe RTL (for example, emif_usr_clk, afi_clk), but the physical signalsare equivalent, hence it does not matter whether a clock port from a masteror a slave is used. As the combined width of all interfaces sharing the samecore clock increases, you may encounter timing closure difficulty fortransfers between the FPGA core and the periphery.(Identifier: PHY_DDR4_CORE_CLKS_SHARING_ENUM)Specify additional core clocks based onexisting PLLDisplays additional parameters allowing you to create additional outputclocks based on the existing PLL. This parameter provides an alternativeclock-generation mechanism for when your design exhaustsavailable PLL resources. The additional output clocks that you create canbe fed into the core. Clock signals created with this parameter aresynchronous to each other, but asynchronous to the memory interface coreclock domains (such as emif_usr_clk or afi_clk). You must followproper clock-domain-crossing techniques when transferring data betweenclock domains. (Identifier: PLL_ADD_EXTRA_CLKS)Table : General / Clocks / Additional Core ClocksDisplay NameDescriptionNumber of additional core clocksSpecifies the number of additional output clocks to create from the PLL.(Identifier: PLL_USER_NUM_OF_EXTRA_CLKS)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_0Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_5)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_5)6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide203Table : General / Clocks / Additional Core Clocks / pll_extra_clk_1Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_6)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_6)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_2Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_7)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_7)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_3Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_8)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_8) Intel Stratix 10 EMIF IP DDR4 Parameters: MemoryTable : Memory / TopologyDisplay NameDescriptionMemory formatSpecifies the format of the external memory device. The following formatsare supported: Component - a Discrete memory device; UDIMM -Unregistered/Unbuffered DIMM where address/control, clock, and data areunbuffered; RDIMM - Registered DIMM where address/control and clockare buffered; LRDIMM - Load Reduction DIMM where address/control,clock, and data are buffered. LRDIMM reduces the load to increasememory speed and supports higher densities than RDIMM; SODIMM -Small Outline DIMM is similar to UDIMM but smaller in size and is typicallyused for systems with limited space. Some memory protocols may not beavailable in all formats. (Identifier: MEM_DDR4_FORMAT_ENUM)DQ widthSpecifies the total number of data pins in the interface. The maximumsupported width is 144, or 72 in Ping Pong PHY mode. (Identifier:MEM_DDR4_DQ_WIDTH)DQ pins per DQS groupSpecifies the total number of DQ pins per DQS group. (Identifier:MEM_DDR4_DQ_PER_DQS)Number of clocksSpecifies the number of CK/CK# clock pairs exposed by the memoryinterface. Usually more than 1 pair is required for RDIMM/LRDIMM value of this parameter depends on the memory device selected; referto the data sheet for your memory device. (Identifier:MEM_DDR4_CK_WIDTH)Number of chip selectsSpecifies the total number of chip selects in the interface, up to a maximumof 4. This parameter applies to discrete components only. (Identifier:MEM_DDR4_DISCRETE_CS_WIDTH)N umber of DIMMsTotal number of DIMMs. (Identifier: MEM_DDR4_NUM_OF_DIMMS) 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide204Display NameDescriptionChip ID widthSpecifies the number of chip ID pins. Only applicable to registered andload-reduced DIMMs that use 3DS/TSV memory devices. (Identifier:MEM_DDR4_CHIP_ID_WIDTH)Numbe r of physical ranks per DIMMNumber of ranks per DIMM. For LRDIMM, this represents the number ofphysical ranks on the DIMM behind the memory buffer (Identifier:MEM_DDR4_RANKS_PER_DIMM)Numb er of clock enables per DIMMNumber of clock enables ( CKE) per DIMM. Only applicable to registeredand load-reduced DIMMs. (Identifier: MEM_DDR4_CKE_PER_DIMM)Row address widthSpecifies the number of row address pins. Refer to the data sheet for yourmemory device. The density of the selected memory device determines thenumber of address pins needed for access to all available rows. (Identifier:MEM_DDR4_ROW_ADDR_WIDTH)Colu mn address widthSpecifies the number of column address pins. Refer to the data sheet foryour memory device. The density of the selected memory devicedetermines the number of address pins needed for access to all availablecolumns. (Identifier: MEM_DDR4_COL_ADDR_WIDTH)Bank address widthSpecifies the number of bank address pins. Refer to the data sheet for yourmemory device. The density of the selected memory device determines thenumber of bank address pins needed for access to all available banks.(Identifier: MEM_DDR4_BANK_ADDR_WIDTH)Bank group widthSpecifies the number of bank group pins. Refer to the data sheet for yourmemory device. The density of the selected memory device determines thenumber of bank group pins needed for access to all available bank groups.(Identifier: MEM_DDR4_BANK_GROUP_WIDTH)Data maskIndicates whether the interface uses data mask (DM) pins. This featureallows specified portions of the data bus to be written to memory (notavailable in x4 mode). One DM pin exists per DQS group. (Identifier:MEM_DDR4_DM_EN)Write DBIIndicates whether the interface uses write data bus inversion (DBI). Thisfeature provides better signal integrity and write margin. This featureis unavailable if Data Mask is enabled or in x4 mode. (Identifier:MEM_DDR4_WRITE_DBI)Read DBISpecifies whether the interface uses read data bus inversion (DBI). Enablethis feature for better signal integrity and read margin. This feature isnot available in x4 configurations. (Identifier: MEM_DDR4_READ_DBI)Enable address mirroring for odd chip-selectsEnabling address mirroring for multi-CS discrete components. Typically usedwhen components are arranged in a clamshell layout. (Identifier:MEM_DDR4_DISCRETE_MIRROR_ADD RESSING_EN)Enable address mirroring for odd ranksEnabling address mirroring for dual-rank or quad-rank DIMM. (Identifier:MEM_DDR4_MIRROR_ADDRESSING_E N)Enable ALERT#/PAR pinsAllows address/command calibration, which may provide better margins onthe address/command bus. The alert_n signal is not accessible in the AFIor Avalon domains. This means there is no way to know whether a parityerror has occurred during user mode. The parity pin is a dedicated pin inthe address/command bank, but the alert_n pin can be placed in anybank that spans the memory interface. You should explicitly choose thelocation of the alert_n pin and place it in the address/command bank.(Identifier: MEM_DDR4_ALERT_PAR_EN)ALERT# pin placementSpecifies placement for the mem_alert_n signal. If you select "I/O Lanewith Address/Command Pins", you can pick the I/O lane and pin indexin the add/cmd bank with the subsequent drop down menus. If you select"I/O Lane with DQS Group", you can specify the DQS group with whichto place the mem_alert_n pin. If you select "Automatically select alocation", the IP automatically selects a pin for the mem_alert_n you select this option, no additional location constraints can be applied 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide205Display NameDescriptionthe mem_alert_n pin, or a fitter error will result during compilation. Foroptimum signal integrity, you should choose "I/O Lane with Address/Command Pins". For interfaces containing multiple memory devices, it isrecommended to connect the ALERT# pins together to the ALERT# pin onthe FPGA. (Identifier: MEM_DDR4_ALERT_N_PLACEMENT_ENUM)DQS group of ALERT#Select the DQS group with which the ALERT# pin is placed. (Identifier:MEM_DDR4_ALERT_N_DQS_GROUP)A ddress/command I/O lane of ALERT#Select the lane of the Address/Command I/O Tile where ALERT# pin isplaced. (Identifier: MEM_DDR4_ALERT_N_AC_LANE)Pin index of ALERT#Select the pin of the Address/Command I/O Lane where ALERT# pin isplaced. (Identifier: MEM_DDR4_ALERT_N_AC_PIN)Table : Memory / Latency and BurstDisplay NameDescriptionMemory CAS latency settingSpecifies the number of clock cycles between the read command and theavailability of the first bit of output data at the memory device. Overall readlatency equals the additive latency (AL) + the CAS latency (CL). Overallread latency depends on the memory device selected; refer to thedatasheet for your device. (Identifier: MEM_DDR4_TCL)Memory write CAS latency settingSpecifies the number of clock cycles from the release of internal write tothe latching of the first data in at the memory device. This value dependson the memory device selected; refer to the datasheet for your device.(Identifier: MEM_DDR4_WTCL)Memory additive CAS latency settingDetermines the posted CAS additive latency of the memory device. Enablethis feature to improve command and bus efficiency, and increasesystem bandwidth. (Identifier: MEM_DDR4_ATCL_ENUM)Table : Memory / Mode Register SettingsDisplay NameDescriptionHide advanced mode register settingsShow or hide advanced mode register settings. Changing advanced moderegister settings to non-default values is strongly discouraged. (Identifier:MEM_DDR4_HIDE_ADV_MR_SETTING S)Addr/CMD parity latencyAdditional latency incurred by enabling address/command parity check aftercalibration. Select a value to enable address/command parity with thelatency associated with the selected value. Select Disable to disableaddress/command parity. Address/command is enabled automatically andas-needed during calibration regardless of the value of this setting.(Identifier: MEM_DDR4_AC_PARITY_LATENCY)Burst LengthSpecifies the DRAM burst length which determines how many consecutiveaddresses should be accessed for a given read/write command. (Identifier:MEM_DDR4_BL_ENUM)Read Burst TypeIndicates whether accesses within a given burst are in sequential orinterleaved order. Select sequential if you are using the Intel-providedmemory controller. (Identifier: MEM_DDR4_BT_ENUM)Enable the DLL in memory deviceEnable the DLL in memory device (Identifier: MEM_DDR4_DLL_EN)Auto self-refresh methodIndicates whether to enable or disable auto self-refresh. Auto self-refreshallows the controller to issue self-refresh requests, rather than manuallyissuing self-refresh in order for memory to retain data. (Identifier:MEM_DDR4_ASR_ENUM)Write CRC enableWrite CRC enable (Identifier: MEM_DDR4_WRITE_CRC) 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide206Display NameDescriptionDDR4 geardown modeSet DDR4 geardown mode for control signals at high frequency (Identifier:MEM_DDR4_GEARDOWN)Per-DRAM addressabilityPer-DRAM addressability enable (Identifier: MEM_DDR4_PER_DRAM_ADDR)Temperature sensor readoutTemperature sensor readout enable (Identifier:MEM_DDR4_TEMP_SENSOR_READOUT )Fine granularity refreshIncreased frequency of refresh in exchange for shorter refresh. ShortertRFC and increased cycle time can produce higher bandwidth. (Identifier:MEM_DDR4_FINE_GRANULARITY_RE FRESH)MPR read formatMultipurpose register readout format (Identifier:MEM_DDR4_MPR_READ_FORMAT)Max imum power down modeMaximum power down mode (Identifier: MEM_DDR4_MAX_POWERDOWN)Temperature controlled refresh rangeIndicates temperature controlled refresh range where normal temperaturemode covers 0C to 85C and extended mode covers 0C to 95C. (Identifier:MEM_DDR4_TEMP_CONTROLLED_RFS H_RANGE)Temperature controlled refresh enableIndicates whether to enable temperature controlled refresh, which allowsthe device to adjust the internal refresh period to be longer than tREFI ofthe normal temperature range by skipping external refresh commands.(Identifier: MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA)Intern al VrefDQ monitorIndicates whether to enable the internal VrefDQ monitor. (Identifier:MEM_DDR4_INTERNAL_VREFDQ_MON ITOR)CS to Addr/CMD LatencyCS to Addr/CMD Latency (CAL mode) for idle state DRAM receiver powerreduction (Identifier: MEM_DDR4_CAL_MODE)Self refresh abortSelf refresh abort for latency reduction. (Identifier:MEM_DDR4_SELF_RFSH_ABORT)Rea d preamble training mode enableRead preamble training mode enable (Identifier:MEM_DDR4_READ_PREAMBLE_TRAIN ING)Read preambleNumber of read preamble cycles. This mode register setting determines thenumber of cycles DQS (read) will go low before starting to toggle.(Identifier: MEM_DDR4_READ_PREAMBLE)Write preambleWrite preamble cycles. (Identifier: MEM_DDR4_WRITE_PREAMBLE)ODT input buffer during powerdownmodeIndicates whether to enable on-die termination (ODT) input buffer duringpowerdown mode. (Identifier: MEM_DDR4_ODT_IN_POWERDOWN)Addr/CMD persistent errorIf set, Addr/CMD parity errors continue to be checked after a previousAddr/CMD parity error (Identifier: MEM_DDR4_AC_PERSISTENT_ERROR) Intel Stratix 10 EMIF IP DDR4 Parameters: Mem I/OTable : Mem I/O / Memory I/O SettingsDisplay NameDescriptionOutput drive strength settingSpecifies the output driver impedance setting at the memory device. Toobtain optimum signal integrity performance, select option based onboard simulation results. (Identifier: MEM_DDR4_DRV_STR_ENUM)Dynamic ODT (Rtt_WR) valueSpecifies the mode of the dynamic on-die termination (ODT) during writesto the memory device (used for multi-rank configurations). For optimumsignal integrity performance, select this option based on boardsimulation results. (Identifier: MEM_DDR4_RTT_WR_ENUM) 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide207Display NameDescriptionODT Rtt nominal valueDetermines the nominal on-die termination value applied to the DRAM. Thetermination is applied any time that ODT is asserted. If you specify adifferent value for RTT_WR, that value takes precedence over the valuesmentioned here. For optimum signal integrity performance, select youroption based on board simulation results. (Identifier:MEM_DDR4_RTT_NOM_ENUM)RTT PARKIf set, the value is applied when the DRAM is not being written AND ODT isnot asserted HIGH. (Identifier: MEM_DDR4_RTT_PARK)RCD CA Input Bus TerminationSpecifies the input termination setting for the following pins of theregistering clock driver: , , , DACT_n,DC2, DPAR. This parameter determines the value of bits DA[1:0] of controlword RC7x of the registering clock driver. Perform board simulation toobtain the optimal value for this setting. (Identifier:MEM_DDR4_RCD_CA_IBT_ENUM)RCD DCS[3:0]_n Input Bus TerminationSpecifies the input termination setting for the following pins of theregistering clock driver: DCS[3:0]_n. This parameter determines the valueof bits DA[3:2] of control word RC7x of the registering clock board simulation to obtain the optimal value for thissetting. (Identifier: MEM_DDR4_RCD_CS_IBT_ENUM)RCD DCKE Input Bus TerminationSpecifies the input termination setting for the following pins of theregistering clock driver: DCKE0, DCKE1. This parameter determines thevalue of bits DA[5:4] of control word RC7x of the registering clock board simulation to obtain the optimal value for thissetting. (Identifier: MEM_DDR4_RCD_CKE_IBT_ENUM)RCD DODT Input Bus TerminationSpecifies the input termination setting for the following pins of theregistering clock driver: DODT0, DODT1. This parameter determines thevalue of bits DA[7:6] of control word RC7x of the registering clock board simulation to obtain the optimal value for thissetting. (Identifier: MEM_DDR4_RCD_ODT_IBT_ENUM)DB Host Interface DQ RTT_NOMSpecifies the RTT_NOM setting for the host interface of the data buffer. Only"RTT_NOM disabled" is supported. This parameter determines the value ofthe control word BC00 of the data buffer. (Identifier:MEM_DDR4_DB_RTT_NOM_ENUM)DB Host Interface DQ RTT_WRSpecifies the RTT_WR setting of the host interface of the data buffer. Thisparameter determines the value of the control word BC01 of the databuffer. Perform board simulation to obtain the optimal value for thissetting. (Identifier: MEM_DDR4_DB_RTT_WR_ENUM)DB Host Interface DQ RTT_PARKSpecifies the RTT_PARK setting for the host interface of the data parameter determines the value of control word BC02 of the databuffer. Perform board simulation to obtain the optimal value for thissetting. (Identifier: MEM_DDR4_DB_RTT_PARK_ENUM)DB Host Interface DQ DriverSpecifies the driver impedance setting for the host interface of the databuffer. This parameter determines the value of the control word BC03 of thedata buffer. Perform board simulation to obtain the optimal value forthis setting. (Identifier: MEM_DDR4_DB_DQ_DRV_ENUM)Use recommended initial VrefDQ valueSpecifies to use the recommended initial VrefDQ value. This value is usedas a starting point and may change after calibration. (Identifier:MEM_DDR4_DEFAULT_VREFOUT)Vre fDQ training valueVrefDQ training value. (Identifier:MEM_DDR4_USER_VREFDQ_TRAININ G_VALUE)VrefDQ training rangeVrefDQ training range. (Identifier:MEM_DDR4_USER_VREFDQ_TRAININ G_RANGE)6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide208Table : Mem I/O / RDIMM/LRDIMM Serial Presence Detect (SPD) DataDisplay NameDescriptionSPD Byte 137 - RCD Drive Strength forCommand/AddressSpecifies the drive strength of the registering clock driver's control andcommand/address outputs to the DRAM. The value must come from Byte137 of the SPD from the DIMM vendor. (Identifier:MEM_DDR4_SPD_137_RCD_CA_DRV) SPD Byte 138 - RCD Drive Strength forCKSpecifies the drive strength of the registering clock driver's clock outputs tothe DRAM. The value must come from Byte 138 of the SPD from theDIMM vendor. (Identifier: MEM_DDR4_SPD_138_RCD_CK_DRV)SPD Byte 140 - DRAM VrefDQ forPackage Rank 0Specifies the VrefDQ setting for package rank 0 of an LRDIMM. The valuemust come from Byte 140 of the SPD from the DIMM vendor. (Identifier:MEM_DDR4_SPD_140_DRAM_VREFDQ _R0)SPD Byte 141 - DRAM VrefDQ forPackage Rank 1Specifies the VrefDQ setting for package rank 1 of an LRDIMM. The valuemust come from Byte 141 of the SPD from the DIMM vendor. (Identifier:MEM_DDR4_SPD_141_DRAM_VREFDQ _R1)SPD Byte 142 - DRAM VrefDQ forPackage Rank 2Specifies the VrefDQ setting for package rank 2 (if it exists) of an value must come from Byte 142 of the SPD from the DIMM vendor.(Identifier: MEM_DDR4_SPD_142_DRAM_VREFDQ_R2)SPD Byte 143 - DRAM VrefDQ forPackage Rank 3Specifies the VrefDQ setting for package rank 3 (if it exists) of an value must come from Byte 143 of the SPD from the DIMM vendor.(Identifier: MEM_DDR4_SPD_143_DRAM_VREFDQ_R3)SPD Byte 144 - DB VrefDQ for DRAMInterfaceSpecifies the VrefDQ setting of the data buffer's DRAM interface. The valuemust come from Byte 144 of the SPD from the DIMM vendor. (Identifier:MEM_DDR4_SPD_144_DB_VREFDQ)S PD Byte 145-147 - DB MDQ DriveStrength and RTTSpecifies the drive strength of the MDQ pins of the data buffer's DRAMinterface. The value must come from either Byte 145 (data rate =1866), 146 (1866 data rate = 2400), or 147 (2400 data rate =3200) of the SPD from the DIMM vendor. (Identifier:MEM_DDR4_SPD_145_DB_MDQ_DRV) SPD Byte 148 - DRAM Drive StrengthSpecifies the drive strength of the DRAM. The value must come from Byte148 of the SPD from the DIMM vendor. (Identifier:MEM_DDR4_SPD_148_DRAM_DRV)SP D Byte 149-151 - DRAM ODT(RTT_WR and RTT_NOM)Specifies the RTT_WR and RTT_NOM setting of the DRAM. The value mustcome from either Byte 149 (data rate = 1866), 150 (1866 data rate= 2400), or 151 (2400 data rate = 3200) of the SPD from the DIMMvendor. (Identifier: MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM)SPD Byte 152-154 - DRAM ODT(RTT_PARK)Specifies the RTT_PARK setting of the DRAM. The value must come fromeither Byte 152 (data rate = 1866), 153 (1866 data rate = 2400), or154 (2400 data rate = 3200) of the SPD from the DIMM vendor.(Identifier: MEM_DDR4_SPD_152_DRAM_RTT_PARK)RCD and DB Manufacturer (LSB)Specifies the LSB of the ID code of the registering clock driver and databuffer manufacturer. The value must come from Byte 133 of the SPD fromthe DIMM vendor. (Identifier:MEM_DDR4_SPD_133_RCD_DB_VEND OR_LSB)RCD and DB Manufacturer (MSB)Specifies the MSB of the ID code of the registering clock driver and databuffer manufacturer. The value must come from Byte 134 of the SPD fromthe DIMM vendor. (Identifier:MEM_DDR4_SPD_134_RCD_DB_VEND OR_MSB)RCD Revision NumberSpecifies the die revision of the registering clock driver. The value mustcome from Byte 135 of the SPD from the DIMM vendor. (Identifier:MEM_DDR4_SPD_135_RCD_REV)DB Revision NumberSpecifies the die revision of the data buffer. The value must come fromByte 139 of the SPD from the DIMM vendor. (Identifier:MEM_DDR4_SPD_139_DB_REV)6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide209Table : Mem I/O / ODT ActivationDisplay NameDescriptionUse Default ODT Assertion TablesEnables the default ODT assertion pattern as determined from vendorguidelines. These settings are provided as a default only; you shouldsimulate your memory interface to determine the optimal ODT settings andassertion patterns. (Identifier: MEM_DDR4_USE_DEFAULT_ODT) Intel Stratix 10 EMIF IP DDR4 Parameters: FPGA I/OYou should use Hyperlynx* or similar simulators to determine the best settings foryour board. Refer to the EMIF Simulation Guidance wiki page for : FPGA I/O / FPGA I/O SettingsDisplay NameDescriptionVoltageThe voltage level for the I/O pins driving the signals between the memorydevice and the FPGA memory interface. (Identifier:PHY_DDR4_IO_VOLTAGE)Periodic OCT re-calibrationSpecifies that the system periodically recalibrate on-chip termination (OCT)to minimize variations in termination value caused by changing operatingconditions (such as changes in temperature). By recalibrating OCT, I/Otiming margins are improved. When enabled, this parameter causes thePHY to halt user traffic about every seconds for about 1900 memoryclock cycles, to perform OCT recalibration. Efficiency is reduced byabout 1% when this option is enabled. (Identifier:PHY_DDR4_USER_PERIODIC_OCT_R ECAL_ENUM)Use default I/O settingsSpecifies that a legal set of I/O settings are automatically selected. Thedefault I/O settings are not necessarily optimized for a specific board. Toachieve optimal signal integrity, perform I/O simulations with IBIS modelsand enter the I/O settings manually, based on simulation results.(Identifier: PHY_DDR4_DEFAULT_IO)Table : FPGA I/O / FPGA I/O Settings / Address/CommandDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the address/command pins of thememory interface. The selected I/O standard configures the circuit withinthe I/O buffer to match the industry standard. (Identifier:PHY_DDR4_USER_AC_IO_STD_ENUM )Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_DDR4_USER_AC_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_DDR4_USER_AC_SLEW_RATE_ENUM)6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide210Table : FPGA I/O / FPGA I/O Settings / Memory ClockDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the memory clock pins. Theselected I/O standard configures the circuit within the I/O buffer to matchthe industry standard. (Identifier: PHY_DDR4_USER_CK_IO_STD_ENUM)Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_DDR4_USER_CK_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_DDR4_USER_CK_SLEW_RATE_ENUM)Table : FPGA I/O / FPGA I/O Settings / Data BusDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the data and data clock/strobe pinsof the memory interface. The selected I/O standard option configures thecircuit within the I/O buffer to match the industry standard. (Identifier:PHY_DDR4_USER_DATA_IO_STD_EN UM)Output modeThis parameter allows you to change the output current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_DDR4_USER_DATA_OUT_MODE_ENUM)Input modeThis parameter allows you to change the input termination settings for theselected I/O standard. Perform board simulation with IBIS models todetermine the best settings for your design. (Identifier:PHY_DDR4_USER_DATA_IN_MODE_E NUM)Use recommended initial VrefinSpecifies that the initial Vrefin setting is calculated automatically, to areasonable value based on termination settings. (Identifier:PHY_DDR4_USER_AUTO_STARTING_ VREFIN_EN)Initial VrefinSpecifies the initial value for the reference voltage on the datapins(Vrefin). This value is entered as a percentage of the supply voltagelevel on the I/O pins. The specified value serves as a starting point and maybe overridden by calibration to provide better timing margins. If you chooseto skip Vref calibration (Diagnostics tab), this is the value that is usedas the Vref for the interface. (Identifier:PHY_DDR4_USER_STARTING_VREFI N)Table : FPGA I/O / FPGA I/O Settings / PHY InputsDisplay NameDescriptionPLL reference clock I/O standardSpecifies the I/O standard for the PLL reference clock of the memoryinterface. (Identifier: PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM)RZ Q I/O standardSpecifies the I/O standard for the RZQ pin used in the memory interface.(Identifier: PHY_DDR4_USER_RZQ_IO_STD_ENUM) Intel Stratix 10 EMIF IP DDR4 Parameters: Mem TimingThese parameters should be read from the table in the datasheet associated with thespeed bin of the memory device (not necessarily the frequency at which the interfaceis running).6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide211Table : Mem Timing / Parameters dependent on Speed BinDisplay NameDescriptionSpeed binThe speed grade of the memory device used. This parameter refers to themaximum rate at which the memory device is specified to run. (Identifier:MEM_DDR4_SPEEDBIN_ENUM)tIS (base)tIS (base) refers to the setup time for the Address/Command/Control(A) bus to the rising edge of CK. (Identifier: MEM_DDR4_TIS_PS)tIS (base) AC leveltIS (base) AC level refers to the voltage level which the address/command signal must cross and remain above during the setupmargin window. The signal is considered stable only if it remains abovethis voltage level (for a logic 1) or below this voltage level (for a logic 0) forthe entire setup period. (Identifier: MEM_DDR4_TIS_AC_MV)tIH (base)tIH (base) refers to the hold time for the Address/Command (A) busafter the rising edge of CK. Depending on what AC level the user haschosen for a design, the hold margin can vary (this variance will beautomatically determined when the user chooses the "tIH (base) AClevel"). (Identifier: MEM_DDR4_TIH_PS)tIH (base) DC leveltIH (base) DC level refers to the voltage level which the address/command signal must not cross during the hold window. The signal isconsidered stable only if it remains above this voltage level (for a logic 1) orbelow this voltage level (for a logic 0) for the entire hold period. (Identifier:MEM_DDR4_TIH_DC_MV)TdiVW_tot alTdiVW_total describes the minimum horizontal width of the DQ eyeopening required by the receiver (memory device/DIMM). It is measured inUI (1UI = half the memory clock period). (Identifier:MEM_DDR4_TDIVW_TOTAL_UI)VdiV W_totalVdiVW_total describes the Rx Mask voltage, or the minimum verticalwidth of the DQ eye opening required by the receiver (memory device/DIMM). It is measured in mV. (Identifier: MEM_DDR4_VDIVW_TOTAL)tDQSQtDQSQ describes the latest valid transition of the associated DQ pinsfor a READ. tDQSQ specifically refers to the DQS, DQS# to DQ skew. It isthe length of time between the DQS, DQS# crossing to the last validtransition of the slowest DQ pin in the DQ group associated with that DQSstrobe. (Identifier: MEM_DDR4_TDQSQ_UI)tQHtQH specifies the output hold time for the DQ in relation to DQS,DQS#. It is the length of time between the DQS, DQS# crossing to theearliest invalid transition of the fastest DQ pin in the DQ group associatedwith that DQS strobe. (Identifier: MEM_DDR4_TQH_UI)tDVWpData valid window per device per pin (Identifier: MEM_DDR4_TDVWP_UI)tDQSCKtDQSCK describes the skew between the memory clock (CK) and theinput data strobes (DQS) used for reads. It is the time between therising data strobe edge (DQS, DQS#) relative to the rising CK edge.(Identifier: MEM_DDR4_TDQSCK_PS)tDQSStDQSS describes the skew between the memory clock (CK) and theoutput data strobes used for writes. It is the time between the risingdata strobe edge (DQS, DQS#) relative to the rising CK edge. (Identifier:MEM_DDR4_TDQSS_CYC)tQSHtQSH refers to the differential High Pulse Width, which is measured as apercentage of tCK. It is the time during which the DQS is high for aread. (Identifier: MEM_DDR4_TQSH_CYC)tDSHtDSH specifies the write DQS hold time. This is the time differencebetween the rising CK edge and the falling edge of DQS, measured as apercentage of tCK. (Identifier: MEM_DDR4_TDSH_CYC)tDSStDSS describes the time between the falling edge of DQS to the risingedge of the next CK transition. (Identifier: MEM_DDR4_TDSS_CYC) 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide212Display NameDescriptiontWLStWLS describes the write leveling setup time. It is measured from therising edge of CK to the rising edge of DQS. (Identifier:MEM_DDR4_TWLS_CYC)tWLHtWLH describes the write leveling hold time. It is measured from therising edge of DQS to the rising edge of CK. (Identifier:MEM_DDR4_TWLH_CYC)tINITtINIT describes the time duration of the memory initialization after adevice power-up. After RESET_n is de-asserted, wait for another 500usuntil CKE becomes active. During this time, the DRAM will start internalinitialization; this will be done independently of external clocks. (Identifier:MEM_DDR4_TINIT_US)tMRDThe mode register set command cycle time, tMRD is the minimum timeperiod required between two MRS commands. (Identifier:MEM_DDR4_TMRD_CK_CYC)tRAStRA S describes the activate to precharge duration. A row cannot bedeactivated until the tRAS time has been met. Therefore tRAS determineshow long the memory has to wait after a activate command before aprecharge command can be issued to close the row. (Identifier:MEM_DDR4_TRAS_NS)tRCDtRCD, row command delay, describes the active to read/write time. Itis the amount of delay between the activation of a row through the RAScommand and the access to the data through the CAS command.(Identifier: MEM_DDR4_TRCD_NS)tRPtRP refers to the Precharge (PRE) command period. It describes howlong it takes for the memory to disable access to a row by precharging andbefore it is ready to activate a different row. (Identifier:MEM_DDR4_TRP_NS)tWRtWR refers to the Write Recovery time. It specifies the amount of clockcycles needed to complete a write before a precharge command can beissued. (Identifier: MEM_DDR4_TWR_NS)Table : Mem Timing / Parameters dependent on Speed Bin, OperatingFrequency, and Page SizeDisplay NameDescriptiontRRD_StRRD_S refers to the Activate to Activate Command Period (short). Itis the minimum time interval between two activate commands to thedifferent bank groups. For 3DS devices, this parameter is the same astRRD_S_slr ( tRRD_S within the same logical rank) in the memory datasheet. (Identifier: MEM_DDR4_TRRD_S_CYC)tRRD_LtRRD_L refers to the Activate to Activate Command Period (long). It isthe minimum time interval (measured in memory clock cycles) between twoactivate commands to the same bank group. For 3DS devices, thisparameter is the same as tRRD_L_slr ( tRRD_L within the same logicalrank) in the memory data sheet. (Identifier: MEM_DDR4_TRRD_L_CYC)tRRD_dlrtRRD_dlr refers to the Activate to Activate Command Period toDifferent Logical Ranks. It is the minimum time interval (measured inmemory clock cycles) between two activate commands to different logicalranks within a 3DS DDR4 device. (Identifier: MEM_DDR4_TRRD_DLR_CYC)tFAWtFAW refers to the four activate window time. It describes the period oftime during which only four banks can be active. For 3DS devices, thisparameter is the same as tFAW_slr ( tFAW within the same logical rank)in the memory data sheet. (Identifier: MEM_DDR4_TFAW_NS) 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide213Display NameDescriptiontFAW_dlrtFAW_dlr refers to the four activate window to different logical describes the period of time during which only four banks can be activeacross all logical ranks within a 3DS DDR4 device. (Identifier:MEM_DDR4_TFAW_DLR_CYC)tCCD_S tCCD_S refers to the CAS_n-to-CAS_n delay (short). It is the minimumtime interval between two read/write (CAS) commands to different bankgroups. (Identifier: MEM_DDR4_TCCD_S_CYC)tCCD_LtCCD_L refers to the CAS_n-to-CAS_n delay (long). It is the minimumtime interval between two read/write (CAS) commands to the same bankgroup. (Identifier: MEM_DDR4_TCCD_L_CYC)tWTR_StWTR_S or Write Timing Parameter refers to the Write to Read period fordifferent bank groups. It describes the delay from start of internal writetransaction to internal read command, for accesses to the different bankgroup. The delay is measured from the first rising memory clock edge afterthe last write data is received to the rising memory clock edge when a readcommand is received. (Identifier: MEM_DDR4_TWTR_S_CYC)tWTR_LtWTR_L or Write Timing Parameter refers to the Write to Read period forthe same bank group. It describes the delay from start of internal writetransaction to internal read command, for accesses to the same bankgroup. The delay is measured from the first rising memory clock edge afterthe last write data is received to the rising memory clock edge when a readcommand is received. (Identifier: MEM_DDR4_TWTR_L_CYC)Table : Mem Timing / Parameters dependent on Density and TemperatureDisplay NameDescriptiontRFCtRFC refers to the Refresh Cycle Time. It is the amount of delay after arefresh command before an activate command can be accepted by thememory. This parameter is dependent on the memory density and isnecessary for proper hardware functionality. For 3DS devices, thisparameter is the same as tRFC_slr ( tRFC within the same logical rank)in the memory data sheet. (Identifier: MEM_DDR4_TRFC_NS)tRFC_dlrtRFC_dlr refers to the Refresh Cycle Time to different logical rank. It isthe amount of delay after a refresh command to one logical rank before anactivate command can be accepted by another logical rank within a 3DSDDR4 device. This parameter is dependent on the memory density and isnecessary for proper hardware functionality. (Identifier:MEM_DDR4_TRFC_DLR_NS)tREFItR EFI refers to the average periodic refresh interval. It is the maximumamount of time the memory can tolerate in between each refresh command(Identifier: MEM_DDR4_TREFI_US) Intel Stratix 10 EMIF IP DDR4 Parameters: BoardTable : Board / Intersymbol Interference/CrosstalkDisplay NameDescriptionUse default ISI/crosstalk valuesYou can enable this option to use default intersymbol interference andcrosstalk values for your topology. Note that the default values are notoptimized for your board. For optimal signal integrity, it is recommendedthat you do not enable this parameter, but instead perform I/O 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide214Display NameDescriptionusing IBIS models and Hyperlynx*, and manually enter values based onyour simulation results, instead of using the default values. (Identifier:BOARD_DDR4_USE_DEFAULT_ISI_V ALUES)Address and command ISI/crosstalkThe address and command window reduction due to ISI and crosstalkeffects. The number to be entered is the total loss of margin on both thesetup and hold sides (measured loss on the setup side + measuredloss on the hold side). Refer to the EMIF Simulation Guidance wiki pagefor additional information. (Identifier: BOARD_DDR4_USER_AC_ISI_NS)Read DQS/DQS# ISI/crosstalkThe reduction of the read data window due to ISI and crosstalk effects onthe DQS/DQS# signal when driven by the memory device during a number to be entered is the total loss of margin on the setup andhold sides (measured loss on the setup side + measured loss on thehold side). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_DDR4_USER_RCLK_ISI_NS)Read DQ ISI/crosstalkThe reduction of the read data window due to ISI and crosstalk effects onthe DQ signal when driven by the memory device during a read. Thenumber to be entered is the total loss of margin on the setup and holdside (measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_DDR4_USER_RDATA_ISI_NS)Write DQS/DQS# ISI/crosstalkThe reduction of the write data window due to ISI and crosstalk effects onthe DQS/DQS# signal when driven by the FPGA during a write. The numberto be entered is the total loss of margin on the setup and hold sides(measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_DDR4_USER_WCLK_ISI_NS)Write DQ ISI/crosstalkThe reduction of the write data window due to ISI and crosstalk effects onthe DQ signal when driven by the FPGA during a write. The number to beentered is the total loss of margin on the setup and hold sides(measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_DDR4_USER_WDATA_ISI_NS)Table : Board / Board and Package SkewsDisplay NameDescriptionPackage deskewed with board layout(DQS group)Enable this parameter if you are compensating for package skew on the DQ,DQS, and DM buses in the board layout. Include package skew incalculating the following board skew parameters. (Identifier:BOARD_DDR4_IS_SKEW_WITHIN_DQ S_DESKEWED)Maximum board skew within DQS groupThe largest skew between all DQ and DM pins in a DQS group. This valueaffects the read capture and write margins. (Identifier:BOARD_DDR4_BRD_SKEW_WITHIN_D QS_NS)Maximum system skew within DQSgroupThe largest skew between all DQ and DM pins in a DQS group. Entercombined board and package skew. This value affects the read capture andwrite margins. (Identifier:BOARD_DDR4_PKG_BRD_SKEW_WITH IN_DQS_NS)Package deskewed with board layout(address/command bus)Enable this parameter if you are compensating for package skew on theaddress, command, control, and memory clock buses in the board package skew in calculating the following board skewparameters. (Identifier:BOARD_DDR4_IS_SKEW_WITHIN_AC _DESKEWED)Maximum board skew within address/command busThe largest skew between the address and command signals. (Identifier:BOARD_DDR4_BRD_SKEW_WITHIN_A C_NS)Maximum system skew within address/command busThe largest skew between the address and command signals. Entercombined board and package skew. (Identifier:BOARD_DDR4_PKG_BRD_SKEW_WITH IN_AC_NS) 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide215Display NameDescriptionAverage delay difference between DQSand CKThe average delay difference between the DQS signals and the CK signal,calculated by averaging the longest and smallest DQS trace delay minus theCK trace delay. Positive values represent DQS signals that are longer thanCK signals and negative values represent DQS signals that are shorter thanCK signals. (Identifier: BOARD_DDR4_DQS_TO_CK_SKEW_NS)Maximum delay difference betweenDIMMs/devicesThe largest propagation delay on DQ signals between ranks (applicable onlywhen there is more than one rank).For example: when you configure two ranks using one DIMM there is ashort distance between the ranks for the same DQ pin; when youimplement two ranks using two DIMMs the distance is larger.(Identifier: BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS)Maximum skew between DQS groupsThe largest skew between DQS signals. (Identifier:BOARD_DDR4_SKEW_BETWEEN_DQS_ NS)Average delay difference betweenaddress/command and CKThe average delay difference between the address/command signals andthe CK signal, calculated by averaging the longest and smallest address/command signal trace delay minus the maximum CK trace delay. Positivevalues represent address and command signals that are longer than CKsignals and negative values represent address and command signals thatare shorter than CK signals. (Identifier:BOARD_DDR4_AC_TO_CK_SKEW_NS) Maximum CK delay to DIMM/deviceThe delay of the longest CK trace from the FPGA to any DIMM/device.(Identifier: BOARD_DDR4_MAX_CK_DELAY_NS)Maximum DQS delay to DIMM/deviceThe delay of the longest DQS trace from the FPGA to any DIMM/device(Identifier: BOARD_DDR4_MAX_DQS_DELAY_NS) Intel Stratix 10 EMIF IP DDR4 Parameters: ControllerTable : Controller / Avalon InterfaceDisplay NameDescriptionAvalon InterfaceSelects the Avalon Interface through which the controller interacts with userlogic (Identifier: CTRL_DDR4_AVL_PROTOCOL_ENUM)Table : Controller / Low Power ModeDisplay NameDescriptionEnable Self-Refresh ControlSelect this option to enable the self-refresh control on the controller toplevel. The control signal allows you to place the memory device into self-refresh mode, on a per chip-select basis. (Identifier:CTRL_DDR4_SELF_REFRESH_EN)En able Auto Power-DownEnable this parameter to have the controller automatically place thememory device into power-down mode after a specified number of idlecontroller clock cycles. The idle wait time is configurable. All ranks mustbe idle to enter auto power-down. (Identifier:CTRL_DDR4_AUTO_POWER_DOWN_EN )Auto Power-Down CyclesSpecifies the number of idle controller cycles after which the memorydevice is placed into power-down mode. You can configure the idle waitingtime. The supported range for number of cycles is from 1 to 65534.(Identifier: CTRL_DDR4_AUTO_POWER_DOWN_CYCS)6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide216Table : Controller / EfficiencyDisplay NameDescriptionEnable User Refresh ControlWhen enabled, user logic has complete control and is responsible for issuingadaquate refresh commands to the memory devices, via the MMR feature provides increased control over worst-case read latency andenables you to issue refresh bursts during idle periods. (Identifier:CTRL_DDR4_USER_REFRESH_EN)En able Auto-Precharge ControlSelect this parameter to enable the auto-precharge control on the controllertop level. If you assert the auto-precharge control signal while requesting aread or write burst, you can specify whether the controller should close(auto-precharge) the currently open page at the end of the read or writeburst, potentially making a future access to a different page of the samebank faster. (Identifier: CTRL_DDR4_AUTO_PRECHARGE_EN)Address OrderingControls the mapping between Avalon addresses and memory deviceaddresses. By changing the value of this parameter, you can changethe mappings between the Avalon-MM address and the DRAMaddress. (CS = chip select, CID = chip ID in 3DS/TSV devices, BG = bankgroup address, Bank = bank address, Row = row address, Col = columnaddress) (Identifier: CTRL_DDR4_ADDR_ORDER_ENUM)Enable ReorderingEnable this parameter to allow the controller to perform command and datareordering. Reordering can improve efficiency by reducing busturnaround time and row/bank switching time. Data reordering allowsthe single-port memory controller to change the order of read and writecommands to achieve highest efficiency. Command reordering allows thecontroller to issue bank management commands early based on incomingpatterns, so that the desired row in memory is already open when thecommand reaches the memory interface. For more information, refer to theData Reordering topic in the EMIF Handbook. (Identifier:CTRL_DDR4_REORDER_EN)Starvat ion limit for each commandSpecifies the number of commands that can be served before awaiting command is served. The controller employs a counter to ensurethat all requests are served after a pre-defined interval -- this ensures thatlow priority requests are not ignored, when doing data reordering forefficiency. The valid range for this parameter is from 1 to 63. For moreinformation, refer to the Starvation Control topic in the EMIF Handbook.(Identifier: CTRL_DDR4_STARVE_LIMIT)Enable Command Priority ControlSelect this parameter to enable user-requested command priority control onthe controller top level. This parameter instructs the controller to treat aread or write request as high-priority. The controller attempts to fill high-priority requests sooner, to reduce latency. Connect this interface to theconduit of your logic block that determines when the externalmemory interface IP treats the read or write request as a high-priority command. (Identifier: CTRL_DDR4_USER_PRIORITY_EN)Table : Controller / Configuration, Status and Error HandlingDisplay NameDescriptionEnable Memory-Mapped Configurationand Status Register (MMR) InterfaceEnable this parameter to change or read memory timing parameters,memory address size, mode register settings, controller status, and requestsideband operations. (Identifier: CTRL_DDR4_MMR_EN)Enable Error Detection and CorrectionLogic with ECCEnables error-correction code (ECC) for single-bit error correction anddouble-bit error detection. Your memory interface must have a width of16, 24, 40, or 72 bits to use ECC. ECC is implemented as soft logic.(Identifier: CTRL_DDR4_ECC_EN)Enable Auto Error Correction toExternal MemorySpecifies that the controller automatically schedule and perform a writeback to the external memory when a single-bit error is detected. Regardlessof whether the option is enabled or disabled, the ECC feature alwayscorrects single-bit errors before returning the read data to user logic.(Identifier: CTRL_DDR4_ECC_AUTO_CORRECTION_EN)6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide217Table : Controller / Data Bus Turnaround TimeDisplay NameDescriptionAdditional read-to-write turnaroundtime (same rank)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a read to a write within the same logicalrank. This can help resolve bus contention problems specific to your boardtopology. The value is added to the default which is calculatedautomatically. Use the default setting unless you suspect a problem exists.(Identifier: CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS) Additional write-to-read turnaroundtime (same rank)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a write to a read within the same logicalrank. This can help resolve bus contention problems specific to your boardtopology. The value is added to the default which is calculatedautomatically. Use the default setting unless you suspect a problem exists.(Identifier: CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS) Additional read-to-read turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a read of one logical rank to a read ofanother logical rank. This can resolve bus contention problems specific toyour board topology. The value is added to the default which is calculatedautomatically. Use the default setting unless you suspect a problem exists.(Identifier: CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS) Additional read-to-write turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a read of one logical rank to a write ofanother logical rank. This can help resolve bus contention problemsspecific to your board topology. The value is added to the default which iscalculated automatically. Use the default setting unless you suspect aproblem exists. (Identifier:CTRL_DDR4_RD_TO_WR_DIFF_CHIP _DELTA_CYCS)Additional write-to-write turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a write of one logical rank to a write ofanother logical rank. This can help resolve bus contention problemsspecific to your board topology. The value is added to the default which iscalculated automatically. Use the default setting unless you suspect aproblem exists. (Identifier:CTRL_DDR4_WR_TO_WR_DIFF_CHIP _DELTA_CYCS)Additional write-to-read turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a write of one logical rank to a read ofanother logical rank. This can help resolve bus contention problemsspecific to your board topology. The value is added to the default which iscalculated automatically. Use the default setting unless you suspect aproblem exists. (Identifier:CTRL_DDR4_WR_TO_RD_DIFF_CHIP _DELTA_CYCS) Intel Stratix 10 EMIF IP DDR4 Parameters: DiagnosticsTable : Diagnostics / Simulation OptionsDisplay NameDescriptionCalibration modeSpecifies whether to skip memory interface calibration duringsimulation, or to simulate the full calibration the full calibration process can take hours (or even days),depending on the width and depth of the memory interface. You canachieve much faster simulation times by skipping the calibration process,but that is only expected to work when the memory model is ideal and theinterconnect delays are you enable this parameter, the interface still performs some memoryinitialization before starting normal operations. Abstract PHY is supportedwith skip 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide218Display NameDescription(Identifier: DIAG_DDR4_SIM_CAL_MODE_ENUM)Abstract phy for fast simulationSpecifies that the system use Abstract PHY for simulation. Abstract PHYreplaces the PHY with a model for fast simulation and can reducesimulation time by 2-3 times. Abstract PHY is available for certainprotocols and device families, and only when you select Skip Calibration.(Identifier: DIAG_DDR4_ABSTRACT_PHY)Table : Diagnostics / Calibration Debug OptionsDisplay NameDescriptionQuartus Prime EMIF Debug Toolkit/On-Chip Debug PortSpecifies the connectivity of an Avalon slave interface for use by theQuartus Prime EMIF Debug Toolkit or user core you set this parameter to "Disabled", no debug features are enabled. Ifyou set this parameter to "Export", an Avalon slave interface named"cal_debug" is exported from the IP. To use this interface with the EMIFDebug Toolkit, you must instantiate and connect an EMIF debug interface IPcore to it, or connect it to the cal_debug_out interface of another EMIFcore. If you select "Add EMIF Debug Interface", an EMIF debug interfacecomponent containing a JTAG Avalon Master is connected to the debug port,allowing the core to be accessed by the EMIF Debug one EMIF debug interface should be instantiated per I/O column. Youcan chain additional EMIF or PHYLite cores to the first by enabling the"Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option for all cores in the chain, and selecting "Export"for the "Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port"option on all cores after the first.(Identifier: DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE)Enable Daisy-Chaining for QuartusPrime EMIF Debug Toolkit/On-ChipDebug PortSpecifies that the IP export an Avalon-MM master interface(cal_debug_out) which can connect to the cal_debug interface of otherEMIF cores residing in the same I/O column. This parameter applies onlyif the EMIF Debug Toolkit or On-Chip Debug Port is enabled. Refer tothe Debugging Multiple EMIFs wiki page for more information aboutdebugging multiple EMIFs. (Identifier:DIAG_DDR4_EXPORT_SEQ_AVALON_ MASTER)Interface IDIdentifies interfaces within the I/O column, for use by the EMIF DebugToolkit and the On-Chip Debug Port. Interface IDs should be unique amongEMIF cores within the same I/O column. If the Quartus Prime EMIFDebug Toolkit/On-Chip Debug Port parameter is set to Disabled, theinterface ID is unused. (Identifier: DIAG_DDR4_INTERFACE_ID)Skip address/command levelingcalibrationSpecifies to skip the address/command leveling stage during leveling attempts to center the memory clock edgeagainst CS# by adjusting delay elements inside the PHY, and then applyingthe same delay offset to the rest of the address and command pins.(Identifier: DIAG_DDR4_SKIP_CA_LEVEL)Skip address/command deskewcalibrationSpecifies to skip the address/command deskew calibration stage. Address/command deskew performs per-bit deskew for the address and commandpins. (Identifier: DIAG_DDR4_SKIP_CA_DESKEW)Skip VREF calibrationSpecifies to skip the VREF stage of calibration. Enable this parameter fordebug purposes only; generally, you should include the VREF calibrationstage during normal operation. (Identifier: DIAG_DDR4_SKIP_VREF_CAL)Use Soft NIOS Processor for On-ChipDebugEnables a soft Nios processor as a peripheral component to access the On-Chip Debug Port. Only one interface in a column can activate this option.(Identifier: DIAG_SOFT_NIOS_MODE)6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide219Table : Diagnostics / Example DesignDisplay NameDescriptionNumber of core clocks sharing slaves toinstantiate in the example designSpecifies the number of core clock sharing slaves to instantiate in theexample design. This parameter applies only if you set the "Core clockssharing" parameter in the "General" tab to "Master" or "Slave".(Identifier: DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES)Enable In-System-Sources-and-ProbesEnables In-System-Sources-and-Probes in the example design for commondebug signals, such as calibration status or example traffic generator per-bit status. This parameter must be enabled if you want to do drivermargining. (Identifier: DIAG_DDR4_EX_DESIGN_ISSP_EN)Table : Diagnostics / Traffic GeneratorDisplay NameDescriptionUse configurable Avalon trafficgenerator option allows users to add the new configurable Avalon trafficgenerator to the example design. (Identifier: DIAG_DDR4_USE_TG_AVL_2)Bypass the default traffic patternSpecifies that the controller/interface bypass the traffic generator pattern after reset. If you do not enable this parameter, the trafficgenerator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_DDR4_BYPASS_DEFAULT_PATTERN)Bypass the user-configured traffic stageSpecifies that the controller/interface bypass the user-configured trafficgenerator's pattern after reset. If you do not enable this parameter, thetraffic generator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration can be done by connecting to the traffic generator via theEMIF Debug Toolkit, or by using custom logic connected to the Avalon-MMconfiguration slave port on the traffic generator. Configuration can also besimulated using the example testbench provided in file.(Identifier: DIAG_DDR4_BYPASS_USER_STAGE)Bypass the traffic generator repeated-writes/repeated-reads test patternSpecifies that the controller/interface bypass the traffic generator's repeattest stage. If you do not enable this parameter, every write and read isrepeated several times. (Identifier: DIAG_DDR4_BYPASS_REPEAT_STAGE)Bypass the traffic generator stresspatternSpecifies that the controller/interface bypass the traffic generator's stresspattern stage. (Stress patterns are meant to create worst-case signalintegrity patterns on the data pins.) If you do not enable this parameter,the traffic generator does not assert a pass or fail status until the generatoris configured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_DDR4_BYPASS_STRESS_STAGE)Export Traffic Generator interfaceSpecifies that the IP export an Avalon-MM slave port for configuring theTraffic Generator. This is required only if you are configuring the trafficgenerator through user logic and not through through the EMIF DebugToolkit. (Identifier: DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE)Table : Diagnostics / PerformanceDisplay NameDescriptionEnable Efficiency MonitorAdds an Efficiency Monitor component to the Avalon-MM interface of thememory controller, allowing you to view efficiency statistics of the can access the efficiency statistics using the EMIF Debug Toolkit.(Identifier: DIAG_DDR4_EFFICIENCY_MONITOR)6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide220Table : Diagnostics / MiscellaneousDisplay NameDescriptionUse short Qsys interface namesSpecifies the use of short interface names, for improved usability andconsistency with other Qsys components. If this parameter is disabled, thenames of Qsys interfaces exposed by the IP will include the type anddirection of the interface. Long interface names are supported forbackward-compatibility and will be removed in a future release. (Identifier:SHORT_QSYS_INTERFACE_NAMES) Intel Stratix 10 EMIF IP DDR4 Parameters: Example DesignsTable : Example Designs / Available Example DesignsDisplay NameDescriptionSelect designSpecifies the creation of a full Quartus Prime project, instantiating anexternal memory interface and an example traffic generator, according toyour parameterization. After the design is created, you can specify thetarget device and pin location assignments, run a full compilation, verifytiming closure, and test the interface on your board using the programmingfile created by the Quartus Prime assembler. The 'Generate ExampleDesign' button lets you generate simulation or synthesis file sets.(Identifier: EX_DESIGN_GUI_DDR4_SEL_DESIGN)Table : Example Designs / Example Design FilesDisplay NameDescriptionSimulationSpecifies that the 'Generate Example Design' button create all necessaryfile sets for simulation. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, simulation file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the simulation example design, and file with other corresponding tcl files. You canrun from a command line to generate thesimulation example design. The generated example designs for varioussimulators are stored in the /sim sub-directory. (Identifier:EX_DESIGN_GUI_DDR4_GEN_SIM)S ynthesisSpecifies that the 'Generate Example Design' button create all necessaryfile sets for synthesis. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, synthesis file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the synthesis example design, and script with other corresponding tcl files. You canrun from a command line to generate thesynthesis example design. The generated example design is stored inthe /qii sub-directory. (Identifier: EX_DESIGN_GUI_DDR4_GEN_SYNTH)Table : Example Designs / Generated HDL FormatDisplay NameDescriptionSimulation HDL formatThis option lets you choose the format of HDL in which generatedsimulation files are created. (Identifier:EX_DESIGN_GUI_DDR4_HDL_FORMA T)6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide221Table : Example Designs / Target Development KitDisplay NameDescriptionSelect boardSpecifies that when you select a development kit with a memory module,the generated example design contains all settings and fixed pinassignments to run on the selected board. You must select a developmentkit preset to generate a working example design for the specifieddevelopment kit. Any IP settings not applied directly from a developmentkit preset will not have guaranteed results when testing the developmentkit. To exclude hardware support of the example design, select 'none' fromthe 'Select board' pull down menu. When you apply a development kitpreset, all IP parameters are automatically set appropriately to match theselected preset. If you want to save your current settings, you should do sobefore you apply the preset. You can save your settings under a differentname using File->Save as. (Identifier:EX_DESIGN_GUI_DDR4_TARGET_DE V_KIT) Board Skew EquationsThe following table presents the underlying equations for the board skew Equations for DDR4 Board Skew ParametersTable Skew Parameter EquationsParameterDescription/EquationMa ximum CK delay toDIMM/deviceThe delay of the longest CK trace from the FPGA to any n is the number of memory clock and r is the number rank of DIMM/device. Forexample in dual-rank DIMM implementation, if there are 2 pairs of memory clocks in eachrank DIMM, the maximum CK delay is expressed by the following equation:maxCK1PathDelayrank1,CK2PathDel ayrank1,CK1PathDelayrank2,CK2PathDelayra nk2Maximum DQS delay toDIMM/deviceThe delay of the longest DQS trace from the FPGA to the n is the number of DQS and r isthe number of rank of DIMM/device. For example indual-rank DIMM implementation, if there are 2 DQS in each rank DIMM, the maximum DQSdelay is expressed by the following equation:maxDQS1PathDelayrank1,DQS2PathD elayrank1,DQS1PathDelayrank2,DQS2PathDel ayrank2Average delay differencebetween DQS and CKThe average delay difference between the DQS signals and the CK signal, calculated byaveraging the longest and smallest DQS delay minus the CK delay. Positive valuesrepresent DQS signals that are longer than CK signals and negative values represent DQSsignals that are shorter than CK signals. The Quartus Prime software uses this skew tooptimize the delay of the DQS signals for appropriate setup and hold ,mDQSm_rDelay CKn_rDelay+ minrminn,mDQSm_rDelay CKn_rDelay2Where n is the number of memory clock, m is the number of DQS, and r is the number ofrank of 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide222ParameterDescription/EquationWhe n using discete components, the calculation differs slightly. Find the minimum andmaximum values for (DQS-CK) over all groups and then divide by 2. Calculate the (DQS-CK) for each DQS group, by using the appropriate CLK for that example, in a configuration with 5 x16 components, with each component having twoDQS groups: To find the minimum and maximum, calculate the minimum and maximum of(DQS0 CK0, DQS1 CK0, DQS2 CK1, DQS3 CK1, and so forth) and then divide theresult by Board skew withinDQS groupThe largest skew between all DQ and DM pins in a DQS group. Enter your board skew skew is calculated automatically, based on the memory interface configuration,and added to this value. This value affects the read capture and write minDQgMaximum skew betweenDQS groupsThe largest skew between DQS signals in different DQS groupsMingDQSgMaximum system skewwithin address/commandbusMaxAC MinACThe largest skew between the address and command signals. Enter combined board andpackage skew. In the case of a component, find the maximum address/command andminimum address/command values across all component address delay differencebetween address/commandand CKA value equal to the average of the longest and smallest address/command signal delays,minus the delay of the CK signal. The value can be positive or average delay difference between the address/command and CK is expressed by thefollowing equation: n=nn= 1LongestACPathDelay+ShortestACPathDelay2 CKnPathDelaynwhere n is the number of memory delay differencebetween DIMMs/devicesThe largest propagation delay on DQ signals betweek ranks. For example, in a two-rankconfiguration where you place DIMMs in different slots there is also a propagation delay forDQ signals going to and coming back from the furthest DIMM compared to the nearestDIMM. This parameter is applicable only when there is more than one { maxn,m [(DQn_r path delay DQn_r+1 path delay), (DQSm_r path delay DQSm_r+1 path delay)]}Where n is the number of DQ, m is the number of DQS and r is number of rank of DIMM/device . Pin and Resource PlanningThe following topics provide guidelines on pin placement for external , all external memory interfaces require the following FPGA resources: Interface pins PLL and clock network Other FPGA resources for example, core fabric logic, and on-chip termination(OCT) calibration blocksOnce all the requirements are known for your external memory interface, you canbegin planning your Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Interface PinsAny I/O banks that do not support transceiver operations in Intel Stratix 10 devicessupport external memory interfaces. However, DQS (data strobe or data clock) andDQ (data) pins are listed in the device pin tables and are fixed at specific locations inthe device. You must adhere to these pin locations to optimize routing, minimize skew,and maximize margins. Always check the pin table for the actual locations of the DQSand DQ : Maximum interface width varies from device to device depending on the number ofI/O pins and DQS or DQ groups available. Achievable interface width also depends onthe number of address and command pins that the design requires. To ensureadequate PLL, clock, and device routing resources are available, you should alwaystest fit any IP in the Intel Quartus Prime Prime software before PCB devices do not limit the width of external memory interfaces beyond thefollowing requirements: Maximum possible interface width in any particular device is limited by thenumber of DQS groups available. Sufficient clock networks are available to the interface PLL as required by the IP. Sufficient spare pins exist within the chosen bank or side of the device to includeall other address and command, and clock pin placement requirements. The greater the number of banks, the greater the skew, hence Intel recommendsthat you always generate a test project of your desired configuration and confirmthat it meets Estimating Pin RequirementsYou should use the Intel Quartus Prime software for final pin fitting. However, you canestimate whether you have enough pins for your memory interface using the EMIFDevice Selector on , or perform the following steps:1. Determine how many read/write data pins are associated per data strobe or Calculate the number of other memory interface pins needed, including any otherclocks (write clock or memory system clock), address, command, and RZQ. Referto the External Memory Interface Pin Table to determine necessary Address/Command/Clock pins based on your desired Calculate the total number of I/O banks required to implement the memoryinterface, given that an I/O bank supports up to 48 GPIO should test the proposed pin-outs with the rest of your design in the Intel QuartusPrime software (with the correct I/O standard and OCT connections) before finalizingthe pin-outs. There can be interactions between modules that are illegal in the IntelQuartus Prime software that you might not know about unless you compile the designand use the Intel Quartus Prime Pin LinksExternal Memory Interfaces Support Center6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User DIMM OptionsUnbuffered DIMMs (UDIMMs) require one set of chip-select (CS#), on-die termination(ODT), clock-enable (CKE), and clock pair (CK/CKn) for every physical rank on theDIMM. Registered DIMMs use only one pair of clocks. DDR3 registered DIMMs requirea minimum of two chip-select signals, while DDR4 requires only to the unbuffered DIMMs (UDIMM), registered and load-reduced DIMMs(RDIMMs and LRDIMMs, respectively) use at least two chip-select signals CS#[1:0] inDDR3 and DDR4. Both RDIMMs and LRDIMMs require an additional parity signal foraddress, RAS#, CAS#, and WE# signals. A parity error signal is asserted by the modulewhenever a parity error is expand on the operation of RDIMMs by buffering the DQ/DQS bus. Only oneelectrical load is presented to the controller regardless of the number of ranks,therefore only one clock enable (CKE) and ODT signal are required for LRDIMMs,regardless of the number of physical ranks. Because the number of physical ranksmay exceed the number of physical chip-select signals, DDR3 LRDIMMs provide afeature known as rank multiplication, which aggregates two or four physical ranks intoone larger logical rank. Refer to LRDIMM buffer documentation for details on following table shows UDIMM and RDIMM pin options for and RDIMM Pin Options for DDR3PinsUDIMM Pins (SingleRank)UDIMM Pins(Dual Rank)RDIMM Pins (SingleRank)RDIMM Pins(Dual Rank)Data72 bit DQ[71:0] ={CB[7:0], DQ[63:0]}72 bit DQ[71:0] ={CB[7:0], DQ[63:0]}72 bit DQ[71:0] ={CB[7:0], DQ[63:0]}72 bit DQ[71:0]={CB[7:0], DQ[63:0]}Data MaskDM[8:0]DM[8:0]DM[8:0]DM[8:0]Data StrobeDQS[8:0] andDQS#[8:0]DQS[8:0] andDQS#[8:0]DQS[8:0] andDQS#[8:0]DQS[8:0] andDQS#[8:0]AddressBA[2:0], A[15:0] 2 GB: A[13:0]4 GB: A[14:0]8 GB: A[15:0]BA[2:0], A[15:0] 2 GB: A[13:0]4 GB: A[14:0]8 GB: A[15:0]BA[2:0], A[15:0] 2 GB: A[13:0]4 GB: A[14:0]8 GB: A[15:0]BA[2:0], A[15:0] 2 GB: A[13:0]4 GB: A[14:0]8 GB: A[15:0]ClockCK0/CK0#CK0/CK0#, CK1/CK1#CK0/CK0#CK0/CK0#CommandODT, CS#, CKE, RAS#,CAS#, WE#ODT[1:0], CS#[1:0],CKE[1:0], RAS#, CAS#,WE#ODT, CS#[1:0], CKE,RAS#, CAS#, WE# 2ODT[1:0], CS#[1:0],CKE[1:0], RAS#,CAS#, WE#Parity PAR, ALERTPAR, ALERTOther PinsSA[2:0], SDA, SCL,EVENT#, RESET#SA[2:0], SDA, SCL,EVENT#, RESET#SA[2:0], SDA, SCL,EVENT#, RESET#SA[2:0], SDA, SCL,EVENT#, RESET#The following table shows LRDIMM pin options for Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide225Table Pin Options for DDR3PinsLRDIMMPins (x4,2R)LRDIMM(x4, 4R,RMF=1) 3LRDIMMPins (x4,4R, RMF=2)LRDIMMPins (x4,8R, RMF=2)LRDIMMPins (x4,8R, RMF=4)LRDIMM(x8, 4R,RMF=1) 3LRDIMMPins (x8,4R, RMF=2)Data72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}72 bit DQ[71:0]={CB [7:0],DQ[63:0]}Data Mask DM[8:0]DM[8:0]Data StrobeDQS[17:0]andDQS#[17:0]DQS[17:0]and DQS#[17:0]DQS[17:0]andDQS#[17:0]DQS[17:0 ]andDQS#[17:0]DQS[17:0]andDQS#[17:0]DQS[ 8:0]andDQS#[8:0]DQS[8:0]andDQS#[8:0]Addr essBA[2:0], A[15:0]-2GB:A[13:0] 4GB:A[14:0]8GB:A[15:0] BA[2:0], A[15:0]-2GB:A[13:0] 4GB:A[14:0]8GB:A[15:0]BA[2:0], A[16:0]-4GB:A[14:0] 8GB:A[15:0]16GB:A[16:0]BA[2:0], A[16:0]-4GB:A[14:0] 8GB:A[15:0]16GB:A[16:0] BA[2:0], A[17:0]-16GB:A[15:0] 32GB:A[16:0]64GB:A[17:0] BA[2:0], A[15:0]-2GB:A[13:0] 4GB:A[14:0]8GB:A[15:0]BA[2:0], A[16:0]-4GB:A[14:0] 8GB:A[15:0]16GB:A[16:0]ClockCK0/CK0#CK0/ CK0#CK0/CK0#CK0/CK0#CK0/CK0#CK0/CK0#CK0/ CK0#CommandODT,CS[1:0]#,CKE,RAS#,CAS#, WE#ODT,CS[3:0]#,CKE,RAS#,CAS#, WE#ODT,CS[2:0]#,CKE,RAS#,CAS#, WE#ODT,CS[3:0]#,CKE,RAS#,CAS#, WE#ODT,CS[3:0]#,CKE,RAS#,CAS#, WE#ODT,CS[3:0]#,CKE,RAS#,CAS#, WE#ODT,CS[2:0]#,CKE,RAS#,CAS#, WE#ParityPAR, ALERTPAR, ALERTPAR, ALERTPAR, ALERTPAR, ALERTPAR, ALERTPAR, ALERTOther PinsSA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#Notes to Table:1. DM pins are not used for LRDIMMs that are constructed using 4 S#[2] is treated as A[16] (whose corresponding pins are labeled as CS#[2] or RM[0]) and S#[3] is treated as A[17](whose corresponding pins are labeled as CS#[3] or RM[1]) for certain rank multiplication = rank, RMF = rank multiplication following table shows UDIMM, RDIMM, and LRDIMM pin options for , RDIMM, and LRDIMM Pin Options for DDR4PinsUDIMM Pins(Single Rank)UDIMM Pins(Dual Rank)RDIMM Pins(Single Rank)RDIMM Pins(Dual Rank)LRDIMM Pins(Dual Rank)LRDIMM Pins(Quad Rank)Data72 bitDQ[71:0]={CB[7:0],DQ[63:0]}72 bitDQ[71:0]={CB[7:0],DQ[63:0]}72 bitDQ[71:0]={CB[7:0],DQ[63:0]}72 bitDQ[71:0]={CB[7:0],DQ[63:0]}72 bitDQ[71:0]={CB[7:0],DQ[63:0]}72 bitDQ[71:0]={CB[7:0],DQ[63:0]}Data MaskDM#/DBI#[8:0] (1)DM#/DBI#[8:0](1)DM#/DBI#[8:0](1)DM#/D BI#[8:0](1) 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide226PinsUDIMM Pins(Single Rank)UDIMM Pins(Dual Rank)RDIMM Pins(Single Rank)RDIMM Pins(Dual Rank)LRDIMM Pins(Dual Rank)LRDIMM Pins(Quad Rank)Data Strobex8:DQS[8:0] andDQS#[8:0]x8:DQS[8:0] andDQS#[8:0]x8:DQS[8:0] andDQS#[8:0]x4:DQS[17:0]andDQS#[17:0]x8: DQS[8:0] andDQS#[8:0]x4:DQS[17:0]andDQS#[17:0]x4: DQS[17:0]andDQS#[17:0]x4:DQS[17:0]andDQS #[17:0]AddressBA[1:0],BG[1:0],A[16:0] -4GB:A[14:0]8GB: A[15:0]16GB:A[16:0] (2)BA[1:0],BG[1:0],A[16:0] -8GB: A[14:0]16GB:A[15:0]32GB:A[16:0] (2)BA[1:0],BG[1:0], x8:A[16:0] -4GB:A[14:0]8GB: A[15:0]16GB:A[16:0] (2)32GB:A[17:0] (3)BA[1:0],BG[1:0],x8:A[16:0] x4:A[17:0] -8GB: A[14:0]16GB:A[15:0]32GB:A[16:0] (2)64GB:A[17:0] (3)BA[1:0],BG[1:0],A[17:0] -16GB:A[15:0]32GB:A[16:0] (2)64GB:A[17:0] (3)BA[1:0],BG[1:0],A[17:0] -32GB:A[15:0]64GB:A[16:0] (2)128GB:A[17:0] (3)ClockCK0/CK0#CK0/CK0#,CK1/CK1#CK0/CK0 #CK0/CK0#CK0/CK0#CK0/CK0#CommandODT, CS#,CKE, ACT#,RAS#/A16,CAS#/A15,WE#/A14ODT[1:0],C S#[1:0],CKE[1:0],ACT#, RAS#/A16, CAS#/A15,WE#/A14ODT, CS#,CKE, ACT#,RAS#/A16,CAS#/A15,WE#/A14ODT[1:0],C S#[1:0],CKE, ACT#,RAS#/A16,CAS#/A15,WE#/A14ODT,CS#[1: 0],CKE, ACT#,RAS#/A16,CAS#/A15,WE#/A14ODT,CS#[3: 0],CKE, ACT#,RAS#/A16,CAS#/A15,WE#/A14ParityPAR, ALERT#PAR, ALERT#PAR, ALERT#PAR, ALERT#PAR, ALERT#PAR, ALERT#Other PinsSA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#SA[2:0],SDA, SCL,EVENT#,RESET#Notes to Table:1. DM/DBI pins are available only for DIMMs constructed using x8 or greater This density requires 4Gb x4 or 2Gb x8 DRAM This density requires 8Gb x4 DRAM This table assumes a single slot configuration. The Intel Stratix 10 memory controller can support up to 4 ranks perchannel. A single slot interface may have up to 4 ranks, and a dual slot interface may have up to 2 ranks per slot. Ineither cse, the total number of ranks, calculated as the number of slots multipled by the number of ranks per slot, mustbe less than or equal to Maximum Number of InterfacesThe maximum number of interfaces supported for a given memory protocol varies,depending on the FPGA in otherwise noted, the calculation for the maximum number of interfaces isbased on independent interfaces where the address or command pins are not : You may need to share PLL clock outputs depending on your clock network interface information for Intel Stratix 10, consult the EMIF Device Selector Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide227Timing closure depends on device resource and routing utilization. For moreinformation about timing closure, refer to the Area and Timing OptimizationTechniques chapter in the Intel Quartus Prime Links External Memory Interfaces Support Center Intel Stratix 10 EMIF Architecture: PLL Reference Clock Networks on page 20 External Memory Interface Device Selector Intel Quartus Prime Pro Edition FPGA ResourcesThe Intel FPGA memory interface IP uses FPGA fabric, including registers and theMemory Block to implement the memory OCT calibration block is used if you are using the FPGA OCT feature in thememory interface. The OCT calibration block uses a single pin (RZQ). You can selectany of the available OCT calibration block as you do not need to place this block in thesame bank or device side of your memory interface. The only requirement is that theI/O bank where you place the OCT calibration block uses the same VCCIO voltage asthe memory interface. You can share multiple memory interfaces with the same OCTcalibration block if the VCCIO voltage is the OCTIf the memory interface uses any FPGA OCT calibrated series, parallel, or dynamictermination for any I/O in your design, you need a calibration block for the OCTcircuitry. This calibration block is not required to be within the same bank or side ofthe device as the memory interface RZQ pin in Intel Stratix 10 devices can be used as a general purpose I/O pin whenit is not used to support OCT, provided the signal conforms to the bank PLLWhen using PLL for external memory interfaces, you must consider the followingguidelines:6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide228 For the clock source, use the clock input pin specifically dedicated to the PLL thatyou want to use with your external memory interface. The input and output pinsare only fully compensated when you use the dedicated PLL clock input pin. If theclock source for the PLL is not a dedicated clock input pin for the dedicated PLL,you would need an additional clock network to connect the clock source to the PLLblock. Using additional clock network may increase clock jitter and degrade thetiming margin. Pick a PLL and PLL input clock pin that are located on the same side of the deviceas the memory interface pins. Share the DLL and PLL static clocks for multiple memory interfaces provided thecontrollers are on the same or adjacent side of the device and run at the samememory clock frequency. If your design uses a dedicated PLL to only generate a DLL input reference clock,you must set the PLL mode to No Compensation in the Intel Quartus Primesoftware to minimize the jitter, or the software forces this setting PLL does not generate other output, so it does not need to compensate forany clock Pin Guidelines for Intel Stratix 10 EMIF IPThe Intel Stratix 10 device contains up to three I/O columns that can be used byexternal memory Intel Stratix 10 I/O subsystem resides in the I/Ocolumns. Each column contains multiple I/O banks, each of which consists of four I/Olanes. An I/O lane is a group of twelve I/O I/O column, I/O bank, I/O lane, adjacent I/O bank, and pairing pin for everyphysical I/O pin can be uniquely identified using the Bank Number and Indexwithin I/O Bank values which are defined in each Intel Stratix 10 device pin-outfile. The numeric component of the Bank Number value identifies the I/O column,while the letter represents the I/O bank. The Index within I/O Bank value falls within one of the following ranges: 0 to11, 12 to 23, 24 to 35, or 36 to 47, and represents I/O lanes 1, 2, 3, and 4,respectively. The adjacent I/O bank is defined as the I/O bank with same column number butthe letter is either before or after the respective I/O bank letter in the A-Z system. The pairing pin for an I/O pin is located in the same I/O bank. You can identify thepairing pin by adding one to its Index within I/O Bank number (if it is aneven number), or by subtracting one from its Index within I/O Bank number(if it is an odd number).For example, a physical pin with a Bank Number of 2M and Index within I/OBank of 22, indicates that the pin resides in I/O lane 2, in I/O bank 2M, in column adjacent I/O banks are 2L and 2N. The pairing pin for this physical pin is the pinwith an Index within I/O Bank of 23 and Bank Number of General GuidelinesYou should follow the recommended guidelines when performing pin placement for allexternal memory interface pins targeting Intel Stratix 10 devices, whether you areusing the hard memory controller or your own Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide229If you are using the hard memory controller, you should employ the relative pinlocations defined in the <variation_name>/altera_emif_arch_nd_versionnumber/<synth|sim>/<variation_name>_altera_emif_arch_nd_versionnumber_<unique ID> file, w+ted with your : 1. EMIF IP pin-out requirements for the Intel Stratix 10 Hard Processor Subsystem(HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IPdefines a fixed pin-out in the Intel Quartus Prime IP file (.qip), based on the IPconfiguration. When targeting Intel Stratix 10 HPS, you do not need to makelocation assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the IntelQuartus Prime software. Alternatively, consult the device handbook or the devicepin-out files. For information on how you can customize the HPS EMIF pin-out,refer to Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP with Ping Pong PHY, PHY only, RLDRAMx , QDRx and LPDDR3 are not supported the following general guidelines when placing pins for your Intel Stratix 10external memory interface:1. Ensure that the pins of a single external memory interface reside within a singleI/O An external memory interface can occupy one or more banks in the same I/Ocolumn. When an interface must occupy multiple banks, ensure that those banksare adjacent to one Any pin in the same bank that is not used by an external memory interface isavailable for use as a general purpose I/O of compatible voltage and All address and command pins and their associated clock pins (CK and CK#) mustreside within a single bank. The bank containing the address and command pins isidentified as the address and command To minimize latency, when the interface uses more than two banks, you mustselect the center bank of the interface as the address and command The address and command pins and their associated clock pins in the address andcommand bank must follow a fixed pin-out scheme, as defined in the Intel Stratix10 External Memory Interface Pin Information File, which is available do not have to place every address and command pin manually. If you assignthe location for one address and command pin, the Fitter automatically places theremaining address and command : The pin-out scheme is a hardware requirement that you must follow, andcan vary according to the topology of the memory device. Some schemesrequire three lanes to implement address and command pins, while othersrequire four lanes. To determine which scheme to follow, refer to themessages window during parameterization of your IP, or to the<variation_name>/altera_emif_arch_nd_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nd_<version>_<uniqueID> file after you have generated your Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide2307. An unused I/O lane in the address and command bank can serve to implement adata group, such as a x8 DQS group. The data group must be from the samecontroller as the address and command An I/O lane must not be used by both address and command pins and data Place read data groups according to the DQS grouping in the pin table and PinPlanner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQand CQ# / QK and QK#) must reside at physical pins capable of functioning asDQS/CQ and DQSn/CQn for a specific read data group size. You must place theassociated read data pins (such as DQ and Q), within the same : other device families, there is no need to swap CQ/CQ# pins incertain QDR II and QDR II+ latency requires that the polarity of all QKB/QKB# pins be swapped withrespect to the polarity of the differential buffer inputs on the FPGA toensure correct data capture on port B. All QKB pins on the memorydevice must be connected to the negative pins of the input buffers onthe FPGA side, and all QKB# pins on the memory device must beconnected to the positive pins of the input buffers on the FPGA that the port names at the top-level of the IP already reflect thisswap (that is, mem_qkb is assigned to the negative buffer leg, andmem_qkb_n is assigned to the positive buffer leg).10. You can implement two x4 DQS groups with a single I/O lane. The pin tablespecifies which pins within an I/O lane can be used for the two pairs of DQS andDQS# signals. In addition, for x4 DQS groups you must observe the followingrules:6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide231 There must be an even number of x4 groups in an external memory interface. DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly,DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS groupX and DQS group X+1 must be in the same I/O lane, where X is an evennumber. When placing DQ pins in x4 mode, it is important to stay within a nibble whenswapping pin locations. In other words, you may swap DQ pins within a givenDQS group, but you may not swap pins across DQS groups. The followingtable illustrates an example, where DATA_A and DATA_B are swap groups,meaning that any pin in that index can move within that range of Within LaneDQS x4 Locations11DATA_B[3:0]10DATA_B[3:0]9DQS_ Bn8DQS_Bp7DATA_B[3:0]6DATA_B[3:0]5DQS_An 4DQS_Ap3DATA_A[3:0]2DATA_A[3:0]1DATA_A[3 :0]0DATA_A[3:0]11. You should place the write data groups according to the DQS grouping in the pintable and Pin Planner. Output-only data clocks for QDR II, QDR II+, and QDR II+Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, butmust be placed on a differential pin pair. They must be placed in the same I/Obank as the corresponding DQS : For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced toDK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.12. For protocols and topologies with bidirectional data pins where a write data groupconsists of multiple read data groups, you should place the data groups and theirrespective write and read clock in the same bank to improve I/O do not need to specify the location of every data pin manually. If you assignthe location for the read capture strobe/clock pin pairs, the Fitter willautomatically place the remaining data Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/Opin and another in the pairing pin for that I/O pin. It is recommended though notrequired that you follow the same rule for DBI pins, so that at a later date youhave the freedom to repurpose the pin as Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide232Note: 1. x4 mode does not support DM/DBI, or Intel Stratix 10 EMIF IP for If you are using an Intel Stratix 10 EMIF IP-based RLDRAM 3 external memoryinterface, you should ensure that all the pins in a DQS group (that is, DQ, DM, DK,and QK) are placed in the same I/O bank. This requirement facilitates timingclosure and is necessary for successful compilation of your Interfaces in the Same I/O ColumnTo place multiple interfaces in the same I/O column, you must ensure that the globalreset signals (global_reset_n) for each individual interface all come from the sameinput pin or Banks Selection For each memory interface, select consecutive I/O banks. (That is, select banksthat contain the same column number and letter before or after the respective I/Obank letter.) A memory interface can only span across I/O banks in the same I/O column. The number of I/O banks that you require depends on the memory interfacewidth. In some device packages, the number of I/O pins in some LVDS I/O banks is lessthat 48 Pins Location All address/command pins for a controller must be in a single I/O bank. If your interface uses multiple I/O banks, the address/command pins must use themiddle bank. If the number of banks used by the interface is even, any of the twomiddle I/O banks can be used for address/command pins. Address/command pins and data pins cannot share an I/O lane but can share anI/O bank. The address/command pin locations for the soft and hard memory controllers arepredefined. In the External Memory Interface Pin Information for Devicesspreadsheet, each index in the "Index within I/O bank" column denotes adedicated address/command pin function for a given protocol. The index numberof the pin specifies to which I/O lane the pin belongs: I/O lane 0 Pins with index 0 to 11 I/O lane 1 Pins with index 12 to 23 I/O lane 2 Pins with index 24 to 35 I/O lane 3 Pins with index 36 to 47 For memory topologies and protocols that require only three I/O lanes for theaddress/command pins, use I/O lanes 0, 1, and 2. Unused address/command pins in an I/O lane can be used as general-purpose Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide233CK Pins AssignmentAssign the clock pin (CK pin) according to the number of I/O banks in an interface: If the number of I/O banks is odd, assign one CK pin to the middle I/O bank. If the number of I/O banks is even, assign the CK pin to either of the middle twoI/O the Fitter can automatically select the required I/O banks, Intel recommendsthat you make the selection manually to reduce the pre-fit run Reference Clock Pin PlacementPlace the PLL reference clock pin in the address/command bank. Other I/O banks maynot have free pins that you can use as the PLL reference clock pin: If you are sharing the PLL reference clock pin between several interfaces, the I/Obanks must be adjacent. (That is, the banks must contain the same columnnumber and letter before or after the respective I/O bank letter.)The Intel Stratix 10 external memory interface IP does not support PLL Pin PlacementYou may place the RZQ pin in any I/O bank in an I/O column with the correct VCCIO andVCCPT for the memory interface I/O standard in use. However, the recommendedlocation is in the address/command I/O bank, for greater flexibility during debug if anarrower interface project is required for and DQS Pins AssignmentIntel recommends that you assign the DQS pins to the remaining I/O lanes in the I/Obanks as required: Constrain the DQ and DQS signals of the same DQS group to the same I/O lane. You cannot constrain DQ signals from two different DQS groups to the same you do not specify the DQS pins assignment, the Fitter selects the DQS an I/O Bank Across Multiple InterfacesIf you are sharing an I/O bank across multiple external memory interfaces, followthese guidelines: The interfaces must use the same protocol, voltage, data rate, frequency, and PLLreference clock. You cannot use an I/O bank as the address/command bank for more than oneinterface. The memory controller and sequencer cannot be shared. You cannot share an I/O lane. There is only one DQS input per I/O lane, and anI/O lane can connect to only one memory Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Command and Address SignalsCommand and address signals in SDRAM devices are clocked into the memory deviceusing the CK or CK# signal. These pins operate at single data rate (SDR) using onlyone clock edge. The number of address pins depends on the SDRAM device address pins are multiplexed, so two clock cycles are required to send the row,column, and bank DDR3, the CS#, RAS#, CAS#, WE#, CKE, and ODT pins are SDRAM command andcontrol pins. For DDR3 SDRAM, certain topologies such as RDIMM and LRDIMM includeRESET#, PAR ( LVCMOS I/O standard), and ALERT# (SSTL-15 I/O standard).Although DDR4 operates in fundamentally the same way as other SDRAM, there areno longer dedicated pins for RAS#, CAS#, and WE#, as those are now shared withhigher-order address pins. DDR4 still has CS#, CKE, ODT, and RESET# pins, similar toDDR3. DDR4 introduces some additional pins, including the ACT# (activate) pin andBG (bank group) pins. Depending on the memory format and the functions enabled,the following pins might also exist in DDR4: PAR (address command parity) pin andthe ALERT# Clock SignalsDDR3 and DDR4 SDRAM devices use CK and CK# signals to clock the address andcommand signals into the memory. Furthermore, the memory uses these clock signalsto generate the DQS signal during a read through the DLL inside the memory. TheSDRAM data sheet specifies the following timings: tDQSCK is the skew between the CK or CK# signals and the SDRAM-generated DQSsignal tDSH is the DQS falling edge from CK rising edge hold time tDSS is the DQS falling edge from CK rising edge setup time tDQSS is the positive DQS latching edge to CK rising edgeSDRAM have a write requirement (tDQSS) that states the positive edge of the DQSsignal on writes must be within 25% ( 90 ) of the positive edge of the SDRAMclock input. Therefore, you should generate the CK and CK# signals using the DDRregisters in the IOE to match with the DQS signal and reduce any variations acrossprocess, voltage, and temperature. The positive edge of the SDRAM clock, CK, isaligned with the DQS write to satisfy SDRAM can use a daisy-chained control address command (CAC) topology, inwhich the memory clock must arrive at each chip at a different time. To compensatefor the flight-time skew between devices when using the CAC topology, you shouldemploy write Data, Data Strobes, DM/DBI, and Optional ECC SignalsDDR3 and DDR4 SDRAM use bidirectional differential data strobes. Differential DQSoperation enables improved system timing due to reduced crosstalk and lesssimultaneous switching noise on the strobe output drivers. The DQ pins are pins in DDR3 and DDR4 SDRAM interfaces can operate in either 4 or 8 modeDQS groups, depending on your chosen memory device or DIMM, regardless ofinterface width. The 4 and 8 configurations use one pair of bidirectional data strobe6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide235signals, DQS and DQSn, to capture input data. However, two pairs of data strobes,UDQS and UDQS# (upper byte) and LDQS and LDQS# (lower byte), are required bythe 16 configuration devices. A group of DQ pins must remain associated with itsrespective DQS and DQSn DQ signals are edge-aligned with the DQS signal during a read from the memoryand are center-aligned with the DQS signal during a write to the memory. Thememory controller shifts the DQ signals by 90 degrees during a write operation tocenter align the DQ and DQS signals. The PHY IP delays the DQS signal during a read,so that the DQ and DQS signals are center aligned at the capture register. Inteldevices use a phase-locked loop (PLL) to center-align the DQS signal with respect tothe DQ signals during writes and Intel devices use dedicated DQS phase-shift circuitryto shift the incoming DQS signal during reads. The following figure shows an examplewhere the DQS signal is shifted by 90 degrees for a read from the DDR3 DQ and DQS Relationship During a DDR3 SDRAM Read in Burst-of-Four ModeDQS at DQIOE registersDQS at FPGA PinDQ at DQIOE registersDQ atFPGA PinDQS phase shiftPreamblePostambleThe following figure shows an example of the relationship between the data and datastrobe during a burst-of-four and DQS Relationship During a DDR3 SDRAM Write in Burst-of-Four ModeDQS atFPGA PinDQ atFPGA PinThe memory device's setup (tDS) and hold times (tDH) for the DQ and DM pins duringwrites are relative to the edges of DQS write signals and not the CK or CK# and hold requirements are not necessarily balanced in DDR3 DQS signal is generated on the positive edge of the system clock to meet thetDQSS requirement. DQ and DM signals use a clock shifted 90 degrees from thesystem clock, so that the DQS edges are centered on the DQ or DM signals when theyarrive at the DDR3 SDRAM. The DQS, DQ, and DM board trace lengths need to betightly matched (within 20 ps).The SDRAM uses the DM pins during a write operation. Driving the DM pins low showsthat the write is valid. The memory masks the DQ signals if the DM pins are drivenhigh. To generate the DM signal, Intel recommends that you use the spare DQ pinwithin the same DQS group as the respective data, to minimize Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide236The DM signal's timing requirements at the SDRAM input are identical to those for DQdata. The DDR registers, clocked by the 90 degree shifted clock, create the supports DM similarly to other SDRAM, except that in DDR4 DM is active LOWand bidirectional, because it supports Data Bus Inversion (DBI) through the same is multiplexed with DBI by a Mode Register setting whereby only one function canbe enabled at a time. DBI is an input/output identifying whether to store/output thetrue or inverted data. When enabled, if DBI is LOW, during a write operation the datais inverted and stored inside the DDR4 SDRAM; during a read operation, the data isinverted and output. The data is not inverted if DBI is HIGH. For Intel Stratix 10interfaces, the DM (for DDR3) pins in each DQS group must be paired with a DQ pinfor proper operation. DM/DBI (for DDR4) do not need to be paired with a DQ SDRAM modules support error correction coding (ECC) to allow the controller todetect and automatically correct error in data transmission. The 72-bit SDRAMmodules contain eight extra data pins in addition to 64 data pins. The eight extra ECCpins should be connected to a single DQS or DQ group on the Resource Sharing Guidelines (Multiple Interfaces)In Intel Cyclone 10Intel Stratix 10 external memory interface IP, different externalmemory interfaces can share PLL reference clock pins, core clock networks, I/O banks,and hard Nios processors. Each I/O bank has DLL and PLL resources, therefore thesedo not need to be shared. The Intel Quartus Prime Fitter automatically merges DLLand PLL resources when a bank is shared by different external memory interfaces, andduplicates them for a multi-I/O-bank external memory Reference Clock PinTo conserve pin usage and enable core clock network and I/O bank sharing, you canshare a PLL reference clock pin between multiple external memory interfaces; theinterfaces must be of the same protocol, rate, and frequency. Sharing of a PLLreference clock pin also implies sharing of the reference clock the following guidelines for sharing the PLL reference clock share a PLL reference clock pin, connect the same signal to the pll_ref_clkport of multiple external memory interfaces in the RTL Place related external memory interfaces in the same I/O Place related external memory interfaces in adjacent I/O banks. If you leave anunused I/O bank between the I/O banks used by the external memory interfaces,that I/O bank cannot be used by any other external memory interface with adifferent PLL reference clock : You can place the pll_ref_clk pin in the address and command I/O bank or in adata I/O bank, there is no impact on timing. However, for greatest flexibility duringdebug (such as when creating designs with narrower interfaces), the recommendedplacement is in the address and command I/O Clock NetworkTo access all external memory interfaces synchronously and to reduce global clocknetwork usage, you may share the same core clock network with other externalmemory Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide237Observe the following guidelines for sharing the core clock share a core clock network, connect the clks_sharing_master_out of themaster to the clks_sharing_slave_in of all slaves in the RTL Place related external memory interfaces in the same I/O Related external memory interface must have the same rate, memory clockfrequency, and PLL reference BankTo reduce I/O bank utilization, you may share an I/O Bank with other externalmemory the following guidelines for sharing an I/O Bank:1. Related external memory interfaces must have the same protocol, rate, memoryclock frequency, and PLL reference You cannot use a given I/O bank as the address and command bank for more thanone external memory You cannot share an I/O lane between external memory interfaces, but an unusedpin can serve as a general purpose I/O pin, of compatible voltage and Nios ProcessorAll external memory interfaces residing in the same I/O column will share the samehard Nios processor. The shared hard Nios processor calibrates the external memoryinterfaces DDR4 Board Design GuidelinesThe following topics provide guidelines for improving the signal integrity of yoursystem and for successfully implementing a DDR4 SDRAM interface on your following areas are discussed: comparison of various types of termination schemes, and their effects on thesignal quality on the receiver proper drive strength setting on the FPGA to optimize the signal integrity at thereceiver effects of different loading types, such as components versus DIMM configuration,on signal qualityIt is important to understand the trade-offs between different types of terminationschemes, the effects of output drive strengths, and different loading types, so thatyou can swiftly navigate through the multiple combinations and choose the bestpossible settings for your following key factors affect signal quality at the receiver: Leveling and dynamic ODT Proper use of termination Layout guidelines6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide238As memory interface performance increases, board designers must pay closerattention to the quality of the signal seen at the receiver because poorly transmittedsignals can dramatically reduce the overall data-valid margin at the receiver. Thefollowing figure shows the differences between an ideal and real signal seen by and Real Signal at the ReceiverIdealRealVoltageVoltageVIHVIHVIL VILTimeTimeRelated Terminations for DDR3 and DDR4 with Intel Stratix 10 DevicesThe following topics describe considerations specific to DDR3 and DDR4 externalmemory interface protocols on Intel Stratix 10 Dynamic On-Chip Termination (OCT) in Intel Stratix 10 DevicesDepending upon the Rs (series) and Rt (parallel) OCT values that you want, youshould choose appropriate values for the RZQ resistor and connect this resistor to theRZQ pin of the FPGA. Select a 240-ohm reference resistor to ground to implement Rs OCT values of 34-ohm, 40-ohm, 48-ohm, 60-ohm, and 80-ohm, and Rt OCT resistance values of 20-ohm, 30-ohm, 34-ohm, 40-ohm, 60-ohm, 80-ohm, 120-ohm and 240 ohm. Select a 100-ohm reference resistor to ground to implement Rs OCT values of 25-ohm and 50-ohm, and an RT OCT resistance of the FPGA I/O tab of the parameter editor to determine the I/O standards andtermination values supported for data, address and command, and memory LinksChoosing Terminations on Intel Stratix 10 Devices on page Dynamic On-Die Termination (ODT) in DDR4In DDR4, in addition to the Rtt_nom and Rtt_wr values, which are applied during readand write respectively, a third option called Rtt_park is available. When Rtt_park isenabled, a selected termination value is set in the DRAM when ODT is driven Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide239Rtt_nom and Rtt_wr work the same as in DDR3, which is described in Dynamic ODTfor to the DDR4 JEDEC specification or your memory vendor data sheet for detailsabout available termination values and functional description for dynamic ODT inDDR4 DDR4 LRDIMM, if SPD byte 152 calls for different values of Rtt_Park to be usedfor package ranks 0 and 1 versus package ranks 2 and 3, set the value to the larger ofthe two impedance Choosing Terminations on Intel Stratix 10 DevicesTo determine optimal on-chip termination (OCT) and on-die termination (ODT) valuesfor best signal integrity, you should simulate your memory interface in HyperLynx or asimilar the optimal OCT and ODT termination values as determined by simulation are notavailable in the list of available values in the parameter editor, select the closestavailable termination values for OCT and information about available ODT choices, refer to your memory vendor data LinksDynamic On-Chip Termination (OCT) in Intel Stratix 10 Devices on page On-Chip Termination Recommendations for Intel Stratix 10 Devices Output mode (drive strength) for Address/Command/Clock and Data Signals:Depending upon the I/O standard that you have selected, you would have a rangeof selections expressed in terms of ohms or miliamps. A value of 34 to 40 ohms or12 mA is a good starting point for output mode drive strength. Input mode (parallel termination) for Data and Data Strobe signals: A value of 40or 60 ohms is a good starting point for FPGA side input Channel Signal Integrity MeasurementAs external memory interface data rates increase, so does the importance of properchannel signal integrity measuring the actual channel loss during thelayout process and including that data in your parameterization, a realistic assessmentof margins is Importance of Accurate Channel Signal Integrity InformationDefault values for channel loss (or eye reductoin) can be used when calculating timingmargins, however those default values may not accurately reflect the channel loss inyour the channel loss in your system is different than the default values, thecalculated timing margins will vary your actual channel loss is greater than the default channel loss, and if you rely ondefault values, the available timing margins for the entire system will be lower thanthe values calculated during compilation. By relying on default values that do not6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide240accurately reflect your system, you may be lead to believe that you have good timingmargin, while in reality, your design may require changes to achieve good channelsignal Understanding Channel Signal Integrity MeasurementTo measure channel signal integrity you need to measure the channel loss for a particular signal or signal trace, channel loss is defined as loss of the eyewidth at +/- VIH(ac and dc) +/- VIL(ac and dc). VIH/VIL above or below VREF is used toalign with various requirements of the timing model for memory example below shows a reference eye diagram where the channel loss on thesetup- or leading-side of the eye is equal to the channel loss on the hold- or lagging-side of the eye; howevever, it does not necessarily have to be that way. BecauseIntel's calibrating PHY will calibrate to the center of the read and write eye, the BoardSettings tab has parameters for the total extra channel loss for Write DQ and ReadDQ. For address and command signals which are not-calibrated, the Board Settingstab allows you to enter setup- and hold-side channel losses that are not equal,allowing the Intel Quartus Prime software to place the clock statically within the centerof the address and command Setup and Hold-side How to Enter Calculated Channel Signal Integrity ValuesYou should enter calculated channel loss values in the Channel Signal Integritysection of the Board (or Board Timing) tab of the parameter Intel Stratix 10 external memory interfaces, the default channel loss displayed inthe parameter editor is based on the selected configuration (different values for singlerank versus dual rank), and on internal Intel reference boards. You should replace thedefault value with the value that you Guidelines for Calculating DDR4 Channel Signal Integrity6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide241Address and Command ISI and CrosstalkSimulate the address/command and control signals and capture eye at the DRAM pins,using the memory clock as the trgger for the memory interface's address/commandand control signals. Measure the setup and hold channel losses at the voltagethresholds mentioned in the memory vendor's data and command channel loss = Measured loss on the setup side + measuredloss on the hold = VDD/2 = mV for address/command for should select the VIH and VIL voltage levels appropriately for the DDR4 memorydevice that you are using. Check with your memory vendor for the correct voltagelevels, as the levels may vary for different speed grades of following figure illustrates a DDR4-1200 example, where VIH(AC)/ VIL(AC) is +/- 100mV and VIH(DC)/ VIL(DC) is +/- 75 the VIH(AC), VIL(AC), VIH(DC), and VIL(DC)for the speed grade of DDR4 memorydevice from the memory vendor's data DQ ISI and CrosstalkSimulate the write DQ signals and capture eye at the DRAM pins, using DQ Strobe(DQS) as a trigger for the DQ signals of the memory interface simulation. Measure thesetup and hold channel lossses at the VIH and VIL mentioned in the memory vendor'sdata sheetWrite Channel Loss = Measured Loss on the Setup side + Measured Loss on the Channel Loss = UI (Eye opening at VIH or VIL).VREF = Voltage level where the eye opening is Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide242VIH = VREF + ( x VdiVW).VIL = VREF - ( x VdiVW).Where VdiVW varies by frequency of operation; you can find the VdiVW value in yourmemory vendor's data DQ ISI and CrosstalkSimulate read DQ signals and capture eye at the FPGA die. Do not measure at the pin,because you might see unwanted reflections that could create a false representation ofthe eye opening at the input buffer of the FPGA. Use DQ Strobe (DQS) as a trigger forthe DQ signals of your memory interface simulation. Measure the eye opening at +/-70 mV (VIH/VIL) with respect to Channel Loss = (UI) - (Eye opening at +/- 70 mV with respect to VREF.)UI = Unit interval. For example, if you are running your interface at 800 Mhz, theeffective data is 1600 Mbps, giving a unit interval of 1/1600 = 625 = Voltage level where the eye opening is Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide243Figure DQS ISI and CrosstalkSimulate write and read DQS and capture eye. Measure the uncertainty at = Voltage level where the eye opening is the Layout ApproachFor all practical purposes, you can regard the Timing Analyzer report on your memoryinterface as definitive for a given set of memory and board timing will find timing under Report DDR in the Timing Analyzer and on the TimingAnalysis tab in the parameter Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide244The following flowchart illustrates the recommended process to follow during theboard design phase, to determine timing margin and make iterative improvements toyour LayoutCalculate Setupand Hold DeratingCalculate ChannelSignal IntegrityCalculate BoardSkewsFind MemoryTiming ParametersGenerate an IP Core that Accurately Represents Your Memory Subsystem, Including pin-out and Accurate Parameters in the Parameter Editor s Board Settings TabRun Quartus Prime Compilation with the Generated IP CoreAny Non-Core TimingViolations in the ReportDDR Panel?yesnoDoneAdjust Layout to Improve: Trace Length Mis-Match Signal Reflections (ISI) Cross Talk Memory Speed GradeBoard SkewFor information on calculating board skew parameters, refer to Board Skew Equations,in this Board Skew Parameter Tool is an interactive tool that can help you calculate boardskew parameters if you know the absolute delay values for all the memory Timing ParametersFor information on the memory timing parameters to be entered into the parametereditor, refer to the datasheet for your external memory LinksBoard Skew Parameter Design Layout GuidelinesThe general layout guidelines in the following topic apply to DDR3 and DDR4 guidelines will help you plan your board layout, but are not meant as strict rulesthat must be adhered to. Intel recommends that you perform your own board-levelsimulations to ensure that the layout you choose for your board allows you to achieveyour desired Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide245For more information about how the memory manufacturers route these address andcontrol signals on their DIMMs, refer to the Cadence PCB browser from the Cadencewebsite, at The various JEDEC example DIMM layouts are availablefrom the JEDEC website, at assistance in calculating board skew parameters, refer to the board skewcalculator tool, which is available at the Intel : 1. The following layout guidelines include several +/- length based rules. Theselength based guidelines are for first order timing approximations if you cannotsimulate the actual delay characteristic of the interface. They do not include anymargin for To ensure reliable timing closure to and from the periphery of the device, signalsto and from the periphery should be registered before any further logic recommends that you get accurate time base skew numbers for your designwhen you simulate the specific Links Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits) on page195 Board Skew Parameter Tool General Layout GuidelinesThe following table lists general board design layout guidelines. These guidelines areIntel recommendations, and should not be considered as hard requirements. Youshould perform signal integrity simulation on all the traces to verify the signal integrityof the interface. You should extract the slew rate and propagation delay information,enter it into the IP and compile the design to ensure that timing requirements Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide246Table Layout GuidelinesParameterGuidelinesImpedance All unused via pads must be removed, because they cause unwantedcapacitance. Trace impedance plays an important role in the signal integrity. You mustperform board level simulation to determine the best characteristic impedancefor your PCB. For example, it is possible that for multi rank systems 40 ohmscould yield better results than a traditional 50 ohm characteristic Parameter Use uF in 0402 size to minimize inductance Make VTT voltage decoupling close to termination resistors Connect decoupling caps between VTT and ground Use a uF cap for every other VTT pin and uF cap for every VDD andVDDQ pin Verify the capacitive decoupling using the Intel Power Distribution NetworkDesign ToolPower Route GND and VCC as planes Route VCCIO for memories in a single split plane with at least a 20-mil( inches, or mm) gap of separation Route VTT as islands or 250-mil ( ) power traces Route oscillators and PLL power as islands or 100-mil ( ) power tracesGeneral RoutingAll specified delay matching requirements include PCB trace delays, different layerpropagation velocity variance, and crosstalk. To minimize PCB layer propogationvariance, Intel recommends that signals from the same net group always berouted on the same layer. Use 45 angles (not 90 corners) Avoid T-Junctions for critical nets or clocks Avoid T-junctions greater than 250 mils ( mm) Disallow signals across split planes Restrict routing other signals close to system reset signals Avoid routing memory signals closer than inch ( mm) to PCI orsystem clocksRelated LinksPower Distribution Layout GuidelinesThe following table lists layout otherwise specified, the guidelines in the following table apply to the followingtopologies: DIMM UDIMM topology DIMM RDIMM topology DIMM LRDIMM topology Not all versions of the Intel Quartus Prime software support LRDIMM. Discrete components laid out in UDIMM topology Discrete components laid out in RDIMM topologyThese guidelines are recommendations, and should not be considered as hardrequirements. You should perform signal integrity simulation on all the traces to verifythe signal integrity of the Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide247For supported frequencies and topologies, refer to the External Memory Interface SpecEstimator frequencies greater than 800 MHz, when you are calculating the delay associatedwith a trace, you must take the FPGA package delays into Guidelines (1)ParameterGuidelinesDecoupling Parameter Make VTT voltage decoupling close to the components and pull-up resistors. Connect decoupling caps between VTT and VDD using a F cap for everyother VTT pin. Use a uF cap and uF cap for every VDDQ Trace Length Even though there are no hard requirements for minimum trace length, youneed to simulate the trace to ensure the signal integrity. Shorter routes resultin better timing. For DIMM topology only: Maximum trace length for all signals from FPGA to the first DIMM slot is Maximum trace length for all signals from DIMM slot to DIMM slot is For discrete components only: Maximum trace length for address, command, control, and clock from FPGA tothe first component must not be more than 7 inches. Maximum trace length for DQ, DQS, DQS#, and DM from FPGA to the firstcomponent is 5 Routing Route over appropriate VCC and GND planes. Keep signal routing layers close to GND and power Guidelines Avoid routing two signal layers next to each other. Always make sure that thesignals related to memory interface are routed between appropriate GND orpower layers. For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) for these traces. (Where H is the vertical distance to the closest returnpath for that particular trace.) For Address/Command/Control traces: Maintain at least 3H spacing betweenthe edges (air-gap) these traces. (Where H is the vertical distance to theclosest return path for that particular trace.) For Clock traces: Maintain at least 5H spacing between two clock pair or aclock pair and any other memory interface trace. (Where H is the verticaldistance to the closest return path for that particular trace.)Clock Routing Route clocks on inner layers with outer-layer run lengths held to under 500mils ( mm). Route clock signals in a daisy chain topology from the first SDRAM to the lastSDRAM. The maximum length of the first SDRAM to the last SDRAM must notexceed tCK for DDR3 and tCK for DDR4. For different DIMMconfigurations, check the appropriate JEDEC specification. These signals should maintain the following spacings: Clocks should maintain a length-matching between clock pairs of 5 ps. Clocks should maintain a length-matching between positive (p) and negative(n) signals of 2 ps, routed in parallel. Space between different pairs should be at least two times the trace width ofthe differential pair to minimize loss and maximize interconnect density. To avoid mismatched transmission line to via, Intel recommends that you useGround Signal Signal Ground (GSSG) topology for your clock pattern GND|CLKP|CKLN|GND. Route all addresses and commands to match the clock signals to within 20 psto each discrete memory component. Refer to the following 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide248ParameterGuidelinesAddress and Command Routing Route address and command signals in a daisy chain topology from the firstSDRAM to the last SDRAM. The maximum length of the first SDRAM to the lastSDRAM must not be more than tCK for DDR3 and tCK for DDR4. Fordifferent DIMM configurations, check the appropriate JEDEC specifications. UDIMMs are more susceptible to cross-talk and are generally noisier thanbuffered DIMMs. Therefore, route address and command signals of UDIMMs ona different layer than data signals (DQ) and data mask signals (DM) and withgreater spacing. Do not route differential clock (CK) and clock enable (CKE) signals close toaddress signals. Route all addresses and commands to match the clock signals to within 20 psto each discrete memory component. Refer to the following , DM, and DQS Routing Rules All the trace length matching requirements are from the FPGA package ball tothe SDRAM package ball, which means you must consider trace mismatchingon different DIMM raw cards. Match in length all DQ, DQS, and DM signals within a given byte-lane groupwith a maximum deviation of 10 ps. Ensure to route all DQ, DQS, and DM signals within a given byte-lane group onthe same layer to avoid layer to layer transmission velocity differences, whichotherwise increase the skew within the group. Do not count on FPGAs to deskew for more than 20 ps of DQ group skew. Theskew algorithm only removes the following possible uncertainties: Minimum and maximum die IOE skew or delay mismatch Minimum and maximum device package skew or mismatch Board delay mismatch of 20 ps Memory component DQ skew mismatch Increasing any of these four parameters runs the risk of the deskewalgorithm limiting, failing to correct for the total observed system skew. Ifthe algorithm cannot compensate without limiting the correction, timinganalysis shows reduced margins. For memory interfaces with leveling, the timing between the DQS and clocksignals on each device calibrates dynamically to meet tDQSS. To make surethe skew is not too large for the leveling circuit s capability, follow these rules: Propagation delay of clock signal must not be shorter than propagationdelay of DQS signal at every device: (CKi) DQSi > 0; 0 < i < number ofcomponents 1 . For DIMMs, ensure that the CK trace is longer than thelongest DQS trace at the DIMM connector. Total skew of CLK and DQS signal between groups is less than one clockcycle: (CKi+ DQSi) max (CKi+ DQSi) min < 1 tCK(If you are using aDIMM topology, your delay and skew must take into consideration valuesfor the actual DIMM.) 6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide249ParameterGuidelinesSpacing Guidelines Avoid routing two signal layers next to each other. Always ensure that thesignals related to the memory interface are routed between appropriate GNDor power layers. For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) of these traces, where H is the vertical distance to the closest return pathfor that particular trace. For Address/Command/Control traces: Maintain at least 3H spacing betweenthe edges (air-gap) of these traces, where H is the vertical distance to theclosest return path for that particular trace. For Clock traces: Maintain at least 5H spacing between two clock pairs or aclock pair and any other memory interface trace, where H is the verticaldistance to the closest return path for that particular Quartus Prime Software Settingsfor Board Layout To perform timing analyses on board and I/O buffers, use a third-partysimulation tool to simulate all timing information such as skew, ISI, crosstalk,and type the simulation result into the Board Settings tab in the parametereditor. Do not use advanced I/O timing model (AIOT) or board trace model unless youdo not have access to any third party tool. AIOT provides reasonable accuracybut tools like HyperLynx provide better to Table:1. For point-to-point and DIMM interface designs, refer to the Micron website, Links Package Deskew on page 198 External Memory Interface Spec Estimator Length Matching RulesThe following topics provide guidance on length matching for different types of all addresses and commands to match the clock signals to within 20 ps toeach discrete memory component. The following figure shows the component routingguidelines for address and command Component Address and Command Routing GuidelinesIf using discrete components:x = y 20 psx + x1 = y + y1 20 psx + x1 + x2 = y + y1 + y2 20 psaddress andcommandclockxyx1y1x2y2x3y3If using a DIMM topology: x=y +/- 20 psPropagation delay < for DDR3 VTTVTTSDRAMComponentSDRAMComponentSDRAMComponentSDRAMComponentFPGAx + x1 + x2 + x3 = y + y1 + y2 +y3 20 pstCKPropagation delay < for DDR4 tCK6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide250The timing between the DQS and clock signals on each device calibrates dynamicallyto meet tDQSS. The following figure shows the delay requirements to align DQS andclock signals. To ensure that the skew is not too large for the leveling circuit scapability, follow these rules: Propagation delay of clock signal must not be shorter than propagation delay ofDQS signal at every device:CKi DQSi > 0; 0 < i < number of components 1 Total skew of CLK and DQS signal between groups is less than one clock cycle:(CKi + DQSi) max (CKi + DQSi) min < 1 tCKFigure DQS Signal to Align DQS and ClockVTTSDRAMComponentDQ Group 0CKCK0CK1DSQiCKiCKi = Clock signal propagation delay to device iFPGASDRAMComponentSDRAMComponentDQ Group 1DQ Group iDQSi = DQ/DQS signals propagation delay to group iClk pair matching If you are using a DIMM (UDIMM, RDIMM, or LRDIMM) topology,match the trace lengths up to the DIMM connector. If you are using discretecomponents, match the lengths for all the memory components connected in the fly-by group length matching If you are using a DIMM (UDIMM, RDIMM, or LRDIMM)topology, apply the DQ group trace matching rules described in the guideline tableearlier up to the DIMM connector. If you are using discrete components, match thelengths up to the respective memory you are using DIMMs, it is assumed that lengths are tightly matched within theDIMM itself. You should check that appropriate traces are length-matched within Spacing GuidelinesThis topic provides recommendations for minimum spacing between board traces forvarious signal Guidelines for DQ, DQS, and DM TracesMaintain a minimum of 3H spacing between the edges (air-gap) of these traces.(Where H is the vertical distance to the closest return path for that particular trace.) GND or Power3HHGND or PowerH6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide251Spacing Guidelines for Address and Command and Control TracesMaintain at least 3H spacing between the edges (air-gap) of these traces. (Where H isthe vertical distance to the closest return path for that particular trace.) GND or Power3HHGND or PowerHSpacing Guidelines for Clock TracesMaintain at least 5H spacing between two clock pair or a clock pair and any othermemory interface trace. (Where H is the vertical distance to the closest return path forthat particular trace.) 5HGND or PowerHHGND or Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits)The following topics discuss different ways to lay out a wider DDR3 or DDR4 SDRAMinterface to the FPGA. Choose the topology based on board trace simulation and thetiming budget of your EMIF IP supports up to a 144-bit wide DDR3 interface. You can use discretecomponents or DIMMs to implement a wide interface (any interface wider than 72bits). Intel recommends using leveling when you implement a wide interface withDDR3 you lay out for a wider interface, all rules and constraints discussed in theprevious sections still apply. The DQS, DQ, and DM signals are point-to-point, and allthe same rules discussed in Design Layout Guidelines main challenge for the design of the fly-by network topology for the clock,command, and address signals is to avoid signal integrity issues, and to make sureyou route the DQS, DQ, and DM signals with the chosen LinksDesign Layout Guidelines on page Fly-By Network Design for Clock, Command, and Address SignalsThe EMIF IP requires the flight-time skew between the first SDRAM component andthe last SDRAM component to be less than tCK for memory clocks. Thisconstraint limits the number of components you can have for each fly-by you design with discrete components, you can choose to use one or more fly-bynetworks for the clock, command, and address following figure shows an example of a single fly-by network Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide252Figure Fly-By Network TopologyVTTFPGADDR3SDRAMDDR3SDRAMDDR3SDR AMDDR3SDRAMDDR3SDRAMDDR3SDRAMLess than tCKEvery SDRAM component connected to the signal is a small load that causesdiscontinuity and degrades the signal. When using a single fly-by network topology, tominimize signal distortion, follow these guidelines: Use 16 device instead 4 or 8 to minimize the number of devices connected tothe trace. Keep the stubs as short as possible. Even with added loads from additional components, keep the total trace lengthshort; keep the distance between the FPGA and the first SDRAM component lessthan 5 inches. Simulate clock signals to ensure a decent following figure shows an example of a double fly-by network topology. Thistopology is not rigid but you can use it as an alternative option. The advantage ofusing this topology is that you can have more SDRAM components in a system withoutviolating the tCK rule. However, as the signals branch out, the components stillcreate Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide253Figure Fly-By Network TopologyDDR3SDRAMDDR3SDRAMDDR3SDRAMDDR3S DRAMDDR3SDRAMDDR3SDRAMLess than tFPGADDR3SDRAMDDR3SDRAMDDR3SDRAMDDR3SDRA MDDR3SDRAMDDR3SDRAMLess than tVTTVTTCKCKYou must perform simulations to find the location of the split, and the best impedancefor the traces before and after the following figure shows a way to minimize the discontinuity effect. In this example,keep TL2 and TL3 matches in length. Keep TL1 longer than TL2 and TL3, so that it iseasier to route all the signals during Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide254Figure Discontinuity EffectSplitting PointTL3, ZQ = 50 TL1, ZQ = 25 TL2, ZQ = 50 You can also consider using a DIMM on each branch to replace the the trade impedance on the DIMM card is 40-ohm to 60-ohm, perform aboard trace simulation to control the reflection to within the level your system the fly-by daisy chain topology increases the complexity of the datapath andcontroller design to achieve leveling, but also greatly improves performance and easesboard layout for SDRAM can also use the SDRAM components without leveling in a design if it may resultin a more optimal solution, or use with devices that support the required electricalinterface standard, but do not support the required read and write Package DeskewTrace lengths inside the device package are not uniform for all package pins. Thenonuniformity of package traces can affect system timing for high frequencies. Apackage deskew option is available in the Intel Quartus Prime you do not enable the package deskew option, the Intel Quartus Prime softwareuses the package delay numbers to adjust skews on the appropriate signals; you donot need to adjust for package delays on the board traces. If you do enable thepackage deskew option, the Intel Quartus Prime software does not use the packagedelay numbers for timing analysis, and you must deskew the package delays with theboard traces for the appropriate signals for your LinksLayout Guidelines on page DQ/DQS/DM DeskewTo get the package delay information, follow these steps:6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide2551. Select the FPGA DQ/DQS Package Skews Deskewed on Board checkbox onthe Board Settings tab of the parameter Generate your Instantiate your IP in the Compile your Refer to the All Package Pins compilation report, or find the pin delays displayedin the <core_name>.pin Address and Command DeskewDeskew address and command delays as follows:1. Select the FPGA Address/Command Package Skews Deskewed on Boardcheckbox on the Board Settings tab of the parameter Generate your Instantiate your IP in the Compile your Refer to the All Package Pins compilation report, or find the pin delays displayedin the <core_name>.pin Package Deskew Recommendations for Intel Stratix 10 DevicesThe following table shows package deskew recommendations for Intel Stratix operating frequencies increase, it becomes increasingly critical to perform packagedeskew. The frequencies listed in the table are the minimum frequencies for which youmust perform package you plan to use a listed protocol at the specified frequency or higher, you mustperform package Frequency (MHz) for Which to Perform Package DeskewSingle RankDual RankQuad RankDDR4933800667DDR3933800667LPDDR36675 33Not requiredQDR IV933Not applicableNot applicableRLDRAM 3933667Not applicableQDR II, II+, II+ XtremeNot requiredNot applicableNot Deskew ExampleConsider an example where you want to deskew an interface with 4 DQ pins, 1 DQSpin, and 1 DQSn Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide256Let s assume an operating frequency of 667 MHz, and the package lengths for the pinsreported in the .pin file as follows:dq[0] = 120 psdq[1] = 120 psdq[2] = 100 psdq[3] = 100 psdqs = 80 psdqs_n = 80 psThe following figure illustrates this ExampleFPGA mem_dq[0]mem_dq[1]mem_dq[2]mem_dq[3]mem_ dqsmem_dqs_nmem_dq[0]mem_dq[1]mem_dq[2]m em_dq[3]mem_dqsmem_dqs_nMemory120 ps120 ps100 ps100 ps80 ps80 psABCDEFWhen you perform length matching for all the traces in the DQS group, you must takepackage delays into consideration. Because the package delays of traces A and B are40 ps longer than the package delays of traces E and F, you would need to make theboard traces for E and F 40 ps longer than the board traces for A and similar methodology would apply to traces C and D, which should be 20 ps longerthan the lengths of traces A and following figure shows this scenario with the length of trace A at 450 Example with Trace Delay CalculationsFPGAmem_dq[0]mem_dq[1]mem_dq [2]mem_dq[3]mem_dqsmem_dqs_nmem_dq[0]mem _dq[1]mem_dq[2]mem_dq[3]mem_dqsmem_dqs_n Memory120 ps120 ps100 ps100 ps80 ps80 psA=450psB=A=450psC=A+20ps=470psC=A+20ps =470psC=A+40ps=490psC=A+40ps=490ps6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide257When you enter the board skews into the Board Settings tab of the DDR3 parametereditor, you should calculate the board skew parameters as the sums of board delayand corresponding package delay. If a pin does not have a package delay (such asaddress and command pins), you should use the board delay example of the preceding figure shows an ideal case where board skews areperfectly matched. In reality, you should allow plus or minus 10 ps of skew mismatchwithin a DQS group (DQ/DQS/DM).6 Intel Stratix 10 EMIF IP for DDR4UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide2587 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeThis chapter contains IP parameter descriptions, board skew equations, pin planninginformation, and board design guidance for Intel Stratix 10 external memoryinterfaces for QDR II/II+/II+ Parameter DescriptionsThe following topics describe the parameters available on each tab of the IP parametereditor, which you can use to configure your Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters:GeneralTable : General / InterfaceDisplay NameDescriptionConfigurationSpecifies the configuration of the memory interface. The available optionsdepend on the protocol in use. Options include Hard PHY and HardController, Hard PHY and Soft Controller, or Hard PHY only. If youselect Hard PHY only, the AFI interface is exported to allow connection ofa custom memory controller or third-party IP. (Identifier:PHY_QDR2_CONFIG_ENUM)Table : General / ClocksDisplay NameDescriptionMemory clock frequencySpecifies the operating frequency of the memory interface in MHz. If youchange the memory frequency, you should update the memory latencyparameters on the Memory tab and the memory timing parameters on theMem Timing tab. (Identifier: PHY_QDR2_MEM_CLK_FREQ_MHZ)Use recommended PLL reference clockfrequencySpecifies that the PLL reference clock frequency is automatically calculatedfor best performance. If you want to specify a different PLL reference clockfrequency, uncheck the check box for this parameter. (Identifier:PHY_QDR2_DEFAULT_REF_CLK_FRE Q)PLL reference clock frequencyThis parameter tells the IP what PLL reference clock frequency the user willsupply. Users must select a valid PLL reference clock frequency from thelist. The values in the list can change when the memory interface frequencychanges and/or the clock rate of user logic changes. It is recommended touse the fastest possible PLL reference clock frequency because it leads tobetter jitter performance. Selection is required only if the user does notcheck the "Use recommended PLL reference clock frequency" option.(Identifier: PHY_QDR2_USER_REF_CLK_FREQ_MHZ) UG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008RegisteredDisplay NameDescriptionPLL reference clock jitterSpecifies the peak-to-peak jitter on the PLL reference clock source. Theclock source of the PLL reference clock must meet or exceed the followingjitter requirements: 10ps peak to peak, or RMS at 1e-12 BER, at 1e-16 BER. (Identifier: PHY_QDR2_REF_CLK_JITTER_PS)Clock rate of user logicSpecifies the relationship between the user logic clock frequency and thememory clock frequency. For example, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz, a quarter-rate interfacemeans that the user logic in the FPGA runs at 200MHz. (Identifier:PHY_QDR2_RATE_ENUM)Core clocks sharingWhen a design contains multiple interfaces of the same protocol, rate,frequency, and PLL reference clock source, they can share a common set ofcore clock domains. By sharing core clock domains, they reduce clocknetwork usage and avoid clock synchronization logic between share core clocks, denote one of the interfaces as "Master", and theremaining interfaces as "Slave". In the RTL, connect theclks_sharing_master_out signal from the master interface to theclks_sharing_slave_in signal of all the slave master and slave interfaces still expose their own output clock ports inthe RTL (for example, emif_usr_clk, afi_clk), but the physical signalsare equivalent, hence it does not matter whether a clock port from a masteror a slave is used. As the combined width of all interfaces sharing the samecore clock increases, you may encounter timing closure difficulty fortransfers between the FPGA core and the periphery.(Identifier: PHY_QDR2_CORE_CLKS_SHARING_ENUM)Specify additional core clocks based onexisting PLLDisplays additional parameters allowing you to create additional outputclocks based on the existing PLL. This parameter provides an alternativeclock-generation mechanism for when your design exhaustsavailable PLL resources. The additional output clocks that you create canbe fed into the core. Clock signals created with this parameter aresynchronous to each other, but asynchronous to the memory interface coreclock domains (such as emif_usr_clk or afi_clk). You must followproper clock-domain-crossing techniques when transferring data betweenclock domains. (Identifier: PLL_ADD_EXTRA_CLKS)Table : General / Clocks / Additional Core ClocksDisplay NameDescriptionNumber of additional core clocksSpecifies the number of additional output clocks to create from the PLL.(Identifier: PLL_USER_NUM_OF_EXTRA_CLKS)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_0Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_5)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_5)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_1Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_6)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_6)7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide260Table : General / Clocks / Additional Core Clocks / pll_extra_clk_2Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_7)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_7)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_3Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_8)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_8) Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: FPGAI/OYou should use Hyperlynx* or similar simulators to determine the best settings foryour board. Refer to the EMIF Simulation Guidance wiki page for : FPGA I/O / FPGA I/O SettingsDisplay NameDescriptionVoltageThe voltage level for the I/O pins driving the signals between the memorydevice and the FPGA memory interface. (Identifier:PHY_QDR2_IO_VOLTAGE)Periodic OCT re-calibrationSpecifies that the system periodically recalibrate on-chip termination (OCT)to minimize variations in termination value caused by changing operatingconditions (such as changes in temperature). By recalibrating OCT, I/Otiming margins are improved. When enabled, this parameter causes thePHY to halt user traffic about every seconds for about 1900 memoryclock cycles, to perform OCT recalibration. Efficiency is reduced byabout 1% when this option is enabled. (Identifier:PHY_QDR2_USER_PERIODIC_OCT_R ECAL_ENUM)Use default I/O settingsSpecifies that a legal set of I/O settings are automatically selected. Thedefault I/O settings are not necessarily optimized for a specific board. Toachieve optimal signal integrity, perform I/O simulations with IBIS modelsand enter the I/O settings manually, based on simulation results.(Identifier: PHY_QDR2_DEFAULT_IO)7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide261Table : FPGA I/O / FPGA I/O Settings / Address/CommandDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the address/command pins of thememory interface. The selected I/O standard configures the circuit withinthe I/O buffer to match the industry standard. (Identifier:PHY_QDR2_USER_AC_IO_STD_ENUM )Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_QDR2_USER_AC_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_QDR2_USER_AC_SLEW_RATE_ENUM)Table : FPGA I/O / FPGA I/O Settings / Memory ClockDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the memory clock pins. Theselected I/O standard configures the circuit within the I/O buffer to matchthe industry standard. (Identifier: PHY_QDR2_USER_CK_IO_STD_ENUM)Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_QDR2_USER_CK_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_QDR2_USER_CK_SLEW_RATE_ENUM)Table : FPGA I/O / FPGA I/O Settings / Data BusDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the data and data clock/strobe pinsof the memory interface. The selected I/O standard option configures thecircuit within the I/O buffer to match the industry standard. (Identifier:PHY_QDR2_USER_DATA_IO_STD_EN UM)Output modeThis parameter allows you to change the output current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_QDR2_USER_DATA_OUT_MODE_ENUM)Input modeThis parameter allows you to change the input termination settings for theselected I/O standard. Perform board simulation with IBIS models todetermine the best settings for your design. (Identifier:PHY_QDR2_USER_DATA_IN_MODE_E NUM)Use recommended initial VrefinSpecifies that the initial Vrefin setting is calculated automatically, to areasonable value based on termination settings. (Identifier:PHY_QDR2_USER_AUTO_STARTING_ VREFIN_EN)Initial VrefinSpecifies the initial value for the reference voltage on the datapins(Vrefin). This value is entered as a percentage of the supply voltagelevel on the I/O pins. The specified value serves as a starting point and maybe overridden by calibration to provide better timing margins. If you chooseto skip Vref calibration (Diagnostics tab), this is the value that is usedas the Vref for the interface. (Identifier:PHY_QDR2_USER_STARTING_VREFI N)7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide262Table : FPGA I/O / FPGA I/O Settings / PHY InputsDisplay NameDescriptionPLL reference clock I/O standardSpecifies the I/O standard for the PLL reference clock of the memoryinterface. (Identifier: PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM)RZ Q I/O standardSpecifies the I/O standard for the RZQ pin used in the memory interface.(Identifier: PHY_QDR2_USER_RZQ_IO_STD_ENUM) Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters:MemoryTable : Memory / TopologyDisplay NameDescriptionData width per deviceNumber of D and Q pins per QDR II device. (Identifier:MEM_QDR2_DATA_PER_DEVICE)Ena ble BWS# pinsIndicates whether the interface uses the BWS#(Byte Write Select) pins. Ifenabled, 1 BWS# pin for every 9 D pins will be added. (Identifier:MEM_QDR2_BWS_EN)Enable width expansionIndicates whether to combine two memory devices to double the data buswidth. With two devices, the interface supports a width expansionconfiguration up to 72-bits. For width expansion configuration, the addressand control signals are routed to 2 devices. (Identifier:MEM_QDR2_WIDTH_EXPANDED)Addr ess widthNumber of address pins. (Identifier: MEM_QDR2_ADDR_WIDTH)Burst lengthBurst length of the memory device. (Identifier: MEM_QDR2_BL) Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: MemTimingThese parameters should be read from the table in the datasheet associated with thespeed bin of the memory device (not necessarily the frequency at which the interfaceis running).Table : Mem TimingDisplay NameDescriptionSpeed binThe speed grade of the memory device used. This parameter refers to themaximum rate at which the memory device is specified to run. (Identifier:MEM_QDR2_SPEEDBIN_ENUM)tRLtR L refers to the QDR memory specific read latency. This parameterdescribes the length of time after a Read command has been registered onthe rising edge of the Write Clock (K) at the QDR memory before the firstpiece of read data (Q) can be expected at the output of the memory. It ismeasured in Write Clock (K) cycles. The Read Latency is specific to aQDR memory device and cannot be modified to a different Read Latency (tRL) can have the following values: , 2, 2,5 clkcycles. (Identifier: MEM_QDR2_TRL_CYC)tSAtSA refers to the setup time for the address and command bus (A)before the rising edge of the clock (K). The address and command busmust be stable for at least tSA before the rising edge of K. (Identifier:MEM_QDR2_TSA_NS) 7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide263Display NameDescriptiontHAtHA refers to the hold time after the rising edge of the clock (K) tothe address and command control bus (A). The address and commandcontrol bus must remain stable for at least tHA after the rising edge of K.(Identifier: MEM_QDR2_THA_NS)tSDtSD refers to the setup time for the data bus (D) before the risingedge of the clock (K). The data bus must be stable for at least tSD beforethe rising edge of K. (Identifier: MEM_QDR2_TSD_NS)tHDtHD refers to the hold time after the rising edge of the clock (K) tothe data bus (D). The data bus must remain stable for at least tHD afterthe rising edge of K. (Identifier: MEM_QDR2_THD_NS)tCQDtCQD refers to the maximum time expected between an echo clock edgeand valid data on the Read Data bus (Q). (Identifier:MEM_QDR2_TCQD_NS)tCQDOHtCQDO H refers to the minimum time expected between the echo clock (CQor CQ#) edge and the last of the valid Read data (Q). (Identifier:MEM_QDR2_TCQDOH_NS)Internal JitterQDRII internal jitter. (Identifier: MEM_QDR2_INTERNAL_JITTER_NS)tCQHtCQH describes the time period during which the echo clock (CQ, #CQ) isconsidered logically high. (Identifier: MEM_QDR2_TCQH_NS)tCCQOtCCQO describes the skew between the rising edge of the C clock tothe rising edge of the echo clock (CQ) in QDRII memory devices.(Identifier: MEM_QDR2_TCCQO_NS) Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: BoardTable : Board / Intersymbol Interference/CrosstalkDisplay NameDescriptionUse default ISI/crosstalk valuesYou can enable this option to use default intersymbol interference andcrosstalk values for your topology. Note that the default values are notoptimized for your board. For optimal signal integrity, it is recommendedthat you do not enable this parameter, but instead perform I/O simulationusing IBIS models and Hyperlynx)*, and manually enter values based onyour simulation results, instead of using the default values. (Identifier:BOARD_QDR2_USE_DEFAULT_ISI_V ALUES)Address and command ISI/crosstalkThe address and command window reduction due to ISI and crosstalkeffects. The number to be entered is the total loss of margin on both thesetup and hold sides (measured loss on the setup side + measuredloss on the hold side). Refer to the EMIF Simulation Guidance wiki pagefor additional information. (Identifier: BOARD_QDR2_USER_AC_ISI_NS)CQ/CQ# ISI/crosstalkCQ/CQ# ISI/crosstalk describes the reduction of the read data window dueto intersymbol interference and crosstalk effects on the CQ/CQ# signalwhen driven by the memory device during a read. The number to beentered is the total loss of margin on the setup and hold sides(measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_QDR2_USER_RCLK_ISI_NS)Read Q ISI/crosstalkRead Q ISI/crosstalk describes the reduction of the read data window dueto intersymbol interference and crosstalk effects on the CQ/CQ# signalwhen driven by the memory device during a read. The number to beentered is the total loss of margin on the setup and hold 7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide264Display NameDescription(measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_QDR2_USER_RDATA_ISI_NS)K/K# ISI/crosstalkK/K# ISI/crosstalk describes the reduction of the write data window due tointersymbol interference and crosstalk effects on the K/K# signal whendriven by the FPGA during a write. The number to be entered is the totalloss of margin on the setup and hold sides (measured loss on thesetup side + measured loss on the hold side). Refer to the EMIFSimulation Guidance wiki page for additional information. (Identifier:BOARD_QDR2_USER_WCLK_ISI_NS) Write D ISI/crosstalkWrite D ISI/crosstalk describes the reduction of the write data window dueto intersymbol interference and crosstalk effects on the signal when drivenby driven by the FPGA during a write. The number to be entered is thetotal loss of margin on the setup and hold sides (measured loss onthe setup side + measured loss on the hold side). Refer to the EMIFSimulation Guidance wiki page for additional information. (Identifier:BOARD_QDR2_USER_WDATA_ISI_NS )Table : Board / Board and Package SkewsDisplay NameDescriptionPackage deskewed with board layout(Q group)If you are compensating for package skew on the Q bus in the board layout(hence checking the box here), please include package skew incalculating the following board skew parameters. (Identifier:BOARD_QDR2_IS_SKEW_WITHIN_Q_ DESKEWED)Maximum board skew within Q groupThis parameter describes the largest skew between all Q signals in a Qgroup. Q pins drive the data signals from the memory to the FPGA whenthe read operation is active. Users should enter their board skew skew will be calculated automatically, based on the memoryinterface configuration, and added to this value. This value affects theread capture and write margins. (Identifier:BOARD_QDR2_BRD_SKEW_WITHIN_Q _NS)Maximum system skew within Q groupThe largest skew between all Q pins in a Q group. Enter combined boardand package skew. This value affects the read capture and write margins.(Identifier: BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS)Pack age deskewed with board layout(D group)If you are compensating for package skew on the D and BWS# signals inthe board layout (hence checking the box here), please include packageskew in calculating the following board skew parameters. (Identifier:BOARD_QDR2_IS_SKEW_WITHIN_D_ DESKEWED)Maximum board skew within D groupThis parameter refers to the largest skew between all D and BWS# signalsin a D group. D pins are used for driving data signals to the memory deviceduring a write operation. BWS# pins are used as Byte Write Select signalsto control which byte(s) are written to the memory during a writeoperation. Users should enter their board skew only. Package skew willbe calculated automatically, based on the memory interface configuration,and added to this value. This value affects the read capture and writemargins. (Identifier: BOARD_QDR2_BRD_SKEW_WITHIN_D_NS)Maximum system skew within D groupThe largest skew between all D and BWS# pins in a D group. Entercombined board and package skew. This value affects the read capture andwrite margins. (Identifier: BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS)Pack age deskewed with board layout(address/command bus)Enable this parameter if you are compensating for package skew on theaddress, command, control, and memory clock buses in the board package skew in calculating the following board skewparameters. (Identifier:BOARD_QDR2_IS_SKEW_WITHIN_AC _DESKEWED) 7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide265Display NameDescriptionMaximum board skew within address/command busThe largest skew between the address and command signals. Enter theboard skew only; package skew is calculated automatically, based on thememory interface configuration, and added to this value. (Identifier:BOARD_QDR2_BRD_SKEW_WITHIN_A C_NS)Maximum system skew within address/command busMaximum system skew within address/command bus refers to the largestskew between the address and command signals. (Identifier:BOARD_QDR2_PKG_BRD_SKEW_WITH IN_AC_NS)Average delay difference betweenaddress/command and KThis parameter refers to the average delay difference between the Address/Command signals and the K signal, calculated by averaging the longest andsmallest Address/Command trace delay minus the maximum K trace values represent address and command signals that are longerthan K signals and negative values represent address and command signalsthat are shorter than K signals. (Identifier:BOARD_QDR2_AC_TO_K_SKEW_NS)M aximum K delay to deviceThe maximum K delay to device refers to the delay of the longest K tracefrom the FPGA to any device (Identifier: BOARD_QDR2_MAX_K_DELAY_NS) Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters:ControllerTable : ControllerDisplay NameDescriptionAvalon InterfaceSelects the Avalon Interface through which the controller interacts with userlogic (Identifier: CTRL_QDR2_AVL_PROTOCOL_ENUM)Maximum Avalon-MM burst lengthSpecifies the maximum burst length on the Avalon-MM bus. This will beused to configure the FIFOs to be able to manage the maximum data core logic will be required for an increase in FIFO length.(Identifier: CTRL_QDR2_AVL_MAX_BURST_COUNT)Generate power-of-2 data bus widthsfor QsysIf enabled, the Avalon data bus width is rounded down to thenearest power-of-2. The width of the symbols within the data bus is alsorounded down to the nearest power-of-2. You should only enable this optionif you know you will be connecting the memory interface to Qsysinterconnect components that require the data bus and symbol width to bea power-of-2. If this option is enabled, you cannot utilize the fulldensity of the memory example, in x36 data width upon selecting this parameter, will definethe Avalon data bus to 256-bit. This will ignore the upper 4-bit of datawidth.(Identifier: CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS) Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters:DiagnosticsTable : Diagnostics / Simulation OptionsDisplay NameDescriptionCalibration modeSpecifies whether to skip memory interface calibration duringsimulation, or to simulate the full calibration 7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide266Display NameDescriptionSimulating the full calibration process can take hours (or even days),depending on the width and depth of the memory interface. You canachieve much faster simulation times by skipping the calibration process,but that is only expected to work when the memory model is ideal and theinterconnect delays are you enable this parameter, the interface still performs some memoryinitialization before starting normal operations. Abstract PHY is supportedwith skip calibration.(Identifier: DIAG_QDR2_SIM_CAL_MODE_ENUM)Abstract phy for fast simulationSpecifies that the system use Abstract PHY for simulation. Abstract PHYreplaces the PHY with a model for fast simulation and can reducesimulation time by 2-3 times. Abstract PHY is available for certainprotocols and device families, and only when you select Skip Calibration.(Identifier: DIAG_QDR2_ABSTRACT_PHY)Table : Diagnostics / Calibration Debug OptionsDisplay NameDescriptionQuartus Prime EMIF Debug Toolkit/On-Chip Debug PortSpecifies the connectivity of an Avalon slave interface for use by theQuartus Prime EMIF Debug Toolkit or user core you set this parameter to "Disabled", no debug features are enabled. Ifyou set this parameter to "Export", an Avalon slave interface named"cal_debug" is exported from the IP. To use this interface with the EMIFDebug Toolkit, you must instantiate and connect an EMIF debug interface IPcore to it, or connect it to the cal_debug_out interface of another EMIFcore. If you select "Add EMIF Debug Interface", an EMIF debug interfacecomponent containing a JTAG Avalon Master is connected to the debug port,allowing the core to be accessed by the EMIF Debug one EMIF debug interface should be instantiated per I/O column. Youcan chain additional EMIF or PHYLite cores to the first by enabling the"Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option for all cores in the chain, and selecting "Export"for the "Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port"option on all cores after the first.(Identifier: DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE)Enable Daisy-Chaining for QuartusPrime EMIF Debug Toolkit/On-ChipDebug PortSpecifies that the IP export an Avalon-MM master interface(cal_debug_out) which can connect to the cal_debug interface of otherEMIF cores residing in the same I/O column. This parameter applies onlyif the EMIF Debug Toolkit or On-Chip Debug Port is enabled. Refer tothe Debugging Multiple EMIFs wiki page for more information aboutdebugging multiple EMIFs. (Identifier:DIAG_QDR2_EXPORT_SEQ_AVALON_ MASTER)Interface IDIdentifies interfaces within the I/O column, for use by the EMIF DebugToolkit and the On-Chip Debug Port. Interface IDs should be unique amongEMIF cores within the same I/O column. If the Quartus Prime EMIFDebug Toolkit/On-Chip Debug Port parameter is set to Disabled, theinterface ID is unused. (Identifier: DIAG_QDR2_INTERFACE_ID)Use Soft NIOS Processor for On-ChipDebugEnables a soft Nios processor as a peripheral component to access the On-Chip Debug Port. Only one interface in a column can activate this option.(Identifier: DIAG_SOFT_NIOS_MODE)7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide267Table : Diagnostics / Example DesignDisplay NameDescriptionNumber of core clocks sharing slaves toinstantiate in the example designSpecifies the number of core clock sharing slaves to instantiate in theexample design. This parameter applies only if you set the "Core clockssharing" parameter in the "General" tab to "Master" or "Slave".(Identifier: DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES)Enable In-System-Sources-and-ProbesEnables In-System-Sources-and-Probes in the example design for commondebug signals, such as calibration status or example traffic generator per-bit status. This parameter must be enabled if you want to do drivermargining. (Identifier: DIAG_QDR2_EX_DESIGN_ISSP_EN)Table : Diagnostics / Traffic GeneratorDisplay NameDescriptionUse configurable Avalon trafficgenerator option allows users to add the new configurable Avalon trafficgenerator to the example design. (Identifier: DIAG_QDR2_USE_TG_AVL_2)Bypass the default traffic patternSpecifies that the controller/interface bypass the traffic generator pattern after reset. If you do not enable this parameter, the trafficgenerator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_QDR2_BYPASS_DEFAULT_PATTERN)Bypass the user-configured traffic stageSpecifies that the controller/interface bypass the user-configured trafficgenerator's pattern after reset. If you do not enable this parameter, thetraffic generator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration can be done by connecting to the traffic generator via theEMIF Debug Toolkit, or by using custom logic connected to the Avalon-MMconfiguration slave port on the traffic generator. Configuration can also besimulated using the example testbench provided in file.(Identifier: DIAG_QDR2_BYPASS_USER_STAGE)Bypass the traffic generator repeated-writes/repeated-reads test patternSpecifies that the controller/interface bypass the traffic generator's repeattest stage. If you do not enable this parameter, every write and read isrepeated several times. (Identifier: DIAG_QDR2_BYPASS_REPEAT_STAGE)Bypass the traffic generator stresspatternSpecifies that the controller/interface bypass the traffic generator's stresspattern stage. (Stress patterns are meant to create worst-case signalintegrity patterns on the data pins.) If you do not enable this parameter,the traffic generator does not assert a pass or fail status until the generatoris configured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_QDR2_BYPASS_STRESS_STAGE)Export Traffic Generator interfaceSpecifies that the IP export an Avalon-MM slave port for configuring theTraffic Generator. This is required only if you are configuring the trafficgenerator through user logic and not through through the EMIF DebugToolkit. (Identifier: DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE)Table : Diagnostics / PerformanceDisplay NameDescriptionEnable Efficiency MonitorAdds an Efficiency Monitor component to the Avalon-MM interface of thememory controller, allowing you to view efficiency statistics of the can access the efficiency statistics using the EMIF Debug Toolkit.(Identifier: DIAG_QDR2_EFFICIENCY_MONITOR)7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide268Table : Diagnostics / MiscellaneousDisplay NameDescriptionUse short Qsys interface namesSpecifies the use of short interface names, for improved usability andconsistency with other Qsys components. If this parameter is disabled, thenames of Qsys interfaces exposed by the IP will include the type anddirection of the interface. Long interface names are supported forbackward-compatibility and will be removed in a future release. (Identifier:SHORT_QSYS_INTERFACE_NAMES) Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters:Example DesignsTable : Example Designs / Available Example DesignsDisplay NameDescriptionSelect designSpecifies the creation of a full Quartus Prime project, instantiating anexternal memory interface and an example traffic generator, according toyour parameterization. After the design is created, you can specify thetarget device and pin location assignments, run a full compilation, verifytiming closure, and test the interface on your board using the programmingfile created by the Quartus Prime assembler. The 'Generate ExampleDesign' button lets you generate simulation or synthesis file sets.(Identifier: EX_DESIGN_GUI_QDR2_SEL_DESIGN)Table : Example Designs / Example Design FilesDisplay NameDescriptionSimulationSpecifies that the 'Generate Example Design' button create all necessaryfile sets for simulation. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, simulation file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the simulation example design, and file with other corresponding tcl files. You canrun from a command line to generate thesimulation example design. The generated example designs for varioussimulators are stored in the /sim sub-directory. (Identifier:EX_DESIGN_GUI_QDR2_GEN_SIM)S ynthesisSpecifies that the 'Generate Example Design' button create all necessaryfile sets for synthesis. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, synthesis file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the synthesis example design, and script with other corresponding tcl files. You canrun from a command line to generate thesynthesis example design. The generated example design is stored inthe /qii sub-directory. (Identifier: EX_DESIGN_GUI_QDR2_GEN_SYNTH)Table : Example Designs / Generated HDL FormatDisplay NameDescriptionSimulation HDL formatThis option lets you choose the format of HDL in which generatedsimulation files are created. (Identifier:EX_DESIGN_GUI_QDR2_HDL_FORMA T)7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide269Table : Example Designs / Target Development KitDisplay NameDescriptionSelect boardSpecifies that when you select a development kit with a memory module,the generated example design contains all settings and fixed pinassignments to run on the selected board. You must select a developmentkit preset to generate a working example design for the specifieddevelopment kit. Any IP settings not applied directly from a developmentkit preset will not have guaranteed results when testing the developmentkit. To exclude hardware support of the example design, select 'none' fromthe 'Select board' pull down menu. When you apply a development kitpreset, all IP parameters are automatically set appropriately to match theselected preset. If you want to save your current settings, you should do sobefore you apply the preset. You can save your settings under a differentname using File->Save as. (Identifier:EX_DESIGN_GUI_QDR2_TARGET_DE V_KIT) Board Skew EquationsThe following table presents the underlying equations for the board skew Equations for QDRII, QDRII+, and QDRII+ Xtreme Board SkewParametersTable Skew Parameter EquationsParameterDescription/EquationMa ximum system skewwithin address/commandbusMaxAC MinACThe largest skew between the address and command signals. Enter combined board andpackage delay differencebetween address/commandand KThe average delay difference between the address and command signals and the K signal,calculated by averaging the longest and smallest Address/Command signal delay minus theK delay. Positive values represent address and command signals that are longer than Ksignals and negative values represent address and command signals that are shorter thanK signals. The Quartus Prime software uses this skew to optimize the delay of the addressand command signals to have appropriate setup and hold margins. n=nn= 1LongestACPathDelay+ShortestACPathDelay2 KnPathDelaynwhere n is the number of K board skew withinQ groupThe largest skew between all Q pins in a Q group. Enter your board skew only. Packageskew is calculated automatically, based on the memory interface configuration, and addedto this value. This value affects the read capture and write minQgwhere g is the number of Q board skew withinD groupThe largest skew between all D and BWS# pins in a D group. Enter your board skew skew is calculated automatically, based on the memory interface configuration,and added to this value. This value affects the read capture and write minDgwhere g is the number of D K delay to devicemaxnKnPathDelaywhere n is the number of K Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Pin and Resource PlanningThe following topics provide guidelines on pin placement for external , all external memory interfaces require the following FPGA resources: Interface pins PLL and clock network Other FPGA resources for example, core fabric logic, and on-chip termination(OCT) calibration blocksOnce all the requirements are known for your external memory interface, you canbegin planning your Interface PinsAny I/O banks that do not support transceiver operations in Intel Stratix 10 devicessupport external memory interfaces. However, DQS (data strobe or data clock) andDQ (data) pins are listed in the device pin tables and are fixed at specific locations inthe device. You must adhere to these pin locations to optimize routing, minimize skew,and maximize margins. Always check the pin table for the actual locations of the DQSand DQ : Maximum interface width varies from device to device depending on the number ofI/O pins and DQS or DQ groups available. Achievable interface width also depends onthe number of address and command pins that the design requires. To ensureadequate PLL, clock, and device routing resources are available, you should alwaystest fit any IP in the Intel Quartus Prime Prime software before PCB devices do not limit the width of external memory interfaces beyond thefollowing requirements: Maximum possible interface width in any particular device is limited by thenumber of DQS groups available. Sufficient clock networks are available to the interface PLL as required by the IP. Sufficient spare pins exist within the chosen bank or side of the device to includeall other address and command, and clock pin placement requirements. The greater the number of banks, the greater the skew, hence Intel recommendsthat you always generate a test project of your desired configuration and confirmthat it meets Estimating Pin RequirementsYou should use the Intel Quartus Prime software for final pin fitting. However, you canestimate whether you have enough pins for your memory interface using the EMIFDevice Selector on , or perform the following steps:7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide2711. Determine how many read/write data pins are associated per data strobe or Calculate the number of other memory interface pins needed, including any otherclocks (write clock or memory system clock), address, command, and RZQ. Referto the External Memory Interface Pin Table to determine necessary Address/Command/Clock pins based on your desired Calculate the total number of I/O banks required to implement the memoryinterface, given that an I/O bank supports up to 48 GPIO should test the proposed pin-outs with the rest of your design in the Intel QuartusPrime software (with the correct I/O standard and OCT connections) before finalizingthe pin-outs. There can be interactions between modules that are illegal in the IntelQuartus Prime software that you might not know about unless you compile the designand use the Intel Quartus Prime Pin LinksExternal Memory Interfaces Support Maximum Number of InterfacesThe maximum number of interfaces supported for a given memory protocol varies,depending on the FPGA in otherwise noted, the calculation for the maximum number of interfaces isbased on independent interfaces where the address or command pins are not : You may need to share PLL clock outputs depending on your clock network interface information for Intel Stratix 10, consult the EMIF Device Selector closure depends on device resource and routing utilization. For moreinformation about timing closure, refer to the Area and Timing OptimizationTechniques chapter in the Intel Quartus Prime Links External Memory Interfaces Support Center Intel Stratix 10 EMIF Architecture: PLL Reference Clock Networks on page 20 External Memory Interface Device Selector Intel Quartus Prime Pro Edition FPGA ResourcesThe Intel FPGA memory interface IP uses FPGA fabric, including registers and theMemory Block to implement the memory OCT calibration block is used if you are using the FPGA OCT feature in thememory interface. The OCT calibration block uses a single pin (RZQ). You can selectany of the available OCT calibration block as you do not need to place this block in thesame bank or device side of your memory interface. The only requirement is that theI/O bank where you place the OCT calibration block uses the same VCCIO voltage asthe memory interface. You can share multiple memory interfaces with the same OCTcalibration block if the VCCIO voltage is the Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User OCTIf the memory interface uses any FPGA OCT calibrated series, parallel, or dynamictermination for any I/O in your design, you need a calibration block for the OCTcircuitry. This calibration block is not required to be within the same bank or side ofthe device as the memory interface RZQ pin in Intel Stratix 10 devices can be used as a general purpose I/O pin whenit is not used to support OCT, provided the signal conforms to the bank PLLWhen using PLL for external memory interfaces, you must consider the followingguidelines: For the clock source, use the clock input pin specifically dedicated to the PLL thatyou want to use with your external memory interface. The input and output pinsare only fully compensated when you use the dedicated PLL clock input pin. If theclock source for the PLL is not a dedicated clock input pin for the dedicated PLL,you would need an additional clock network to connect the clock source to the PLLblock. Using additional clock network may increase clock jitter and degrade thetiming margin. Pick a PLL and PLL input clock pin that are located on the same side of the deviceas the memory interface pins. Share the DLL and PLL static clocks for multiple memory interfaces provided thecontrollers are on the same or adjacent side of the device and run at the samememory clock frequency. If your design uses a dedicated PLL to only generate a DLL input reference clock,you must set the PLL mode to No Compensation in the Intel Quartus Primesoftware to minimize the jitter, or the software forces this setting PLL does not generate other output, so it does not need to compensate forany clock Pin Guidelines for Intel Stratix 10 EMIF IPThe Intel Stratix 10 device contains up to three I/O columns that can be used byexternal memory Intel Stratix 10 I/O subsystem resides in the I/Ocolumns. Each column contains multiple I/O banks, each of which consists of four I/Olanes. An I/O lane is a group of twelve I/O Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide273The I/O column, I/O bank, I/O lane, adjacent I/O bank, and pairing pin for everyphysical I/O pin can be uniquely identified using the Bank Number and Indexwithin I/O Bank values which are defined in each Intel Stratix 10 device pin-outfile. The numeric component of the Bank Number value identifies the I/O column,while the letter represents the I/O bank. The Index within I/O Bank value falls within one of the following ranges: 0 to11, 12 to 23, 24 to 35, or 36 to 47, and represents I/O lanes 1, 2, 3, and 4,respectively. The adjacent I/O bank is defined as the I/O bank with same column number butthe letter is either before or after the respective I/O bank letter in the A-Z system. The pairing pin for an I/O pin is located in the same I/O bank. You can identify thepairing pin by adding one to its Index within I/O Bank number (if it is aneven number), or by subtracting one from its Index within I/O Bank number(if it is an odd number).For example, a physical pin with a Bank Number of 2M and Index within I/OBank of 22, indicates that the pin resides in I/O lane 2, in I/O bank 2M, in column adjacent I/O banks are 2L and 2N. The pairing pin for this physical pin is the pinwith an Index within I/O Bank of 23 and Bank Number of General GuidelinesYou should follow the recommended guidelines when performing pin placement for allexternal memory interface pins targeting Intel Stratix 10 devices, whether you areusing the hard memory controller or your own you are using the hard memory controller, you should employ the relative pinlocations defined in the <variation_name>/altera_emif_arch_nd_versionnumber/<synth|sim>/<variation_name>_altera_emif_arch_nd_versionnumber_<unique ID> file, w+ted with your : 1. EMIF IP pin-out requirements for the Intel Stratix 10 Hard Processor Subsystem(HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IPdefines a fixed pin-out in the Intel Quartus Prime IP file (.qip), based on the IPconfiguration. When targeting Intel Stratix 10 HPS, you do not need to makelocation assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the IntelQuartus Prime software. Alternatively, consult the device handbook or the devicepin-out files. For information on how you can customize the HPS EMIF pin-out,refer to Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP with Ping Pong PHY, PHY only, RLDRAMx , QDRx and LPDDR3 are not supported Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide274Observe the following general guidelines when placing pins for your Intel Stratix 10external memory interface:1. Ensure that the pins of a single external memory interface reside within a singleI/O An external memory interface can occupy one or more banks in the same I/Ocolumn. When an interface must occupy multiple banks, ensure that those banksare adjacent to one Any pin in the same bank that is not used by an external memory interface isavailable for use as a general purpose I/O of compatible voltage and All address and command pins and their associated clock pins (CK and CK#) mustreside within a single bank. The bank containing the address and command pins isidentified as the address and command To minimize latency, when the interface uses more than two banks, you mustselect the center bank of the interface as the address and command The address and command pins and their associated clock pins in the address andcommand bank must follow a fixed pin-out scheme, as defined in the Intel Stratix10 External Memory Interface Pin Information File, which is available do not have to place every address and command pin manually. If you assignthe location for one address and command pin, the Fitter automatically places theremaining address and command : The pin-out scheme is a hardware requirement that you must follow, andcan vary according to the topology of the memory device. Some schemesrequire three lanes to implement address and command pins, while othersrequire four lanes. To determine which scheme to follow, refer to themessages window during parameterization of your IP, or to the<variation_name>/altera_emif_arch_nd_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nd_<version>_<uniqueID> file after you have generated your An unused I/O lane in the address and command bank can serve to implement adata group, such as a x8 DQS group. The data group must be from the samecontroller as the address and command An I/O lane must not be used by both address and command pins and data Place read data groups according to the DQS grouping in the pin table and PinPlanner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQand CQ# / QK and QK#) must reside at physical pins capable of functioning asDQS/CQ and DQSn/CQn for a specific read data group size. You must place theassociated read data pins (such as DQ and Q), within the same Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide275Note: other device families, there is no need to swap CQ/CQ# pins incertain QDR II and QDR II+ latency requires that the polarity of all QKB/QKB# pins be swapped withrespect to the polarity of the differential buffer inputs on the FPGA toensure correct data capture on port B. All QKB pins on the memorydevice must be connected to the negative pins of the input buffers onthe FPGA side, and all QKB# pins on the memory device must beconnected to the positive pins of the input buffers on the FPGA that the port names at the top-level of the IP already reflect thisswap (that is, mem_qkb is assigned to the negative buffer leg, andmem_qkb_n is assigned to the positive buffer leg).10. You can implement two x4 DQS groups with a single I/O lane. The pin tablespecifies which pins within an I/O lane can be used for the two pairs of DQS andDQS# signals. In addition, for x4 DQS groups you must observe the followingrules: There must be an even number of x4 groups in an external memory interface. DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly,DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS groupX and DQS group X+1 must be in the same I/O lane, where X is an You should place the write data groups according to the DQS grouping in the pintable and Pin Planner. Output-only data clocks for QDR II, QDR II+, and QDR II+Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, butmust be placed on a differential pin pair. They must be placed in the same I/Obank as the corresponding DQS : For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced toDK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.12. For protocols and topologies with bidirectional data pins where a write data groupconsists of multiple read data groups, you should place the data groups and theirrespective write and read clock in the same bank to improve I/O do not need to specify the location of every data pin manually. If you assignthe location for the read capture strobe/clock pin pairs, the Fitter willautomatically place the remaining data Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/Opin and another in the pairing pin for that I/O pin. It is recommended though notrequired that you follow the same rule for DBI pins, so that at a later date youhave the freedom to repurpose the pin as : 1. x4 mode does not support DM/DBI, or Intel Stratix 10 EMIF IP for If you are using an Intel Stratix 10 EMIF IP-based RLDRAM 3 external memoryinterface, you should ensure that all the pins in a DQS group (that is, DQ, DM, DK,and QK) are placed in the same I/O bank. This requirement facilitates timingclosure and is necessary for successful compilation of your Interfaces in the Same I/O ColumnTo place multiple interfaces in the same I/O column, you must ensure that the globalreset signals (global_reset_n) for each individual interface all come from the sameinput pin or Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide276I/O Banks Selection For each memory interface, select consecutive I/O banks. (That is, select banksthat contain the same column number and letter before or after the respective I/Obank letter.) A memory interface can only span across I/O banks in the same I/O column. The number of I/O banks that you require depends on the memory interfacewidth. In some device packages, the number of I/O pins in some LVDS I/O banks is lessthat 48 Pins Location All address/command pins for a controller must be in a single I/O bank. If your interface uses multiple I/O banks, the address/command pins must use themiddle bank. If the number of banks used by the interface is even, any of the twomiddle I/O banks can be used for address/command pins. Address/command pins and data pins cannot share an I/O lane but can share anI/O bank. The address/command pin locations for the soft and hard memory controllers arepredefined. In the External Memory Interface Pin Information for Devicesspreadsheet, each index in the "Index within I/O bank" column denotes adedicated address/command pin function for a given protocol. The index numberof the pin specifies to which I/O lane the pin belongs: I/O lane 0 Pins with index 0 to 11 I/O lane 1 Pins with index 12 to 23 I/O lane 2 Pins with index 24 to 35 I/O lane 3 Pins with index 36 to 47 For memory topologies and protocols that require only three I/O lanes for theaddress/command pins, use I/O lanes 0, 1, and 2. Unused address/command pins in an I/O lane can be used as general-purpose Pins AssignmentAssign the clock pin (CK pin) according to the number of I/O banks in an interface: If the number of I/O banks is odd, assign one CK pin to the middle I/O bank. If the number of I/O banks is even, assign the CK pin to either of the middle twoI/O the Fitter can automatically select the required I/O banks, Intel recommendsthat you make the selection manually to reduce the pre-fit run Reference Clock Pin PlacementPlace the PLL reference clock pin in the address/command bank. Other I/O banks maynot have free pins that you can use as the PLL reference clock pin: If you are sharing the PLL reference clock pin between several interfaces, the I/Obanks must be adjacent. (That is, the banks must contain the same columnnumber and letter before or after the respective I/O bank letter.)7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide277The Intel Stratix 10 external memory interface IP does not support PLL Pin PlacementYou may place the RZQ pin in any I/O bank in an I/O column with the correct VCCIO andVCCPT for the memory interface I/O standard in use. However, the recommendedlocation is in the address/command I/O bank, for greater flexibility during debug if anarrower interface project is required for and DQS Pins AssignmentIntel recommends that you assign the DQS pins to the remaining I/O lanes in the I/Obanks as required: Constrain the DQ and DQS signals of the same DQS group to the same I/O lane. You cannot constrain DQ signals from two different DQS groups to the same you do not specify the DQS pins assignment, the Fitter selects the DQS an I/O Bank Across Multiple InterfacesIf you are sharing an I/O bank across multiple external memory interfaces, followthese guidelines: The interfaces must use the same protocol, voltage, data rate, frequency, and PLLreference clock. You cannot use an I/O bank as the address/command bank for more than oneinterface. The memory controller and sequencer cannot be shared. You cannot share an I/O lane. There is only one DQS input per I/O lane, and anI/O lane can connect to only one memory QDR II, QDR II+ and QDR II+ Xtreme SRAM Command SignalsQDR II, QDR II+ and QDR II+ Xtreme SRAM devices use the write port select (WPS#)signal to control write operations and the read port select (RPS#) signal to controlread QDR II, QDR II+ and QDR II+ Xtreme SRAM Address SignalsQDR II, QDR II+ and QDR II+ Xtreme SRAM devices use one address bus (A) for bothread and write QDR II, QDR II+, and QDR II+ Xtreme SRAM Clock SignalsQDR II, QDR II+ and QDR II+ Xtreme SRAM devices have two pairs of clocks, listedbelow. Input clocks K and K# Echo clocks CQ and CQ#In addition, QDR II devices have a third pair of input clocks, C and C#.7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide278The positive input clock, K, is the logical complement of the negative input clock, K#.Similarly, C and CQ are complements of C# and CQ#, respectively. With thesecomplementary clocks, the rising edges of each clock leg latch the DDR QDR II SRAM devices use the K and K# clocks for write access and the C and C#clocks for read accesses only when interfacing more than one QDR II SRAM the number of loads that the K and K# clocks drive affects the switchingtimes of these outputs when a controller drives a single QDR II SRAM device, C andC# are unnecessary. This is because the propagation delays from the controller to theQDR II SRAM device and back are the same. Therefore, to reduce the number of loadson the clock traces, QDR II SRAM devices have a single-clock mode, and the K and K#clocks are used for both reads and writes. In this mode, the C and C# clocks are tiedto the supply voltage (VDD). Intel FPGA external memory IP supports only QDR II, QDR II+, or QDR II+ Xtreme SRAM devices, the rising edge of K is used tocapture synchronous inputs to the device and to drive out data through Q[x:0], insimilar fashion to QDR II SRAM devices in single clock mode. All accesses are initiatedon the rising edge of K .CQ and CQ# are the source-synchronous output clocks from the QDR II, QDR II+, orQDR II+ Xtreme SRAM device that accompanies the read Intel device outputs the K and K# clocks, data, address, and command lines to theQDR II, QDR II+, or QDR II+ Xtreme SRAM device. For the controller to operateproperly, the write data (D), address (A), and control signal trace lengths (andtherefore the propagation times) should be equal to the K and K# clock trace can generate K and K# clocks using any of the PLL registers via the DDR of strict skew requirements between K and K# signals, use adjacent pins togenerate the clock pair. The propagation delays for K and K# from the FPGA to theQDR II, QDR II+, or QDR II+ Xtreme SRAM device are equal to the delays on the dataand address (D, A) signals. Therefore, the signal skew effect on the write and readrequest operations is minimized by using identical DDR output circuits to generateclock and data inputs to the QDR II, QDR II+ and QDR II+ Xtreme SRAM Data, BWS, and QVLD SignalsQDR II, QDR II+ and QDR II+ Xtreme SRAM devices use two unidirectional databuses: one for writes (D) and one for reads (Q).At the pin, the read data is edge-aligned with the CQ and CQ# clocks while the writedata is center-aligned with the K and K# clocks (see the following figures).7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide279Figure CQ and Q Relationship During QDR II+ SRAM ReadCQ# at FPGA PinCQ at FPGA PinQ at FPGA PinCQ at Capture RegisterCQ# at Capture RegisterQ at Capture RegisterDQS phase shiftFigure K and D Relationship During QDR II+ SRAM WriteK# at FPGA PinK at FPGA PinD at FPGA PinThe byte write select signal (BWS#) indicates which byte to write into the II+ and QDR II+ Xtreme SRAM devices also have a QVLD pin that indicates validread data. The QVLD signal is edge-aligned with the echo clock and is asserted highfor approximately half a clock cycle before data is output from : The Intel FPGA external memory interface IP does not use the QVLD Resource Sharing Guidelines (Multiple Interfaces)In Intel Cyclone 10Intel Stratix 10 external memory interface IP, different externalmemory interfaces can share PLL reference clock pins, core clock networks, I/O banks,and hard Nios processors. Each I/O bank has DLL and PLL resources, therefore thesedo not need to be shared. The Intel Quartus Prime Fitter automatically merges DLLand PLL resources when a bank is shared by different external memory interfaces, andduplicates them for a multi-I/O-bank external memory Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide280PLL Reference Clock PinTo conserve pin usage and enable core clock network and I/O bank sharing, you canshare a PLL reference clock pin between multiple external memory interfaces; theinterfaces must be of the same protocol, rate, and frequency. Sharing of a PLLreference clock pin also implies sharing of the reference clock the following guidelines for sharing the PLL reference clock share a PLL reference clock pin, connect the same signal to the pll_ref_clkport of multiple external memory interfaces in the RTL Place related external memory interfaces in the same I/O Place related external memory interfaces in adjacent I/O banks. If you leave anunused I/O bank between the I/O banks used by the external memory interfaces,that I/O bank cannot be used by any other external memory interface with adifferent PLL reference clock : You can place the pll_ref_clk pin in the address and command I/O bank or in adata I/O bank, there is no impact on timing. However, for greatest flexibility duringdebug (such as when creating designs with narrower interfaces), the recommendedplacement is in the address and command I/O Clock NetworkTo access all external memory interfaces synchronously and to reduce global clocknetwork usage, you may share the same core clock network with other externalmemory the following guidelines for sharing the core clock share a core clock network, connect the clks_sharing_master_out of themaster to the clks_sharing_slave_in of all slaves in the RTL Place related external memory interfaces in the same I/O Related external memory interface must have the same rate, memory clockfrequency, and PLL reference BankTo reduce I/O bank utilization, you may share an I/O Bank with other externalmemory the following guidelines for sharing an I/O Bank:1. Related external memory interfaces must have the same protocol, rate, memoryclock frequency, and PLL reference You cannot use a given I/O bank as the address and command bank for more thanone external memory You cannot share an I/O lane between external memory interfaces, but an unusedpin can serve as a general purpose I/O pin, of compatible voltage and Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide281Hard Nios ProcessorAll external memory interfaces residing in the same I/O column will share the samehard Nios processor. The shared hard Nios processor calibrates the external memoryinterfaces QDR II/II+/II+ Xtreme Board Design GuidelinesThe following topics provide guidelines for you to improve your system's signalintegrity and layout guidelines to help successfully implement a QDR II, QDR II+, orQDR II+ Xtreme SRAM interface in your : In the following topics, QDR II SRAM refers to QDR II, QDR II+, and QDR II+ XtremeSRAM unless stated following topics focus on the following key factors that affect signal integrity: I/O standards QDR II SRAM configurations Signal terminations Printed circuit board (PCB) layout guidelinesI/O StandardsQDR II SRAM interface signals use one of the following JEDEC I/O signallingstandards: HSTL-15 provides the advantages of lower power and lower emissions. HSTL-18 provides increased noise immunity with slightly greater output QDR II SRAM ConfigurationsThe QDR II SRAM Controller for Intel Stratix 10 EMIF IP supports interfaces with asingle device, and two devices in a width expansion configuration up to maximumwidth of 72 following figure shows the main signal connections between the FPGA and a singleQDR II SRAM Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide282Figure With A Single QDR II SRAM ComponentDOFFnQDR II DeviceDOFFZQRQVTTVTTDATA INQCQ/CQDBWSK/KAWPSRPSCQ/CQnDATA OUTBWSnK/KnADDRESSWPSnRPSnVTT(1)(2)(3)(3 )(3)(3)(3)(4)The following figure shows the main signal connections between the FPGA and twoQDR II SRAM components in a width expansion With Two QDR II SRAM Components In A Width ExpansionConfigurationDOFFnDATA IN(1)(2)(2)(3)(3)(3)(3)CQ/CQn0CQ/CQn1DAT A OUTBWSnK0/K0nK1/K1nADDRESSWPSnRPSnVTTQDR II SRAM Device 1DOFFZQRQQCQ/CQnDBWSK/KAWPSRPSVTTVTTVTTV TTQDR II SRAM Device 2DOFFZQRQQCQ/CQnDBWSK/KAWPSRPSVTT(3)(4)( 4)(4)(4)VTT(5)VTT(3)VTTVTTThe following figure shows the detailed balanced topology recommended for theaddress and command signals in the width expansion Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide283Figure Parallel Termination for Balanced TopologyTL1VTT(1)TL2TL2FPGAQDRII MemoryQDRII General Layout GuidelinesThe following table lists general board design layout guidelines. These guidelines areIntel recommendations, and should not be considered as hard requirements. Youshould perform signal integrity simulation on all the traces to verify the signal integrityof the interface. You should extract the slew rate and propagation delay information,enter it into the IP and compile the design to ensure that timing requirements Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide284Table Layout GuidelinesParameterGuidelinesImpedance All unused via pads must be removed, because they cause unwantedcapacitance. Trace impedance plays an important role in the signal integrity. You mustperform board level simulation to determine the best characteristic impedancefor your PCB. For example, it is possible that for multi rank systems 40 ohmscould yield better results than a traditional 50 ohm characteristic Parameter Use uF in 0402 size to minimize inductance Make VTT voltage decoupling close to termination resistors Connect decoupling caps between VTT and ground Use a uF cap for every other VTT pin and uF cap for every VDD andVDDQ pin Verify the capacitive decoupling using the Intel Power Distribution NetworkDesign ToolPower Route GND and VCC as planes Route VCCIO for memories in a single split plane with at least a 20-mil( inches, or mm) gap of separation Route VTT as islands or 250-mil ( ) power traces Route oscillators and PLL power as islands or 100-mil ( ) power tracesGeneral RoutingAll specified delay matching requirements include PCB trace delays, different layerpropagation velocity variance, and crosstalk. To minimize PCB layer propogationvariance, Intel recommends that signals from the same net group always berouted on the same layer. Use 45 angles (not 90 corners) Avoid T-Junctions for critical nets or clocks Avoid T-junctions greater than 250 mils ( mm) Disallow signals across split planes Restrict routing other signals close to system reset signals Avoid routing memory signals closer than inch ( mm) to PCI orsystem clocksRelated LinksPower Distribution QDR II Layout GuidelinesThe following table summarizes QDR II and QDR II SRAM general routing : 1. The following layout guidelines include several +/- length based rules. Theselength based guidelines are for first order timing approximations if you cannotsimulate the actual delay characteristics of your PCB implementation. They do notinclude any margin for Intel recommends that you get accurate time base skew numbers when yousimulate your specific To reliably close timing to and from the periphery of the device, signals to andfrom the periphery should be registered before any further logic is Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide285Table II and QDR II+ SRAM Layout GuidelinesParameterGuidelinesGeneral Routing If signals of the same net group must be routed on different layers with the sameimpedance characteristic, you must simulate your worst case PCB trace tolerances toascertain actual propagation delay differences. Typical later to later trace delay variationsare of 15 ps/inch order. Avoid T-junctions greater than 150 Routing Route clocks on inner layers with outer-layer run lengths held to under 150 ps. These signals should maintain a 10-mil ( mm) spacing from other nets. Clocks should maintain a length-matching between clock pairs of 5 ps. Complementary clocks should maintain a length-matching between P and N signals of 2 ps. Keep the distance from the pin on the QDR II SRAM component to stub terminationresistor (VTT) to less than 50 ps for the K, K# clocks. Keep the distance from the pin on the QDR II SRAM component to fly-by terminationresistor (VTT) to less than 100 ps for the K, K# clocks. Keep the distance from the pin on the FPGA component to stub termination resistor (VTT)to less than 50 ps for the echo clocks, CQ, CQ#, if they require an external discretetermination. Keep the distance from the pin on the FPGA component to fly-by termination resistor(VTT) to less than 100 ps for the echo clocks, CQ, CQ#, if they require an externaldiscrete Memory RoutingRules Keep the distance from the pin on the QDR II SRAM component to stub terminationresistor (VTT) to less than 50 ps for the write data, byte write select and address/command signal groups. Keep the distance from the pin on the QDR II SRAM component to fly-by terminationresistor (VTT) to less than 100 ps for the write data, byte write select and address/command signal groups. Keep the distance from the pin on the FPGA to stub termination resistor (VTT) to lessthan 50 ps for the read data signal group. Keep the distance from the pin on the FPGA to fly-by termination resistor (VTT) to lessthan 100 ps for the read data signal group. Parallelism rules for the QDR II SRAM data/address/command groups are as follows: 4 mils for parallel runs < inch (approximately 1 spacing relative to planedistance). 5 mils for parallel runs < inch (approximately 1 spacing relative to planedistance). 10 mils for parallel runs between and inches (approximately 2 spacingrelative to plane distance). 15 mils for parallel runs between and inch (approximately 3 spacing relativeto plane distance).Maximum Trace Length Keep the maximum trace length of all signals from the FPGA to the QDR II SRAMcomponents to 6 LinksPower Distribution QDR II SRAM Layout ApproachUsing the layout guidelines in the above table, Intel recommends the following layoutapproach:7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User the K/K# clocks and set the clocks as the target trace propagation delaysfor the output signal the write data output signal group (write data, byte write select),ideally on the same layer as the K/K# clocks, to within 10 ps skew of the K/K# the address/control output signal group (address, RPS, WPS), ideally onthe same layer as the K/K# clocks, to within 20 ps skew of the K/K# the CQ/CQ# clocks and set the clocks as the target trace propagation delaysfor the input signal the read data output signal group (read data), ideally on the same layeras the CQ/CQ# clocks, to within 10 ps skew of the CQ/CQ# The output and input groups do not need to have the same propagation delays,but they must have all the signals matched closely within the respective : Intel recommends that you create your project with a fully implemented externalmemory interface, and observe the interface timing margins to determine the actualmargins for your the recommendations in this section are based on simulations, you can applythe same general principles when determining the best termination scheme, drivestrength setting, and loading style to any board designs. Even armed with thisknowledge, it is still critical that you perform simulations, either using IBIS or HSPICEmodels, to determine the quality of signal integrity on your Package DeskewYou should follow Intel's package deskew LinksPackage Deskew7 Intel Stratix 10 EMIF IP for QDR II/II+/II+ XtremeUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide2878 Intel Stratix 10 EMIF IP for QDR-IVThis chapter contains IP parameter descriptions, board skew equations, pin planninginformation, and board design guidance for Intel Stratix 10 external memoryinterfaces for Parameter DescriptionsThe following topics describe the parameters available on each tab of the IP parametereditor, which you can use to configure your Intel Stratix 10 EMIF IP QDR-IV Parameters: GeneralTable : General / InterfaceDisplay NameDescriptionConfigurationSpecifies the configuration of the memory interface. The available optionsdepend on the protocol in use. Options include Hard PHY and HardController, Hard PHY and Soft Controller, or Hard PHY only. If youselect Hard PHY only, the AFI interface is exported to allow connection ofa custom memory controller or third-party IP. (Identifier:PHY_QDR4_CONFIG_ENUM)Table : General / ClocksDisplay NameDescriptionMemory clock frequencySpecifies the operating frequency of the memory interface in MHz. If youchange the memory frequency, you should update the memory latencyparameters on the Memory tab and the memory timing parameters on theMem Timing tab. (Identifier: PHY_QDR4_MEM_CLK_FREQ_MHZ)Use recommended PLL reference clockfrequencySpecifies that the PLL reference clock frequency is automatically calculatedfor best performance. If you want to specify a different PLL reference clockfrequency, uncheck the check box for this parameter. (Identifier:PHY_QDR4_DEFAULT_REF_CLK_FREQ)PLL reference clock frequencyThis parameter tells the IP what PLL reference clock frequency the user willsupply. Users must select a valid PLL reference clock frequency from thelist. The values in the list can change when the memory interface frequencychanges and/or the clock rate of user logic changes. It is recommended touse the fastest possible PLL reference clock frequency because it leads tobetter jitter performance. Selection is required only if the user does notcheck the "Use recommended PLL reference clock frequency" option.(Identifier: PHY_QDR4_USER_REF_CLK_FREQ_MHZ) UG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008RegisteredDisplay NameDescriptionPLL reference clock jitterSpecifies the peak-to-peak jitter on the PLL reference clock source. Theclock source of the PLL reference clock must meet or exceed the followingjitter requirements: 10ps peak to peak, or RMS at 1e-12 BER, at 1e-16 BER. (Identifier: PHY_QDR4_REF_CLK_JITTER_PS)Clock rate of user logicSpecifies the relationship between the user logic clock frequency and thememory clock frequency. For example, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz, a quarter-rate interfacemeans that the user logic in the FPGA runs at 200MHz. (Identifier:PHY_QDR4_RATE_ENUM)Core clocks sharingWhen a design contains multiple interfaces of the same protocol, rate,frequency, and PLL reference clock source, they can share a common set ofcore clock domains. By sharing core clock domains, they reduce clocknetwork usage and avoid clock synchronization logic between share core clocks, denote one of the interfaces as "Master", and theremaining interfaces as "Slave". In the RTL, connect theclks_sharing_master_out signal from the master interface to theclks_sharing_slave_in signal of all the slave master and slave interfaces still expose their own output clock ports inthe RTL (for example, emif_usr_clk, afi_clk), but the physical signalsare equivalent, hence it does not matter whether a clock port from a masteror a slave is used. As the combined width of all interfaces sharing the samecore clock increases, you may encounter timing closure difficulty fortransfers between the FPGA core and the periphery.(Identifier: PHY_QDR4_CORE_CLKS_SHARING_ENUM)Specify additional core clocks based onexisting PLLDisplays additional parameters allowing you to create additional outputclocks based on the existing PLL. This parameter provides an alternativeclock-generation mechanism for when your design exhaustsavailable PLL resources. The additional output clocks that you create canbe fed into the core. Clock signals created with this parameter aresynchronous to each other, but asynchronous to the memory interface coreclock domains (such as emif_usr_clk or afi_clk). You must followproper clock-domain-crossing techniques when transferring data betweenclock domains. (Identifier: PLL_ADD_EXTRA_CLKS)Table : General / Clocks / Additional Core ClocksDisplay NameDescriptionNumber of additional core clocksSpecifies the number of additional output clocks to create from the PLL.(Identifier: PLL_USER_NUM_OF_EXTRA_CLKS)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_0Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_1Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6)8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide289Table : General / Clocks / Additional Core Clocks / pll_extra_clk_2Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_3Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8) Intel Stratix 10 EMIF IP QDR-IV Parameters: MemoryTable : Memory / TopologyDisplay NameDescriptionDQ width per deviceSpecifies number of DQ pins per port per QDR IV device. Available widthsfor DQ are x18 and x36. (Identifier:MEM_QDR4_DQ_PER_PORT_PER_DEVICE)Enable width expansionIndicates whether to combine two memory devices to double the data buswidth. With two devices, the interface supports a width expansionconfiguration up to 72-bits. For width expansion configuration, the addressand control signals are routed to 2 devices. (Identifier:MEM_QDR4_WIDTH_EXPANDED)Address widthNumber of address pins. (Identifier: MEM_QDR4_ADDR_WIDTH)Memory TypeThe QDR-IV family includes two members:MEM_XP: QDR-IV Xtreme Performance (XP) with a Maximum ClockFrequency of 1066MHzMEM_HP: QDR-IV High Performance (HP) with a Maximum Clock Frequencyof 667MHz.(Identifier: MEM_QDR4_MEM_TYPE_ENUM)Table : Memory / Configuration Register SettingsDisplay NameDescriptionAddress bus inversionEnable address bus inversion. AINV are all active high at memory device.(Identifier: MEM_QDR4_ADDR_INV_ENA)Data bus inversionEnable data bus inversion for DQ pins. DINVA[1:0] and DINVB[1:0] are allactive high. When set to 1, the corresponding bus is inverted at memorydevice. If the data inversion feature is programmed to be OFF, then theDINVA/DINVB output bits will always be driven to 0. (Identifier:MEM_QDR4_DATA_INV_ENA)ODT (Clock)Determines the configuration register setting that controls the clock ODTsetting. (Identifier: MEM_QDR4_CK_ODT_MODE_ENUM)ODT (Address/Command)Determines the configuration register setting that controls the address/command ODT setting. (Identifier: MEM_QDR4_AC_ODT_MODE_ENUM) 8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide290Display NameDescriptionODT (Data)Determines the configuration register setting that controls the data ODTsetting. (Identifier: MEM_QDR4_DATA_ODT_MODE_ENUM)Output drive (pull-up)Determines the configuration register setting that controls the pull-upoutput drive setting. (Identifier:MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM)Output drive (pull-down)Determines the configuration register setting that controls the pull-downoutput drive setting. (Identifier:MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM) Intel Stratix 10 EMIF IP QDR-IV Parameters: ControllerTable : ControllerDisplay NameDescriptionAvalon InterfaceSelects the Avalon Interface through which the controller interacts with userlogic (Identifier: CTRL_QDR4_AVL_PROTOCOL_ENUM)Maximum Avalon-MM burst lengthSpecifies the maximum burst length on the Avalon-MM bus. This will beused to configure the FIFOs to be able to manage the maximum data core logic will be required for an increase in FIFO length.(Identifier: CTRL_QDR4_AVL_MAX_BURST_COUNT)Generate power-of-2 data bus widthsfor QsysIf enabled, the Avalon data bus width is rounded down to thenearest power-of-2. The width of the symbols within the data bus is alsorounded down to the nearest power-of-2. You should only enable this optionif you know you will be connecting the memory interface to Qsysinterconnect components that require the data bus and symbol width to bea power-of-2. If this option is enabled, you cannot utilize the fulldensity of the memory example, in x36 data width upon selecting this parameter, will definethe Avalon data bus to 256-bit. This will ignore the upper 4-bit of datawidth.(Identifier: CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS)Additional read-after-write turnaroundtimeSpecifies an additional number of idle memory cycles when switching thedata bus (of a single port) from a write to a read. (Identifier:CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC)Additional write-after-read turnaroundtimeSpecifies an additional number of idle memory cycles when switching thedata bus (of a single port) from a read to a write. (Identifier:CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC) Intel Stratix 10 EMIF IP QDR-IV Parameters: FPGA I/OYou should use Hyperlynx* or similar simulators to determine the best settings foryour board. Refer to the EMIF Simulation Guidance wiki page for Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide291Table : FPGA I/O / FPGA I/O SettingsDisplay NameDescriptionVoltageThe voltage level for the I/O pins driving the signals between the memorydevice and the FPGA memory interface. (Identifier:PHY_QDR4_IO_VOLTAGE)Periodic OCT re-calibrationSpecifies that the system periodically recalibrate on-chip termination (OCT)to minimize variations in termination value caused by changing operatingconditions (such as changes in temperature). By recalibrating OCT, I/Otiming margins are improved. When enabled, this parameter causes thePHY to halt user traffic about every seconds for about 1900 memoryclock cycles, to perform OCT recalibration. Efficiency is reduced byabout 1% when this option is enabled. (Identifier:PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM)Use default I/O settingsSpecifies that a legal set of I/O settings are automatically selected. Thedefault I/O settings are not necessarily optimized for a specific board. Toachieve optimal signal integrity, perform I/O simulations with IBIS modelsand enter the I/O settings manually, based on simulation results.(Identifier: PHY_QDR4_DEFAULT_IO)Table : FPGA I/O / FPGA I/O Settings / Address/CommandDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the address/command pins of thememory interface. The selected I/O standard configures the circuit withinthe I/O buffer to match the industry standard. (Identifier:PHY_QDR4_USER_AC_IO_STD_ENUM)Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_QDR4_USER_AC_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_QDR4_USER_AC_SLEW_RATE_ENUM)Table : FPGA I/O / FPGA I/O Settings / Memory ClockDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the memory clock pins. Theselected I/O standard configures the circuit within the I/O buffer to matchthe industry standard. (Identifier: PHY_QDR4_USER_CK_IO_STD_ENUM)Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_QDR4_USER_CK_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_QDR4_USER_CK_SLEW_RATE_ENUM)8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide292Table : FPGA I/O / FPGA I/O Settings / Data BusDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the data and data clock/strobe pinsof the memory interface. The selected I/O standard option configures thecircuit within the I/O buffer to match the industry standard. (Identifier:PHY_QDR4_USER_DATA_IO_STD_ENUM)Output modeThis parameter allows you to change the output current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_QDR4_USER_DATA_OUT_MODE_ENUM)Input modeThis parameter allows you to change the input termination settings for theselected I/O standard. Perform board simulation with IBIS models todetermine the best settings for your design. (Identifier:PHY_QDR4_USER_DATA_IN_MODE_ENUM)Use recommended initial VrefinSpecifies that the initial Vrefin setting is calculated automatically, to areasonable value based on termination settings. (Identifier:PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN)Initial VrefinSpecifies the initial value for the reference voltage on the datapins(Vrefin). This value is entered as a percentage of the supply voltagelevel on the I/O pins. The specified value serves as a starting point and maybe overridden by calibration to provide better timing margins. If you chooseto skip Vref calibration (Diagnostics tab), this is the value that is usedas the Vref for the interface. (Identifier:PHY_QDR4_USER_STARTING_VREFIN)Table : FPGA I/O / FPGA I/O Settings / PHY InputsDisplay NameDescriptionPLL reference clock I/O standardSpecifies the I/O standard for the PLL reference clock of the memoryinterface. (Identifier: PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM)RZQ I/O standardSpecifies the I/O standard for the RZQ pin used in the memory interface.(Identifier: PHY_QDR4_USER_RZQ_IO_STD_ENUM) Intel Stratix 10 EMIF IP QDR-IV Parameters: Mem TimingThese parameters should be read from the table in the datasheet associated with thespeed bin of the memory device (not necessarily the frequency at which the interfaceis running).Table : Mem TimingDisplay NameDescriptionSpeed binThe speed grade of the memory device used. This parameter refers to themaximum rate at which the memory device is specified to run. (Identifier:MEM_QDR4_SPEEDBIN_ENUM)tISHtISH provides the setup/hold window requirement for the entire databus (DK or DINV) in all the data groups with respect to the DKclock. After deskew calibration, this parameter describes the intersectionwindow for all the individual data bus signals setup/hold margins.(Identifier: MEM_QDR4_TISH_PS)tQKQ_maxtQKQ_max describes the maximum skew between the read strobe (QK)clock edge to the data bus (DQ/DINV) edge. (Identifier:MEM_QDR4_TQKQ_MAX_PS)tQHtQH specifies the output hold time for the DQ/DINV in relation to QK.(Identifier: MEM_QDR4_TQH_CYC) 8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide293Display NameDescriptiontCKDK_maxtCKDK_max refers to the maximum skew from the memory clock (CK)to the write strobe (DK). (Identifier: MEM_QDR4_TCKDK_MAX_PS)tCKDK_mintCKDK_min refers to the minimum skew from the memory clock (CK) tothe write strobe (DK). (Identifier: MEM_QDR4_TCKDK_MIN_PS)tCKQK_maxtCKQK_max refers to the maximum skew from the memory clock (CK)to the read strobe (QK). (Identifier: MEM_QDR4_TCKQK_MAX_PS)tASHtASH provides the setup/hold window requirement for the addressbus in relation to the CK clock. Because the individual signals in theaddress bus may not be perfectly aligned with each other, this parameterdescribes the intersection window for all the individual address signalssetup/hold margins. (Identifier: MEM_QDR4_TASH_PS)tCSHtCSH provides the setup/hold window requirement for the controlbus (LD#, RW#) in relation to the CK clock. Because the individualsignals in the control bus may not be perfectly aligned with each other, thisparameter describes the intersection window for all the individual controlsignals setup/hold margins. (Identifier: MEM_QDR4_TCSH_PS) Intel Stratix 10 EMIF IP QDR-IV Parameters: BoardTable : Board / Intersymbol Interference/CrosstalkDisplay NameDescriptionUse default ISI/crosstalk valuesYou can enable this option to use default intersymbol interference andcrosstalk values for your topology. Note that the default values are notoptimized for your board. For optimal signal integrity, it is recommendedthat you do not enable this parameter, but instead perform I/O simulationusing IBIS models and Hyperlynx*, and manually enter values based onyour simulation results, instead of using the default values. (Identifier:BOARD_QDR4_USE_DEFAULT_ISI_VALUES)Address and command ISI/crosstalkThe address and command window reduction due to ISI and crosstalkeffects. The number to be entered is the total loss of margin on thesetup and hold sides (measured loss on the setup side + measuredloss on the hold side). Refer to the EMIF Simulation Guidance wiki pagefor additional information. (Identifier: BOARD_QDR4_USER_AC_ISI_NS)QK/QK# ISI/crosstalkQK/QK# ISI/crosstalk describes the reduction of the read data window dueto intersymbol interference and crosstalk effects on the QK/QK# signalwhen driven by the memory device during a read. The number to beentered in the Quartus Prime software is the total loss of margin on thesetup and hold sides (measured loss on the setup side + measuredloss on the hold side). Refer to the EMIF Simulation Guidance wiki pagefor additional information. (Identifier: BOARD_QDR4_USER_RCLK_ISI_NS)Read DQ ISI/crosstalkThe reduction of the read data window due to ISI and crosstalk effects onthe DQ signal when driven by the memory device during a read. Thenumber to be entered is the total loss of margin on the setup and holdsides (measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_QDR4_USER_RDATA_ISI_NS)DK/DK# ISI/crosstalkDK/DK# ISI/crosstalk describes the reduction of the write data window dueto intersymbol interference and crosstalk effects on the DK/DK# signalwhen driven by the FPGA during a write. The number to be entered is thetotal loss of margin on the setup and hold sides (measured loss 8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide294Display NameDescriptionthe setup side + measured loss on the hold side). Refer to the EMIFSimulation Guidance wiki page for additional information. (Identifier:BOARD_QDR4_USER_WCLK_ISI_NS)Write DQ ISI/crosstalkThe reduction of the write data window due to intersymbol interference andcrosstalk effects on the DQ signal when driven by the FPGA during a number to be entered is the total loss of margin on the setup andhold sides (measured loss on the setup side + measured loss on thehold side). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_QDR4_USER_WDATA_ISI_NS)Table : Board / Board and Package SkewsDisplay NameDescriptionPackage deskewed with board layout(QK group)If you are compensating for package skew on the QK bus in the boardlayout (hence checking the box here), please include package skew incalculating the following board skew parameters. (Identifier:BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED)Maximum board skew within QK groupThe largest skew between all DQ and DM pins in a QK group. Enter yourboard skew only. Package skew will be calculated automatically, based onthe memory interface configuration, and added to this value. This valueaffects the read capture and write margins. (Identifier:BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS)Maximum system skew within QK groupMaximum system skew within QK group refers to the largest skew betweenall DQ and DM pins in a QK group. This value can affect the read captureand write margins. (Identifier:BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS)Package deskewed with board layout(address/command bus)Enable this parameter if you are compensating for package skew on theaddress, command, control, and memory clock buses in the board package skew in calculating the following board skewparameters. (Identifier:BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED)Maximum board skew within address/command busThe largest skew between the address and command signals. Enter theboard skew only; package skew is calculated automatically, based on thememory interface configuration, and added to this value. (Identifier:BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS)Maximum system skew within address/command busMaximum system skew within address/command bus refers to the largestskew between the address and command signals. (Identifier:BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS)Average delay difference between DKand CKThis parameter describes the average delay difference between the DKsignals and the CK signal, calculated by averaging the longest and smallestDK trace delay minus the CK trace delay. Positive values represent DKsignals that are longer than CK signals and negative values represent DKsignals that are shorter than CK signals. (Identifier:BOARD_QDR4_DK_TO_CK_SKEW_NS)Maximum delay difference betweendevicesThis parameter describes the largest propagation delay on the DQ signalsbetween example, in a two-rank configuration where devices are placed in series,there is an extra propagation delay for DQ signals going to and coming backfrom the furthest device compared to the nearest device. This parameter isonly applicable when there is more than one rank.(Identifier: BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS)Maximum skew between DK groupsThis parameter describes the largest skew between DK signals in differentDK groups. (Identifier: BOARD_QDR4_SKEW_BETWEEN_DK_NS)Average delay difference betweenaddress/command and CKThe average delay difference between the address/command signals andthe CK signal, calculated by averaging the longest and smallest address/command signal trace delay minus the maximum CK trace delay. Positivevalues represent address and command signals that are longer than 8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide295Display NameDescriptionsignals and negative values represent address and command signals thatare shorter than CK signals. (Identifier:BOARD_QDR4_AC_TO_CK_SKEW_NS)Maximum CK delay to deviceThe maximum CK delay to device refers to the delay of the longest CK tracefrom the FPGA to any device. (Identifier:BOARD_QDR4_MAX_CK_DELAY_NS)Maximum DK delay to deviceThe maximum DK delay to device refers to the delay of the longest DKtrace from the FPGA to any device. (Identifier:BOARD_QDR4_MAX_DK_DELAY_NS) Intel Stratix 10 EMIF IP QDR-IV Parameters: DiagnosticsTable : Diagnostics / Simulation OptionsDisplay NameDescriptionCalibration modeSpecifies whether to skip memory interface calibration duringsimulation, or to simulate the full calibration the full calibration process can take hours (or even days),depending on the width and depth of the memory interface. You canachieve much faster simulation times by skipping the calibration process,but that is only expected to work when the memory model is ideal and theinterconnect delays are you enable this parameter, the interface still performs some memoryinitialization before starting normal operations. Abstract PHY is supportedwith skip calibration.(Identifier: DIAG_QDR4_SIM_CAL_MODE_ENUM)Abstract phy for fast simulationSpecifies that the system use Abstract PHY for simulation. Abstract PHYreplaces the PHY with a model for fast simulation and can reducesimulation time by 2-3 times. Abstract PHY is available for certainprotocols and device families, and only when you select Skip Calibration.(Identifier: DIAG_QDR4_ABSTRACT_PHY)Table : Diagnostics / Calibration Debug OptionsDisplay NameDescriptionQuartus Prime EMIF Debug Toolkit/On-Chip Debug PortSpecifies the connectivity of an Avalon slave interface for use by theQuartus Prime EMIF Debug Toolkit or user core you set this parameter to "Disabled", no debug features are enabled. Ifyou set this parameter to "Export", an Avalon slave interface named"cal_debug" is exported from the IP. To use this interface with the EMIFDebug Toolkit, you must instantiate and connect an EMIF debug interface IPcore to it, or connect it to the cal_debug_out interface of another EMIFcore. If you select "Add EMIF Debug Interface", an EMIF debug interfacecomponent containing a JTAG Avalon Master is connected to the debug port,allowing the core to be accessed by the EMIF Debug one EMIF debug interface should be instantiated per I/O column. Youcan chain additional EMIF or PHYLite cores to the first by enabling the"Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option for all cores in the chain, and selecting "Export"for the "Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port"option on all cores after the first.(Identifier: DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE)Enable Daisy-Chaining for QuartusPrime EMIF Debug Toolkit/On-ChipDebug PortSpecifies that the IP export an Avalon-MM master interface(cal_debug_out) which can connect to the cal_debug interface of otherEMIF cores residing in the same I/O column. This parameter applies onlyif the EMIF Debug Toolkit or On-Chip Debug Port is enabled. Refer 8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide296Display NameDescriptionthe Debugging Multiple EMIFs wiki page for more information aboutdebugging multiple EMIFs. (Identifier:DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER)Interface IDIdentifies interfaces within the I/O column, for use by the EMIF DebugToolkit and the On-Chip Debug Port. Interface IDs should be unique amongEMIF cores within the same I/O column. If the Quartus Prime EMIFDebug Toolkit/On-Chip Debug Port parameter is set to Disabled, theinterface ID is unused. (Identifier: DIAG_QDR4_INTERFACE_ID)Skip VREF_in calibrationSpecifies to skip the VREF stage of calibration. Enable this parameter fordebug purposes only; generally, you should include the VREF calibrationstage during normal operation. (Identifier: DIAG_QDR4_SKIP_VREF_CAL)Use Soft NIOS Processor for On-ChipDebugEnables a soft Nios processor as a peripheral component to access the On-Chip Debug Port. Only one interface in a column can activate this option.(Identifier: DIAG_SOFT_NIOS_MODE)Table : Diagnostics / Example DesignDisplay NameDescriptionNumber of core clocks sharing slaves toinstantiate in the example designSpecifies the number of core clock sharing slaves to instantiate in theexample design. This parameter applies only if you set the "Core clockssharing" parameter in the "General" tab to "Master" or "Slave".(Identifier: DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES)Enable In-System-Sources-and-ProbesEnables In-System-Sources-and-Probes in the example design for commondebug signals, such as calibration status or example traffic generator per-bit status. This parameter must be enabled if you want to do drivermargining. (Identifier: DIAG_QDR4_EX_DESIGN_ISSP_EN)Table : Diagnostics / Traffic GeneratorDisplay NameDescriptionUse configurable Avalon trafficgenerator option allows users to add the new configurable Avalon trafficgenerator to the example design. (Identifier: DIAG_QDR4_USE_TG_AVL_2)Bypass the default traffic patternSpecifies that the controller/interface bypass the traffic generator pattern after reset. If you do not enable this parameter, the trafficgenerator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_QDR4_BYPASS_DEFAULT_PATTERN)Bypass the user-configured traffic stageSpecifies that the controller/interface bypass the user-configured trafficgenerator's pattern after reset. If you do not enable this parameter, thetraffic generator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration can be done by connecting to the traffic generator via theEMIF Debug Toolkit, or by using custom logic connected to the Avalon-MMconfiguration slave port on the traffic generator. Configuration can also besimulated using the example testbench provided in file.(Identifier: DIAG_QDR4_BYPASS_USER_STAGE)Bypass the traffic generator repeated-writes/repeated-reads test patternSpecifies that the controller/interface bypass the traffic generator's repeattest stage. If you do not enable this parameter, every write and read isrepeated several times. (Identifier: DIAG_QDR4_BYPASS_REPEAT_STAGE)Bypass the traffic generator stresspatternSpecifies that the controller/interface bypass the traffic generator's stresspattern stage. (Stress patterns are meant to create worst-case signalintegrity patterns on the data pins.) If you do not enable this parameter, 8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide297Display NameDescriptionthe traffic generator does not assert a pass or fail status until the generatoris configured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_QDR4_BYPASS_STRESS_STAGE)Export Traffic Generator interfaceSpecifies that the IP export an Avalon-MM slave port for configuring theTraffic Generator. This is required only if you are configuring the trafficgenerator through user logic and not through through the EMIF DebugToolkit. (Identifier: DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE)Table : Diagnostics / PerformanceDisplay NameDescriptionEnable Efficiency MonitorAdds an Efficiency Monitor component to the Avalon-MM interface of thememory controller, allowing you to view efficiency statistics of the can access the efficiency statistics using the EMIF Debug Toolkit.(Identifier: DIAG_QDR4_EFFICIENCY_MONITOR)Table : Diagnostics / MiscellaneousDisplay NameDescriptionUse short Qsys interface namesSpecifies the use of short interface names, for improved usability andconsistency with other Qsys components. If this parameter is disabled, thenames of Qsys interfaces exposed by the IP will include the type anddirection of the interface. Long interface names are supported forbackward-compatibility and will be removed in a future release. (Identifier:SHORT_QSYS_INTERFACE_NAMES) Intel Stratix 10 EMIF IP QDR-IV Parameters: Example DesignsTable : Example Designs / Available Example DesignsDisplay NameDescriptionSelect designSpecifies the creation of a full Quartus Prime project, instantiating anexternal memory interface and an example traffic generator, according toyour parameterization. After the design is created, you can specify thetarget device and pin location assignments, run a full compilation, verifytiming closure, and test the interface on your board using the programmingfile created by the Quartus Prime assembler. The 'Generate ExampleDesign' button lets you generate simulation or synthesis file sets.(Identifier: EX_DESIGN_GUI_QDR4_SEL_DESIGN)Table : Example Designs / Example Design FilesDisplay NameDescriptionSimulationSpecifies that the 'Generate Example Design' button create all necessaryfile sets for simulation. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, simulation file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the simulation example design, and file with other corresponding tcl files. You canrun from a command line to generate 8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide298Display NameDescriptionsimulation example design. The generated example designs for varioussimulators are stored in the /sim sub-directory. (Identifier:EX_DESIGN_GUI_QDR4_GEN_SIM)SynthesisSpecifies that the 'Generate Example Design' button create all necessaryfile sets for synthesis. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, synthesis file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the synthesis example design, and script with other corresponding tcl files. You canrun from a command line to generate thesynthesis example design. The generated example design is stored inthe /qii sub-directory. (Identifier: EX_DESIGN_GUI_QDR4_GEN_SYNTH)Table : Example Designs / Generated HDL FormatDisplay NameDescriptionSimulation HDL formatThis option lets you choose the format of HDL in which generatedsimulation files are created. (Identifier:EX_DESIGN_GUI_QDR4_HDL_FORMAT)Table : Example Designs / Target Development KitDisplay NameDescriptionSelect boardSpecifies that when you select a development kit with a memory module,the generated example design contains all settings and fixed pinassignments to run on the selected board. You must select a developmentkit preset to generate a working example design for the specifieddevelopment kit. Any IP settings not applied directly from a developmentkit preset will not have guaranteed results when testing the developmentkit. To exclude hardware support of the example design, select 'none' fromthe 'Select board' pull down menu. When you apply a development kitpreset, all IP parameters are automatically set appropriately to match theselected preset. If you want to save your current settings, you should do sobefore you apply the preset. You can save your settings under a differentname using File->Save as. (Identifier:EX_DESIGN_GUI_QDR4_TARGET_DE V_KIT) Board Skew EquationsThe following table presents the underlying equations for the board skew Equations for QDR-IV Board Skew ParametersTable Skew Parameter EquationsParameterDescription/EquationMa ximum system skewwithin address/commandbusThe largest skew between the address and command signals. Enter combined board andpackage 8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide299ParameterDescription/EquationMax AC MinACAverage delay differencebetween address/commandand CKThe average delay difference between the address and command signals and the CK signal,calculated by averaging the longest and smallest Address/Command signal delay minus theCK delay. Positive values represent address and command signals that are longer than CKsignals and negative values represent address and command signals that are shorter thanCK signals. The Quartus Prime software uses this skew to optimize the delay of the addressand command signals to have appropriate setup and hold margins. n=nn= 1LongestACPathDelay+ShortestACPathDelay2 CKnPathDelaynwhere n is the number of memory System skewwithin QK groupThe largest skew between all DQ and DM pins in a QK group. Enter combined board andpackage skew. This value affects the read capture and write minDQnWhere n includes both DQa and DQbMaximum CK delay to deviceThe delay of the longest CK trace from the FPGA to any n is the number of memory DK delay to deviceThe delay of the longest DK trace from the FPGA to any n is the number of delay differencebetween DK and CKThe average delay difference between the DK signals and the CK signal, calculated byaveraging the longest and smallest DK delay minus the CK delay. Positive values representDK signals that are longer than CK signals and negative values represent DK signals thatare shorter than CK signals. The Quartus Prime software uses this skew to optimize thedelay of the DK signals to have appropriate setup and hold ,mCKnPathDelay DKmPathDelay+ maxn,mCKnPathDelay DKmPathDelay2CDO:/content/ n is the number of memory clocksand m is the number of skew between DKgroupsThe largest skew between DK signals in different DK minDKnwhere n is the number of DK. Where n includes both DQa and Pin and Resource PlanningThe following topics provide guidelines on pin placement for external , all external memory interfaces require the following FPGA resources: Interface pins PLL and clock network Other FPGA resources for example, core fabric logic, and on-chip termination(OCT) calibration blocksOnce all the requirements are known for your external memory interface, you canbegin planning your Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Interface PinsAny I/O banks that do not support transceiver operations in Intel Stratix 10 devicessupport external memory interfaces. However, DQS (data strobe or data clock) andDQ (data) pins are listed in the device pin tables and are fixed at specific locations inthe device. You must adhere to these pin locations to optimize routing, minimize skew,and maximize margins. Always check the pin table for the actual locations of the DQSand DQ : Maximum interface width varies from device to device depending on the number ofI/O pins and DQS or DQ groups available. Achievable interface width also depends onthe number of address and command pins that the design requires. To ensureadequate PLL, clock, and device routing resources are available, you should alwaystest fit any IP in the Intel Quartus Prime Prime software before PCB devices do not limit the width of external memory interfaces beyond thefollowing requirements: Maximum possible interface width in any particular device is limited by thenumber of DQS groups available. Sufficient clock networks are available to the interface PLL as required by the IP. Sufficient spare pins exist within the chosen bank or side of the device to includeall other address and command, and clock pin placement requirements. The greater the number of banks, the greater the skew, hence Intel recommendsthat you always generate a test project of your desired configuration and confirmthat it meets Estimating Pin RequirementsYou should use the Intel Quartus Prime software for final pin fitting. However, you canestimate whether you have enough pins for your memory interface using the EMIFDevice Selector on , or perform the following steps:1. Determine how many read/write data pins are associated per data strobe or Calculate the number of other memory interface pins needed, including any otherclocks (write clock or memory system clock), address, command, and RZQ. Referto the External Memory Interface Pin Table to determine necessary Address/Command/Clock pins based on your desired Calculate the total number of I/O banks required to implement the memoryinterface, given that an I/O bank supports up to 48 GPIO should test the proposed pin-outs with the rest of your design in the Intel QuartusPrime software (with the correct I/O standard and OCT connections) before finalizingthe pin-outs. There can be interactions between modules that are illegal in the IntelQuartus Prime software that you might not know about unless you compile the designand use the Intel Quartus Prime Pin LinksExternal Memory Interfaces Support Center8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Maximum Number of InterfacesThe maximum number of interfaces supported for a given memory protocol varies,depending on the FPGA in otherwise noted, the calculation for the maximum number of interfaces isbased on independent interfaces where the address or command pins are not : You may need to share PLL clock outputs depending on your clock network interface information for Intel Stratix 10, consult the EMIF Device Selector closure depends on device resource and routing utilization. For moreinformation about timing closure, refer to the Area and Timing OptimizationTechniques chapter in the Intel Quartus Prime Links External Memory Interfaces Support Center Intel Stratix 10 EMIF Architecture: PLL Reference Clock Networks on page 20 External Memory Interface Device Selector Intel Quartus Prime Pro Edition FPGA ResourcesThe Intel FPGA memory interface IP uses FPGA fabric, including registers and theMemory Block to implement the memory OCT calibration block is used if you are using the FPGA OCT feature in thememory interface. The OCT calibration block uses a single pin (RZQ). You can selectany of the available OCT calibration block as you do not need to place this block in thesame bank or device side of your memory interface. The only requirement is that theI/O bank where you place the OCT calibration block uses the same VCCIO voltage asthe memory interface. You can share multiple memory interfaces with the same OCTcalibration block if the VCCIO voltage is the OCTIf the memory interface uses any FPGA OCT calibrated series, parallel, or dynamictermination for any I/O in your design, you need a calibration block for the OCTcircuitry. This calibration block is not required to be within the same bank or side ofthe device as the memory interface RZQ pin in Intel Stratix 10 devices can be used as a general purpose I/O pin whenit is not used to support OCT, provided the signal conforms to the bank PLLWhen using PLL for external memory interfaces, you must consider the followingguidelines:8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide302 For the clock source, use the clock input pin specifically dedicated to the PLL thatyou want to use with your external memory interface. The input and output pinsare only fully compensated when you use the dedicated PLL clock input pin. If theclock source for the PLL is not a dedicated clock input pin for the dedicated PLL,you would need an additional clock network to connect the clock source to the PLLblock. Using additional clock network may increase clock jitter and degrade thetiming margin. Pick a PLL and PLL input clock pin that are located on the same side of the deviceas the memory interface pins. Share the DLL and PLL static clocks for multiple memory interfaces provided thecontrollers are on the same or adjacent side of the device and run at the samememory clock frequency. If your design uses a dedicated PLL to only generate a DLL input reference clock,you must set the PLL mode to No Compensation in the Intel Quartus Primesoftware to minimize the jitter, or the software forces this setting PLL does not generate other output, so it does not need to compensate forany clock Pin Guidelines for Intel Stratix 10 EMIF IPThe Intel Stratix 10 device contains up to three I/O columns that can be used byexternal memory Intel Stratix 10 I/O subsystem resides in the I/Ocolumns. Each column contains multiple I/O banks, each of which consists of four I/Olanes. An I/O lane is a group of twelve I/O I/O column, I/O bank, I/O lane, adjacent I/O bank, and pairing pin for everyphysical I/O pin can be uniquely identified using the Bank Number and Indexwithin I/O Bank values which are defined in each Intel Stratix 10 device pin-outfile. The numeric component of the Bank Number value identifies the I/O column,while the letter represents the I/O bank. The Index within I/O Bank value falls within one of the following ranges: 0 to11, 12 to 23, 24 to 35, or 36 to 47, and represents I/O lanes 1, 2, 3, and 4,respectively. The adjacent I/O bank is defined as the I/O bank with same column number butthe letter is either before or after the respective I/O bank letter in the A-Z system. The pairing pin for an I/O pin is located in the same I/O bank. You can identify thepairing pin by adding one to its Index within I/O Bank number (if it is aneven number), or by subtracting one from its Index within I/O Bank number(if it is an odd number).For example, a physical pin with a Bank Number of 2M and Index within I/OBank of 22, indicates that the pin resides in I/O lane 2, in I/O bank 2M, in column adjacent I/O banks are 2L and 2N. The pairing pin for this physical pin is the pinwith an Index within I/O Bank of 23 and Bank Number of General GuidelinesYou should follow the recommended guidelines when performing pin placement for allexternal memory interface pins targeting Intel Stratix 10 devices, whether you areusing the hard memory controller or your own Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide303If you are using the hard memory controller, you should employ the relative pinlocations defined in the <variation_name>/altera_emif_arch_nd_versionnumber/<synth|sim>/<variation_name>_altera_emif_arch_nd_versionnumber_<unique ID> file, w+ted with your : 1. EMIF IP pin-out requirements for the Intel Stratix 10 Hard Processor Subsystem(HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IPdefines a fixed pin-out in the Intel Quartus Prime IP file (.qip), based on the IPconfiguration. When targeting Intel Stratix 10 HPS, you do not need to makelocation assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the IntelQuartus Prime software. Alternatively, consult the device handbook or the devicepin-out files. For information on how you can customize the HPS EMIF pin-out,refer to Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP with Ping Pong PHY, PHY only, RLDRAMx , QDRx and LPDDR3 are not supported the following general guidelines when placing pins for your Intel Stratix 10external memory interface:1. Ensure that the pins of a single external memory interface reside within a singleI/O An external memory interface can occupy one or more banks in the same I/Ocolumn. When an interface must occupy multiple banks, ensure that those banksare adjacent to one Any pin in the same bank that is not used by an external memory interface isavailable for use as a general purpose I/O of compatible voltage and All address and command pins and their associated clock pins (CK and CK#) mustreside within a single bank. The bank containing the address and command pins isidentified as the address and command To minimize latency, when the interface uses more than two banks, you mustselect the center bank of the interface as the address and command The address and command pins and their associated clock pins in the address andcommand bank must follow a fixed pin-out scheme, as defined in the Intel Stratix10 External Memory Interface Pin Information File, which is available do not have to place every address and command pin manually. If you assignthe location for one address and command pin, the Fitter automatically places theremaining address and command : The pin-out scheme is a hardware requirement that you must follow, andcan vary according to the topology of the memory device. Some schemesrequire three lanes to implement address and command pins, while othersrequire four lanes. To determine which scheme to follow, refer to themessages window during parameterization of your IP, or to the<variation_name>/altera_emif_arch_nd_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nd_<version>_<uniqueID> file after you have generated your Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide3047. An unused I/O lane in the address and command bank can serve to implement adata group, such as a x8 DQS group. The data group must be from the samecontroller as the address and command An I/O lane must not be used by both address and command pins and data Place read data groups according to the DQS grouping in the pin table and PinPlanner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQand CQ# / QK and QK#) must reside at physical pins capable of functioning asDQS/CQ and DQSn/CQn for a specific read data group size. You must place theassociated read data pins (such as DQ and Q), within the same : other device families, there is no need to swap CQ/CQ# pins incertain QDR II and QDR II+ latency requires that the polarity of all QKB/QKB# pins be swapped withrespect to the polarity of the differential buffer inputs on the FPGA toensure correct data capture on port B. All QKB pins on the memorydevice must be connected to the negative pins of the input buffers onthe FPGA side, and all QKB# pins on the memory device must beconnected to the positive pins of the input buffers on the FPGA that the port names at the top-level of the IP already reflect thisswap (that is, mem_qkb is assigned to the negative buffer leg, andmem_qkb_n is assigned to the positive buffer leg).10. You can implement two x4 DQS groups with a single I/O lane. The pin tablespecifies which pins within an I/O lane can be used for the two pairs of DQS andDQS# signals. In addition, for x4 DQS groups you must observe the followingrules: There must be an even number of x4 groups in an external memory interface. DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly,DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS groupX and DQS group X+1 must be in the same I/O lane, where X is an You should place the write data groups according to the DQS grouping in the pintable and Pin Planner. Output-only data clocks for QDR II, QDR II+, and QDR II+Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, butmust be placed on a differential pin pair. They must be placed in the same I/Obank as the corresponding DQS : For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced toDK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.12. For protocols and topologies with bidirectional data pins where a write data groupconsists of multiple read data groups, you should place the data groups and theirrespective write and read clock in the same bank to improve I/O do not need to specify the location of every data pin manually. If you assignthe location for the read capture strobe/clock pin pairs, the Fitter willautomatically place the remaining data Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/Opin and another in the pairing pin for that I/O pin. It is recommended though notrequired that you follow the same rule for DBI pins, so that at a later date youhave the freedom to repurpose the pin as Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide305Note: 1. x4 mode does not support DM/DBI, or Intel Stratix 10 EMIF IP for If you are using an Intel Stratix 10 EMIF IP-based RLDRAM 3 external memoryinterface, you should ensure that all the pins in a DQS group (that is, DQ, DM, DK,and QK) are placed in the same I/O bank. This requirement facilitates timingclosure and is necessary for successful compilation of your Interfaces in the Same I/O ColumnTo place multiple interfaces in the same I/O column, you must ensure that the globalreset signals (global_reset_n) for each individual interface all come from the sameinput pin or Banks Selection For each memory interface, select consecutive I/O banks. (That is, select banksthat contain the same column number and letter before or after the respective I/Obank letter.) A memory interface can only span across I/O banks in the same I/O column. The number of I/O banks that you require depends on the memory interfacewidth. In some device packages, the number of I/O pins in some LVDS I/O banks is lessthat 48 Pins Location All address/command pins for a controller must be in a single I/O bank. If your interface uses multiple I/O banks, the address/command pins must use themiddle bank. If the number of banks used by the interface is even, any of the twomiddle I/O banks can be used for address/command pins. Address/command pins and data pins cannot share an I/O lane but can share anI/O bank. The address/command pin locations for the soft and hard memory controllers arepredefined. In the External Memory Interface Pin Information for Devicesspreadsheet, each index in the "Index within I/O bank" column denotes adedicated address/command pin function for a given protocol. The index numberof the pin specifies to which I/O lane the pin belongs: I/O lane 0 Pins with index 0 to 11 I/O lane 1 Pins with index 12 to 23 I/O lane 2 Pins with index 24 to 35 I/O lane 3 Pins with index 36 to 47 For memory topologies and protocols that require only three I/O lanes for theaddress/command pins, use I/O lanes 0, 1, and 2. Unused address/command pins in an I/O lane can be used as general-purpose Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide306CK Pins AssignmentAssign the clock pin (CK pin) according to the number of I/O banks in an interface: If the number of I/O banks is odd, assign one CK pin to the middle I/O bank. If the number of I/O banks is even, assign the CK pin to either of the middle twoI/O the Fitter can automatically select the required I/O banks, Intel recommendsthat you make the selection manually to reduce the pre-fit run Reference Clock Pin PlacementPlace the PLL reference clock pin in the address/command bank. Other I/O banks maynot have free pins that you can use as the PLL reference clock pin: If you are sharing the PLL reference clock pin between several interfaces, the I/Obanks must be adjacent. (That is, the banks must contain the same columnnumber and letter before or after the respective I/O bank letter.)The Intel Stratix 10 external memory interface IP does not support PLL Pin PlacementYou may place the RZQ pin in any I/O bank in an I/O column with the correct VCCIO andVCCPT for the memory interface I/O standard in use. However, the recommendedlocation is in the address/command I/O bank, for greater flexibility during debug if anarrower interface project is required for and DQS Pins AssignmentIntel recommends that you assign the DQS pins to the remaining I/O lanes in the I/Obanks as required: Constrain the DQ and DQS signals of the same DQS group to the same I/O lane. You cannot constrain DQ signals from two different DQS groups to the same you do not specify the DQS pins assignment, the Fitter selects the DQS an I/O Bank Across Multiple InterfacesIf you are sharing an I/O bank across multiple external memory interfaces, followthese guidelines: The interfaces must use the same protocol, voltage, data rate, frequency, and PLLreference clock. You cannot use an I/O bank as the address/command bank for more than oneinterface. The memory controller and sequencer cannot be shared. You cannot share an I/O lane. There is only one DQS input per I/O lane, and anI/O lane can connect to only one memory Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User QDR IV SRAM Commands and Addresses, AP, and AINV SignalsThe CK and CK# signals clock the commands and addresses into the memory is one pair of CK and CK# pins per QDR IV SRAM device. These pins operate atdouble data rate using both rising and falling edge. The rising edge of CK latches theaddresses for port A, while the falling edge of CK latches the addresses inputs for IV SRAM devices have the ability to invert all address pins to reduce potentialsimultaneous switching noise. Such inversion is accomplished using the AddressInversion Pin for Address and Address Parity Inputs (AINV), whichassumes an address parity of 0, and indicates whether the address bus and addressparity are above features are available as Option Control under Configuration RegisterSettings in the parameter editor. The commands and addresses must meet thememory address and command setup (tAS, tCS) and hold (tAH, tCH) QDR IV SRAM Clock SignalsQDR IV SRAM devices have three pairs of differential three QDR IV differential clocks are as follows: Address and Command Input Clocks CK and CK# Data Input Clocks DKx and DKx#, where x can be A or B, referring to therespective ports Data Output Clocks, QKx and QKx#, where x can be A or B, referring to therespective portsQDR IV SRAM devices have two independent bidirectional data ports, Port A and PortB, to support concurrent read/write transactions on both ports. These data ports arecontrolled by a common address port clocked by CK and CK# in double data is one pair of CK and CK# pins per QDR IV SRAM and DKx# samples the DQx inputs on both rising and falling edges. Similarly, QKxand QKx# samples the DQx outputs on both rising and falling IV SRAM devices employ two sets of free running differential clocks toaccompany the data. The DKx and DKx# clocks are the differential input data clocksused during writes. The QKx and QKx# clocks are the output data clocks used duringreads. Each pair of DKx and DKx#, or QKx and QKx# clocks are associated with either9 or 18 data polarity of the QKB and QKB# pins in the Intel FPGA external memory interface IPwas swapped with respect to the polarity of the differential input buffer on the other words, the QKB pins on the memory side must be connected to the negativepins of the input buffers on the FPGA side, and the QKB# pins on the memory sidemust be connected to the positive pins of the input buffers on the FPGA side. Noticethat the port names at the top-level of the IP already reflect this swap (that is,mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to thepositive buffer leg).8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide308QDR IV SRAM devices are available in x18 and x36 bus width configurations. Theexact clock-data relationships are as follows: For 18 data bus width configuration, there are 9 data bits associated with eachpair of write and read clocks. So, there are two pairs of DKx and DKx# pins andtwo pairs of QKx or QKx# pins. For 36 data bus width configuration, there are 18 data bits associated with eachpair of write and read clocks. So, there are two pairs of DKx and DKx# pins andtwo pairs of QKx or QKx# are tCKDK timing requirements for skew between CK and DKx or CK# andDKx# .Similarly, there are tCKQK timing requirements for skew between CK and QKxor CK# and QKx# . QDR IV SRAM Data, DINV, and QVLD SignalsThe read data is edge-aligned with the QKA or QKB# clocks while the write data iscenter-aligned with the DKA and DKB# is shifted by the DLL so that the clock edges can be used to clock in the DQ at thecapture DQ and QK Relationship During ReadQK at FPGA PinDQ at FPGA PinQK at Capture RegisterDQ at CaptureRegisterFigure DQ and DK Relationship During WriteDK at FPGA PinDQ at FPGA PinThe polarity of the QKB and QKB# pins in the Intel FPGA external memory interface IPwas swapped with respect to the polarity of the differential input buffer on the other words, the QKB pins on the memory side need to be connected to thenegative pins of the input buffers on the FPGA side, and the QKB# pins on the memoryside need to be connected to the positive pins of the input buffers on the FPGA that the port names at the top-level of the IP already reflect this swap (that is,mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to thepositive buffer leg).8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide309The synchronous read/write input, RWx#, is used in conjunction with the synchronousload input, LDx#, to indicate a Read or Write Operation. For port A, these signals aresampled on the rising edge of CK clock, for port B, these signals are sampled on thefalling edge of CK IV SRAM devices have the ability to invert all data pins to reduce potentialsimultaneous switching noise, using the Data Inversion Pin for DQ Data Bus, pin indicates whether DQx pins are inverted or enable the data pin inversion feature, click Configuration Register Settings Option Control in the parameter IV SRAM devices also have a QVLD pin which indicates valid read data. The QVLDsignal is edge-aligned with QKx or QKx# and is high approximately one-half clock cyclebefore data is output from the : The Intel ZFPGA external memory interface IP does not use the QVLD Resource Sharing Guidelines (Multiple Interfaces)In Intel Cyclone 10Intel Stratix 10 external memory interface IP, different externalmemory interfaces can share PLL reference clock pins, core clock networks, I/O banks,and hard Nios processors. Each I/O bank has DLL and PLL resources, therefore thesedo not need to be shared. The Intel Quartus Prime Fitter automatically merges DLLand PLL resources when a bank is shared by different external memory interfaces, andduplicates them for a multi-I/O-bank external memory Reference Clock PinTo conserve pin usage and enable core clock network and I/O bank sharing, you canshare a PLL reference clock pin between multiple external memory interfaces; theinterfaces must be of the same protocol, rate, and frequency. Sharing of a PLLreference clock pin also implies sharing of the reference clock the following guidelines for sharing the PLL reference clock share a PLL reference clock pin, connect the same signal to the pll_ref_clkport of multiple external memory interfaces in the RTL Place related external memory interfaces in the same I/O Place related external memory interfaces in adjacent I/O banks. If you leave anunused I/O bank between the I/O banks used by the external memory interfaces,that I/O bank cannot be used by any other external memory interface with adifferent PLL reference clock : You can place the pll_ref_clk pin in the address and command I/O bank or in adata I/O bank, there is no impact on timing. However, for greatest flexibility duringdebug (such as when creating designs with narrower interfaces), the recommendedplacement is in the address and command I/O Clock NetworkTo access all external memory interfaces synchronously and to reduce global clocknetwork usage, you may share the same core clock network with other externalmemory Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide310Observe the following guidelines for sharing the core clock share a core clock network, connect the clks_sharing_master_out of themaster to the clks_sharing_slave_in of all slaves in the RTL Place related external memory interfaces in the same I/O Related external memory interface must have the same rate, memory clockfrequency, and PLL reference BankTo reduce I/O bank utilization, you may share an I/O Bank with other externalmemory the following guidelines for sharing an I/O Bank:1. Related external memory interfaces must have the same protocol, rate, memoryclock frequency, and PLL reference You cannot use a given I/O bank as the address and command bank for more thanone external memory You cannot share an I/O lane between external memory interfaces, but an unusedpin can serve as a general purpose I/O pin, of compatible voltage and Nios ProcessorAll external memory interfaces residing in the same I/O column will share the samehard Nios processor. The shared hard Nios processor calibrates the external memoryinterfaces QDR-IV Board Design GuidelinesThe following topics provide guidelines for you to improve your system's signalintegrity and layout guidelines to help successfully implement a QDR-IV SRAMinterface in your following topics focus on the following key factors that affect signal integrity: I/O standards QDR-IV SRAM configurations Signal terminations Printed circuit board (PCB) layout guidelinesI/O StandardsQDR-IV SRAM interface signals use one of the following JEDEC I/O signallingstandards: HSTL-15 provides the advantages of lower power and lower emissions. HSTL-18 provides increased noise immunity with slightly greater output Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User QDR-IV Layout ApproachFor all practical purposes, you can regard the Timing Analyzer report on your memoryinterface as definitive for a given set of memory and board timing parameters. You willfind timing under Report DDR in Timing Analyzer and on the Timing Analysis tab in theparameter following flowchart illustrates the recommended process to follow during thedesign phase, to determine timing margin and make iterative improvements to LayoutCalculate Setupand Hold DeratingCalculate ChannelSignal IntegrityCalculate BoardSkewsFind MemoryTiming ParametersGenerate an IP Core that Accurately Represents Your Memory Subsystem, Including pin-out and Accurate Parameters in the Parameter Editor s Board Settings TabRun Quartus Prime Compilation with the Generated IP CoreAny Non-Core TimingViolations in the ReportDDR Panel?yesnoDoneAdjust Layout to Improve: Trace Length Mis-Match Signal Reflections (ISI) Cross Talk Memory Speed GradeFor more detailed simulation guidance, refer to the wiki: Interference/CrosstalkFor information on intersymbol interference and crosstalk, refer to the wiki: SkewFor information on calculating board skew parameters, refer to Board Skew Equations,in this you know the absolute delays for all the memory related traces, the interactive Board Skew Parameter Tool can help you calculate the necessary Timing ParametersYou can find the memory timing parameters to enter in the parameter editor, in yourmemory vendor's Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User General Layout GuidelinesThe following table lists general board design layout guidelines. These guidelines areIntel recommendations, and should not be considered as hard requirements. Youshould perform signal integrity simulation on all the traces to verify the signal integrityof the interface. You should extract the slew rate and propagation delay information,enter it into the IP and compile the design to ensure that timing requirements Layout GuidelinesParameterGuidelinesImpedance All unused via pads must be removed, because they cause unwantedcapacitance. Trace impedance plays an important role in the signal integrity. You mustperform board level simulation to determine the best characteristic impedancefor your PCB. For example, it is possible that for multi rank systems 40 ohmscould yield better results than a traditional 50 ohm characteristic Parameter Use uF in 0402 size to minimize inductance Make VTT voltage decoupling close to termination resistors Connect decoupling caps between VTT and ground Use a uF cap for every other VTT pin and uF cap for every VDD andVDDQ pin Verify the capacitive decoupling using the Intel Power Distribution NetworkDesign ToolPower Route GND and VCC as planes Route VCCIO for memories in a single split plane with at least a 20-mil( inches, or mm) gap of separation Route VTT as islands or 250-mil ( ) power traces Route oscillators and PLL power as islands or 100-mil ( ) power tracesGeneral RoutingAll specified delay matching requirements include PCB trace delays, different layerpropagation velocity variance, and crosstalk. To minimize PCB layer propogationvariance, Intel recommends that signals from the same net group always berouted on the same layer. Use 45 angles (not 90 corners) Avoid T-Junctions for critical nets or clocks Avoid T-junctions greater than 250 mils ( mm) Disallow signals across split planes Restrict routing other signals close to system reset signals Avoid routing memory signals closer than inch ( mm) to PCI orsystem clocksRelated LinksPower Distribution QDR-IV Layout GuidelinesObserve the following layout guidelines for your QDR-IV Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide313ParameterGuidelinesGeneral Routing If you must route signals of the same net group on different layers with the sameimpedance characteristic, simulate your worst case PCB trace tolerances to determineactual propagation delay differences. Typical layer-to-layer trace delay variations are onthe order of 15 ps/inch. Avoid T-junctions greater than 150 ps. Match all signals within a given DQ group with a maximum skew of 10 ps and route onthe same Routing Route clocks on inner layers with outer-layer run lengths held to less than 150 ps. Clock signals should maintain a 10-mil ( mm) spacing from other nets. Clocks should maintain a length-matching between clock pairs of 5 ps. Differential clocks should maintain a length-matching between P and N signals of 2 ps. Space between different clock pairs should be at least three times the space between thetraces of a differential and CommandRouting - To minimize crosstalk, route address, bank address, and command signals on adifferent layer than the data signals. Do not route the differential clock signals close to the address signals. Keep the distance from the pin on the QDR-IV component to the stub terminationresistor (VTT) to less than 50 ps for the address/command signal group. - Route the mem_ck (CK/CK#) clocks and set as the target trace propagation delays forthe address/command signal group. Match the CK/CK# clock to within 50 ps of all theDK/DK# clocks for both ports. - Route the address/control signal group ideally on the same layer as the mem_ck (CK/CK#) clocks, to within 20 ps skew of the mem_ck (CK/CK#) Signals For port B only: Swap the polarity of the QKB and QKB# signals with respect to thepolarity of the differential buffer inputs on the FPGA. Connect the positive leg of thedifferential input buffer on the FPGA to QDR-IV QKB# (negative) pin and vice-versa. Notethat the port names at the top-level of the IP already reflect this swap (that is, mem_qkbis assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive bufferleg). For each port, route the DK/DK# write clock and QK/QK# read clock associated with a DQgroup on the same PCB layer. Match these clock pairs to within 5 ps. For each port, set the DK/DK# or QK/QK# clock as the target trace propagation delay forthe associated data signals (DQ). For each port, route the data (DQ) signals for the DQ group ideally on the same layer asthe associated QK/QK# and DK/DK# clocks to within 10 ps skew of the target Trace Length Keep the maximum trace length of all signals from the FPGA to the QDR-IV componentsto 600 Guidelines Avoid routing two signal layers next to each other. Always make sure that the signalsrelated to memory interface are routed between appropriate GND or power layers. For Data and Data Strobe traces: Maintain at least 3H spacing between the edges (air-gap) of these traces, where H is the vertical distance to the closest return path for thatparticular trace. For Address/Command/Control traces: Maintain at least 3H spacing between the edges(air-gap) of these traces, where H is the vertical distance to the closest return path forthat particular trace. For Clock (mem_CK) traces: Maintain at least 5H spacing between two clock pair or aclock pair and any other memory interface trace, where H is the vertical distance to theclosest return path for that particular Matching GuidanceThe following layout approach is recommended, based on the preceding port B only: Swap the polarity of the QKB and QKB# signals with respect to thepolarity of the differential buffer inputs on the FPGA. Connect the positive leg of thedifferential input buffer on the FPGA to QDR-IV QKB# (negative) pin and vice-versa. 8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide314ParameterGuidelinesthat the port names at the top-level of the IP already reflect this swap (that is, mem_qkbis assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive bufferleg). each port, set the DK/DK# or QK/QK# clock as the target trace propagation delay forthe associated data signals (DQ). each port, route the data (DQ) signals for the DQ group ideally on the same layer asthe associated QK/QK# and DK/DK# clocks to within 10 ps skew of the target the mem_ck (CK/CK#) clocks and set as the target trace propagation delays for theaddress/command signal group. Match the CK/CK# clock to within 50 ps of all theDK/DK# clocks for both theaddress/control signal group ideally on the same layer as the mem_ck (CK/CK#) clocks, to within 10 ps skew of the mem_ck (CK/CK#) Package DeskewYou should follow Intel's package deskew LinksPackage Deskew8 Intel Stratix 10 EMIF IP for QDR-IVUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide3159 Intel Stratix 10 EMIF IP for RLDRAM 3This chapter contains IP parameter descriptions, board skew equations, pin planninginformation, and board design guidance for Intel Stratix 10 external memoryinterfaces for RLDRAM Parameter DescriptionsThe following topics describe the parameters available on each tab of the IP parametereditor, which you can use to configure your Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: GeneralTable : General / InterfaceDisplay NameDescriptionConfigurationSpecifies the configuration of the memory interface. The available optionsdepend on the protocol in use. Options include Hard PHY and HardController, Hard PHY and Soft Controller, or Hard PHY only. If youselect Hard PHY only, the AFI interface is exported to allow connection ofa custom memory controller or third-party IP. (Identifier:PHY_RLD3_CONFIG_ENUM)Table : General / ClocksDisplay NameDescriptionMemory clock frequencySpecifies the operating frequency of the memory interface in MHz. If youchange the memory frequency, you should update the memory latencyparameters on the Memory tab and the memory timing parameters on theMem Timing tab. (Identifier: PHY_RLD3_MEM_CLK_FREQ_MHZ)Use recommended PLL reference clockfrequencySpecifies that the PLL reference clock frequency is automatically calculatedfor best performance. If you want to specify a different PLL reference clockfrequency, uncheck the check box for this parameter. (Identifier:PHY_RLD3_DEFAULT_REF_CLK_FRE Q)PLL reference clock frequencyThis parameter tells the IP what PLL reference clock frequency the user willsupply. Users must select a valid PLL reference clock frequency from thelist. The values in the list can change when the memory interface frequencychanges and/or the clock rate of user logic changes. It is recommended touse the fastest possible PLL reference clock frequency because it leads tobetter jitter performance. Selection is required only if the user does notcheck the "Use recommended PLL reference clock frequency" option.(Identifier: PHY_RLD3_USER_REF_CLK_FREQ_MHZ) UG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008RegisteredDisplay NameDescriptionPLL reference clock jitterSpecifies the peak-to-peak jitter on the PLL reference clock source. Theclock source of the PLL reference clock must meet or exceed the followingjitter requirements: 10ps peak to peak, or RMS at 1e-12 BER, at 1e-16 BER. (Identifier: PHY_RLD3_REF_CLK_JITTER_PS)Clock rate of user logicSpecifies the relationship between the user logic clock frequency and thememory clock frequency. For example, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz, a quarter-rate interfacemeans that the user logic in the FPGA runs at 200MHz. (Identifier:PHY_RLD3_RATE_ENUM)Core clocks sharingWhen a design contains multiple interfaces of the same protocol, rate,frequency, and PLL reference clock source, they can share a common set ofcore clock domains. By sharing core clock domains, they reduce clocknetwork usage and avoid clock synchronization logic between share core clocks, denote one of the interfaces as "Master", and theremaining interfaces as "Slave". In the RTL, connect theclks_sharing_master_out signal from the master interface to theclks_sharing_slave_in signal of all the slave master and slave interfaces still expose their own output clock ports inthe RTL (for example, emif_usr_clk, afi_clk), but the physical signalsare equivalent, hence it does not matter whether a clock port from a masteror a slave is used. As the combined width of all interfaces sharing the samecore clock increases, you may encounter timing closure difficulty fortransfers between the FPGA core and the periphery.(Identifier: PHY_RLD3_CORE_CLKS_SHARING_ENUM)Specify additional core clocks based onexisting PLLDisplays additional parameters allowing you to create additional outputclocks based on the existing PLL. This parameter provides an alternativeclock-generation mechanism for when your design exhaustsavailable PLL resources. The additional output clocks that you create canbe fed into the core. Clock signals created with this parameter aresynchronous to each other, but asynchronous to the memory interface coreclock domains (such as emif_usr_clk or afi_clk). You must followproper clock-domain-crossing techniques when transferring data betweenclock domains. (Identifier: PLL_ADD_EXTRA_CLKS)Table : General / Clocks / Additional Core ClocksDisplay NameDescriptionNumber of additional core clocksSpecifies the number of additional output clocks to create from the PLL.(Identifier: PLL_USER_NUM_OF_EXTRA_CLKS)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_0Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_5)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_5)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_1Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_6)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_6)9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide317Table : General / Clocks / Additional Core Clocks / pll_extra_clk_2Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_7)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_7)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_3Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MH Z_GUI_8)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_P S_GUI_8) Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: MemoryTable : Memory / TopologyDisplay NameDescriptionDQ width per deviceSpecifies number of DQ pins per RLDRAM3 device. Available widths for DQare x18 and x36. (Identifier: MEM_RLD3_DQ_PER_DEVICE)Enable DM pinsIndicates whether the interface uses the DM pins. If enabled, one DM pinper write data group is added. (Identifier: MEM_RLD3_DM_EN)Enable width expansionIndicates whether to combine two memory devices to double the data buswidth. With two devices, the interface supports a width expansionconfiguration up to 72-bits. For width expansion configuration, the addressand control signals are routed to 2 devices. (Identifier:MEM_RLD3_WIDTH_EXPANDED)Enab le depth expansion using twin diepackageIndicates whether to combine two RLDRAM3 devices to double the addressspace, resulting in more density. (Identifier:MEM_RLD3_DEPTH_EXPANDED)Addr ess widthNumber of address pins. (Identifier: MEM_RLD3_ADDR_WIDTH)Bank address widthNumber of bank address pins (Identifier: MEM_RLD3_BANK_ADDR_WIDTH)Table : Memory / Mode Register SettingsDisplay NameDescriptiontRCDetermines the mode register setting that controls the tRC(activate toactivate timing parameter). Refer to the tRC table in the memory vendordata sheet. Set the tRC according to the memory speed grade and datalatency. (Identifier: MEM_RLD3_T_RC_MODE_ENUM)Data LatencyDetermines the mode register setting that controls the data latency. Setsboth READ and WRITE latency (RL and WL). (Identifier:MEM_RLD3_DATA_LATENCY_MODE_E NUM)Output driveDetermines the mode register setting that controls the output drive setting.(Identifier: MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM)ODTDeter mines the mode register setting that controls the ODT setting.(Identifier: MEM_RLD3_ODT_MODE_ENUM) 9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide318Display NameDescriptionAREF protocolDetermines the mode register setting that controls the AREFprotocol setting. The AUTO REFRESH (AREF) protocol is selected bysetting mode register 1. There are two ways in which AREF commands canbe issued to the RLDRAM, the memory controller can either issue bankaddress-controlled or multibank AREF commands. Multibank refreshprotocol allows for the simultaneous refreshing of a row in up to four banks(Identifier: MEM_RLD3_AREF_PROTOCOL_ENUM)Burst lengthDetermines the mode register setting that controls the burst length.(Identifier: MEM_RLD3_BL)Write protocolDetermines the mode register setting that controls the write protocolsetting. When multiple bank (dual bank or quad bank) is selected, identicaldata is written to multiple banks. (Identifier:MEM_RLD3_WRITE_PROTOCOL_ENUM ) Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: FPGA I/OYou should use Hyperlynx* or similar simulators to determine the best settings foryour board. Refer to the EMIF Simulation Guidance wiki page for : FPGA I/O / FPGA I/O SettingsDisplay NameDescriptionVoltageThe voltage level for the I/O pins driving the signals between the memorydevice and the FPGA memory interface. (Identifier:PHY_RLD3_IO_VOLTAGE)Periodic OCT re-calibrationSpecifies that the system periodically recalibrate on-chip termination (OCT)to minimize variations in termination value caused by changing operatingconditions (such as changes in temperature). By recalibrating OCT, I/Otiming margins are improved. When enabled, this parameter causes thePHY to halt user traffic about every seconds for about 1900 memoryclock cycles, to perform OCT recalibration. Efficiency is reduced byabout 1% when this option is enabled. (Identifier:PHY_RLD3_USER_PERIODIC_OCT_R ECAL_ENUM)Use default I/O settingsSpecifies that a legal set of I/O settings are automatically selected. Thedefault I/O settings are not necessarily optimized for a specific board. Toachieve optimal signal integrity, perform I/O simulations with IBIS modelsand enter the I/O settings manually, based on simulation results.(Identifier: PHY_RLD3_DEFAULT_IO)Table : FPGA I/O / FPGA I/O Settings / Address/CommandDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the address/command pins of thememory interface. The selected I/O standard configures the circuit withinthe I/O buffer to match the industry standard. (Identifier:PHY_RLD3_USER_AC_IO_STD_ENUM )Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_RLD3_USER_AC_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_RLD3_USER_AC_SLEW_RATE_ENUM)9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide319Table : FPGA I/O / FPGA I/O Settings / Memory ClockDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the memory clock pins. Theselected I/O standard configures the circuit within the I/O buffer to matchthe industry standard. (Identifier: PHY_RLD3_USER_CK_IO_STD_ENUM)Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_RLD3_USER_CK_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_RLD3_USER_CK_SLEW_RATE_ENUM)Table : FPGA I/O / FPGA I/O Settings / Data BusDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the data and data clock/strobe pinsof the memory interface. The selected I/O standard option configures thecircuit within the I/O buffer to match the industry standard. (Identifier:PHY_RLD3_USER_DATA_IO_STD_EN UM)Output modeThis parameter allows you to change the output current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_RLD3_USER_DATA_OUT_MODE_ENUM)Input modeThis parameter allows you to change the input termination settings for theselected I/O standard. Perform board simulation with IBIS models todetermine the best settings for your design. (Identifier:PHY_RLD3_USER_DATA_IN_MODE_E NUM)Use recommended initial VrefinSpecifies that the initial Vrefin setting is calculated automatically, to areasonable value based on termination settings. (Identifier:PHY_RLD3_USER_AUTO_STARTING_ VREFIN_EN)Initial VrefinSpecifies the initial value for the reference voltage on the datapins(Vrefin). This value is entered as a percentage of the supply voltagelevel on the I/O pins. The specified value serves as a starting point and maybe overridden by calibration to provide better timing margins. If you chooseto skip Vref calibration (Diagnostics tab), this is the value that is usedas the Vref for the interface. (Identifier:PHY_RLD3_USER_STARTING_VREFI N)Table : FPGA I/O / FPGA I/O Settings / PHY InputsDisplay NameDescriptionPLL reference clock I/O standardSpecifies the I/O standard for the PLL reference clock of the memoryinterface. (Identifier: PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM)RZ Q I/O standardSpecifies the I/O standard for the RZQ pin used in the memory interface.(Identifier: PHY_RLD3_USER_RZQ_IO_STD_ENUM) Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Mem TimingThese parameters should be read from the table in the datasheet associated with thespeed bin of the memory device (not necessarily the frequency at which the interfaceis running).9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide320Table : Mem TimingDisplay NameDescriptionSpeed binThe speed grade of the memory device used. This parameter refers to themaximum rate at which the memory device is specified to run. (Identifier:MEM_RLD3_SPEEDBIN_ENUM)tDS (base)tDS(base) refers to the setup time for the Data (DQ) bus before therising edge of the DQS strobe. (Identifier: MEM_RLD3_TDS_PS)tDS (base) AC leveltDS (base) AC level refers to the voltage level which the data bus mustcross and remain above during the setup margin window. The signalis considered stable only if it remains above this voltage level (for a logic 1)or below this voltage level (for a logic 0) for the entire setup period.(Identifier: MEM_RLD3_TDS_AC_MV)tDH (base)tDH (base) refers to the hold time for the Data (DQ) bus after the risingedge of CK. (Identifier: MEM_RLD3_TDH_PS)tDH (base) DC leveltDH (base) DC level refers to the voltage level which the data bus mustnot cross during the hold window. The signal is considered stable only ifit remains above this voltage level (for a logic 1) or below this voltage level(for a logic 0) for the entire hold period. (Identifier:MEM_RLD3_TDH_DC_MV)tQKQ_maxt QKQ_max describes the maximum skew between the read strobe (QK)clock edge to the data bus (DQ/DINV) edge. (Identifier:MEM_RLD3_TQKQ_MAX_PS)tQHtQH specifies the output hold time for the DQ/DINV in relation to QK.(Identifier: MEM_RLD3_TQH_CYC)tCKDK_maxtCKDK_max refers to the maximum skew from the memory clock (CK)to the write strobe (DK). (Identifier: MEM_RLD3_TCKDK_MAX_CYC)tCKDK_mintCKDK_mi n refers to the minimum skew from the memory clock (CK) tothe write strobe (DK). (Identifier: MEM_RLD3_TCKDK_MIN_CYC)tCKQK_maxtCKQK_ma x refers to the maximum skew from the memory clock (CK)to the read strobe (QK). (Identifier: MEM_RLD3_TCKQK_MAX_PS)tIS (base)tIS (base) refers to the setup time for the Address/Command/Control(A) bus to the rising edge of CK. (Identifier: MEM_RLD3_TIS_PS)tIS (base) AC leveltIS (base) AC level refers to the voltage level which the address/command signal must cross and remain above during the setupmargin window. The signal is considered stable only if it remains abovethis voltage level (for a logic 1) or below this voltage level (for a logic 0) forthe entire setup period. (Identifier: MEM_RLD3_TIS_AC_MV)tIH (base)tIH (base) refers to the hold time for the Address/Command (A) busafter the rising edge of CK. Depending on what AC level the user haschosen for a design, the hold margin can vary (this variance will beautomatically determined when the user chooses the "tIH (base) AClevel"). (Identifier: MEM_RLD3_TIH_PS)tIH (base) DC leveltIH (base) DC level refers to the voltage level which the address/command signal must not cross during the hold window. The signal isconsidered stable only if it remains above this voltage level (for a logic 1) orbelow this voltage level (for a logic 0) for the entire hold period. (Identifier:MEM_RLD3_TIH_DC_MV) Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Board9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide321Table : Board / Intersymbol Interference/CrosstalkDisplay NameDescriptionUse default ISI/crosstalk valuesYou can enable this option to use default intersymbol interference andcrosstalk values for your topology. Note that the default values are notoptimized for your board. For optimal signal integrity, it is recommendedthat you do not enable this parameter, but instead perform I/O simulationusing IBIS models and Hyperlynx)*, and manually enter values based onyour simulation results, instead of using the default values. (Identifier:BOARD_RLD3_USE_DEFAULT_ISI_V ALUES)Address and command ISI/crosstalkThe address and command window reduction due to ISI and crosstalkeffects. The number to be entered is the total loss of margin on both thesetup and hold sides (measured loss on the setup side + measuredloss on the hold side). Refer to the EMIF Simulation Guidance wiki pagefor additional information. (Identifier: BOARD_RLD3_USER_AC_ISI_NS)QK/QK# ISI/crosstalkQK/QK# ISI/crosstalk describes the reduction of the read data window dueto intersymbol interference and crosstalk effects on the QK/QK# signalwhen driven by the memory device during a read. The number to beentered is the total loss of margin on both the setup and hold sides(measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_RLD3_USER_RCLK_ISI_NS)Read DQ ISI/crosstalkThe reduction of the read data window due to ISI and crosstalk effects onthe DQ signal when driven by the memory device during a read. Thenumber to be entered is the total loss of margin on the setup and holdside (measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_RLD3_USER_RDATA_ISI_NS)DK/DK# ISI/crosstalkDK/DK# ISI/crosstalk describes the reduction of the write data window dueto intersymbol interference and crosstalk effects on the DK/DK# signalwhen driven by the FPGA during a write. The number to be entered is thetotal loss of margin on the setup and hold side (measured loss onthe setup side + measured loss on the hold side). Refer to the EMIFSimulation Guidance wiki page for additional information. (Identifier:BOARD_RLD3_USER_WCLK_ISI_NS) Write DQ ISI/crosstalkThe reduction of the write data window due to ISI and crosstalk effects onthe DQ signal when driven by the FPGA during a write. The number to beentered is the total loss of margin on the setup and hold side(measured loss on the setup side + measured loss on the holdside). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_RLD3_USER_WDATA_ISI_NS)Table : Board / Board and Package SkewsDisplay NameDescriptionPackage deskewed with board layout(QK group)If you are compensating for package skew on the QK bus in the boardlayout (hence checking the box here), please include package skew incalculating the following board skew parameters. (Identifier:BOARD_RLD3_IS_SKEW_WITHIN_QK _DESKEWED)Maximum board skew within QK groupMaximum board skew within QK group refers to the largest skew betweenall DQ and DM pins in a QK group. This value can affect the read captureand write margins. (Identifier: BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS)Maximum system skew within QK groupThe largest skew between all DQ and DM pins in a QK group. Entercombined board and package skew. This value affects the read capture andwrite margins. (Identifier:BOARD_RLD3_PKG_BRD_SKEW_WITH IN_QK_NS) 9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide322Display NameDescriptionPackage deskewed with board layout(address/command bus)Enable this parameter if you are compensating for package skew on theaddress, command, control, and memory clock buses in the board package skew in calculating the following board skewparameters. (Identifier:BOARD_RLD3_IS_SKEW_WITHIN_AC _DESKEWED)Maximum board skew within address/command busThe largest skew between the address and command signals. Enter theboard skew only; package skew is calculated automatically, based on thememory interface configuration, and added to this value. (Identifier:BOARD_RLD3_BRD_SKEW_WITHIN_A C_NS)Maximum system skew within address/command busMaximum system skew within address/command bus refers to the largestskew between the address and command signals. (Identifier:BOARD_RLD3_PKG_BRD_SKEW_WITH IN_AC_NS)Average delay difference between DKand CKThis parameter describes the average delay difference between the DKsignals and the CK signal, calculated by averaging the longest and smallestDK trace delay minus the CK trace delay. Positive values represent DKsignals that are longer than CK signals and negative values represent DKsignals that are shorter than CK signals. (Identifier:BOARD_RLD3_DK_TO_CK_SKEW_NS) Maximum delay difference betweendevicesThis parameter describes the largest propagation delay on the DQ signalsbetween example, in a two-rank configuration where devices are placed in series,there is an extra propagation delay for DQ signals going to and coming backfrom the furthest device compared to the nearest device. This parameter isonly applicable when there is more than one rank.(Identifier: BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS)Maximum skew between DK groupsThis parameter describes the largest skew between DK signals in differentDK groups. (Identifier: BOARD_RLD3_SKEW_BETWEEN_DK_NS)Average delay difference betweenaddress/command and CKThe average delay difference between the address/command signals andthe CK signal, calculated by averaging the longest and smallest address/command signal trace delay minus the maximum CK trace delay. Positivevalues represent address and command signals that are longer than CKsignals and negative values represent address and command signals thatare shorter than CK signals. (Identifier:BOARD_RLD3_AC_TO_CK_SKEW_NS) Maximum CK delay to deviceThe maximum CK delay to device refers to the delay of the longest CK tracefrom the FPGA to any device. (Identifier:BOARD_RLD3_MAX_CK_DELAY_NS)M aximum DK delay to deviceThe maximum DK delay to device refers to the delay of the longest DKtrace from the FPGA to any device. (Identifier:BOARD_RLD3_MAX_DK_DELAY_NS) Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: DiagnosticsTable : Diagnostics / Simulation OptionsDisplay NameDescriptionCalibration modeSpecifies whether to skip memory interface calibration duringsimulation, or to simulate the full calibration the full calibration process can take hours (or even days),depending on the width and depth of the memory interface. You canachieve much faster simulation times by skipping the calibration process,but that is only expected to work when the memory model is ideal and theinterconnect delays are 9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide323Display NameDescriptionIf you enable this parameter, the interface still performs some memoryinitialization before starting normal operations. Abstract PHY is supportedwith skip calibration.(Identifier: DIAG_RLD3_SIM_CAL_MODE_ENUM)Abstract phy for fast simulationSpecifies that the system use Abstract PHY for simulation. Abstract PHYreplaces the PHY with a model for fast simulation and can reducesimulation time by 2-3 times. Abstract PHY is available for certainprotocols and device families, and only when you select Skip Calibration.(Identifier: DIAG_RLD3_ABSTRACT_PHY)Table : Diagnostics / Calibration Debug OptionsDisplay NameDescriptionQuartus Prime EMIF Debug Toolkit/On-Chip Debug PortSpecifies the connectivity of an Avalon slave interface for use by theQuartus Prime EMIF Debug Toolkit or user core you set this parameter to "Disabled", no debug features are enabled. Ifyou set this parameter to "Export", an Avalon slave interface named"cal_debug" is exported from the IP. To use this interface with the EMIFDebug Toolkit, you must instantiate and connect an EMIF debug interface IPcore to it, or connect it to the cal_debug_out interface of another EMIFcore. If you select "Add EMIF Debug Interface", an EMIF debug interfacecomponent containing a JTAG Avalon Master is connected to the debug port,allowing the core to be accessed by the EMIF Debug one EMIF debug interface should be instantiated per I/O column. Youcan chain additional EMIF or PHYLite cores to the first by enabling the"Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option for all cores in the chain, and selecting "Export"for the "Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port"option on all cores after the first.(Identifier: DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE)Enable Daisy-Chaining for QuartusPrime EMIF Debug Toolkit/On-ChipDebug PortSpecifies that the IP export an Avalon-MM master interface(cal_debug_out) which can connect to the cal_debug interface of otherEMIF cores residing in the same I/O column. This parameter applies onlyif the EMIF Debug Toolkit or On-Chip Debug Port is enabled. Refer tothe Debugging Multiple EMIFs wiki page for more information aboutdebugging multiple EMIFs. (Identifier:DIAG_RLD3_EXPORT_SEQ_AVALON_ MASTER)Interface IDIdentifies interfaces within the I/O column, for use by the EMIF DebugToolkit and the On-Chip Debug Port. Interface IDs should be unique amongEMIF cores within the same I/O column. If the Quartus Prime EMIFDebug Toolkit/On-Chip Debug Port parameter is set to Disabled, theinterface ID is unused. (Identifier: DIAG_RLD3_INTERFACE_ID)Use Soft NIOS Processor for On-ChipDebugEnables a soft Nios processor as a peripheral component to access the On-Chip Debug Port. Only one interface in a column can activate this option.(Identifier: DIAG_SOFT_NIOS_MODE)Table : Diagnostics / Example DesignDisplay NameDescriptionNumber of core clocks sharing slaves toinstantiate in the example designSpecifies the number of core clock sharing slaves to instantiate in theexample design. This parameter applies only if you set the "Core clockssharing" parameter in the "General" tab to "Master" or "Slave".(Identifier: DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES)Enable In-System-Sources-and-ProbesEnables In-System-Sources-and-Probes in the example design for commondebug signals, such as calibration status or example traffic generator per-bit status. This parameter must be enabled if you want to do drivermargining. (Identifier: DIAG_RLD3_EX_DESIGN_ISSP_EN)9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide324Table : Diagnostics / Traffic GeneratorDisplay NameDescriptionUse configurable Avalon trafficgenerator option allows users to add the new configurable Avalon trafficgenerator to the example design. (Identifier: DIAG_RLD3_USE_TG_AVL_2)Bypass the default traffic patternSpecifies that the controller/interface bypass the traffic generator pattern after reset. If you do not enable this parameter, the trafficgenerator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_RLD3_BYPASS_DEFAULT_PATTERN)Bypass the user-configured traffic stageSpecifies that the controller/interface bypass the user-configured trafficgenerator's pattern after reset. If you do not enable this parameter, thetraffic generator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration can be done by connecting to the traffic generator via theEMIF Debug Toolkit, or by using custom logic connected to the Avalon-MMconfiguration slave port on the traffic generator. Configuration can also besimulated using the example testbench provided in file.(Identifier: DIAG_RLD3_BYPASS_USER_STAGE)Bypass the traffic generator repeated-writes/repeated-reads test patternSpecifies that the controller/interface bypass the traffic generator's repeattest stage. If you do not enable this parameter, every write and read isrepeated several times. (Identifier: DIAG_RLD3_BYPASS_REPEAT_STAGE)Bypass the traffic generator stresspatternSpecifies that the controller/interface bypass the traffic generator's stresspattern stage. (Stress patterns are meant to create worst-case signalintegrity patterns on the data pins.) If you do not enable this parameter,the traffic generator does not assert a pass or fail status until the generatoris configured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_RLD3_BYPASS_STRESS_STAGE)Export Traffic Generator interfaceSpecifies that the IP export an Avalon-MM slave port for configuring theTraffic Generator. This is required only if you are configuring the trafficgenerator through user logic and not through through the EMIF DebugToolkit. (Identifier: DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE)Table : Diagnostics / PerformanceDisplay NameDescriptionEnable Efficiency MonitorAdds an Efficiency Monitor component to the Avalon-MM interface of thememory controller, allowing you to view efficiency statistics of the can access the efficiency statistics using the EMIF Debug Toolkit.(Identifier: DIAG_RLD3_EFFICIENCY_MONITOR)Table : Diagnostics / MiscellaneousDisplay NameDescriptionUse short Qsys interface namesSpecifies the use of short interface names, for improved usability andconsistency with other Qsys components. If this parameter is disabled, thenames of Qsys interfaces exposed by the IP will include the type anddirection of the interface. Long interface names are supported forbackward-compatibility and will be removed in a future release. (Identifier:SHORT_QSYS_INTERFACE_NAMES) Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Example Designs9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide325Table : Example Designs / Available Example DesignsDisplay NameDescriptionSelect designSpecifies the creation of a full Quartus Prime project, instantiating anexternal memory interface and an example traffic generator, according toyour parameterization. After the design is created, you can specify thetarget device and pin location assignments, run a full compilation, verifytiming closure, and test the interface on your board using the programmingfile created by the Quartus Prime assembler. The 'Generate ExampleDesign' button lets you generate simulation or synthesis file sets.(Identifier: EX_DESIGN_GUI_RLD3_SEL_DESIGN)Table : Example Designs / Example Design FilesDisplay NameDescriptionSimulationSpecifies that the 'Generate Example Design' button create all necessaryfile sets for simulation. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, simulation file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the simulation example design, and file with other corresponding tcl files. You canrun from a command line to generate thesimulation example design. The generated example designs for varioussimulators are stored in the /sim sub-directory. (Identifier:EX_DESIGN_GUI_RLD3_GEN_SIM)S ynthesisSpecifies that the 'Generate Example Design' button create all necessaryfile sets for synthesis. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, synthesis file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the synthesis example design, and script with other corresponding tcl files. You canrun from a command line to generate thesynthesis example design. The generated example design is stored inthe /qii sub-directory. (Identifier: EX_DESIGN_GUI_RLD3_GEN_SYNTH)Table : Example Designs / Generated HDL FormatDisplay NameDescriptionSimulation HDL formatThis option lets you choose the format of HDL in which generatedsimulation files are created. (Identifier:EX_DESIGN_GUI_RLD3_HDL_FORMA T)Table : Example Designs / Target Development KitDisplay NameDescriptionSelect boardSpecifies that when you select a development kit with a memory module,the generated example design contains all settings and fixed pinassignments to run on the selected board. You must select a developmentkit preset to generate a working example design for the specifieddevelopment kit. Any IP settings not applied directly from a developmentkit preset will not have guaranteed results when testing the developmentkit. To exclude hardware support of the example design, select 'none' fromthe 'Select board' pull down menu. When you apply a development kitpreset, all IP parameters are automatically set appropriately to match theselected preset. If you want to save your current settings, you should do sobefore you apply the preset. You can save your settings under a differentname using File->Save as. (Identifier:EX_DESIGN_GUI_RLD3_TARGET_DE V_KIT)9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Board Skew EquationsThe following table presents the underlying equations for the board skew Equations for RLDRAM 3 Board Skew ParametersTable Skew Parameter EquationsParameterDescription/EquationMa ximum CK delay to deviceThe delay of the longest CK trace from the FPGA to any n is the number of memory clocks. For example, the maximum CK delay for twopairs of memory clocks is expressed by the following equation:max2CK1PathDelay,CK2PathDelayMa ximum DK delay to deviceThe delay of the longest DK trace from the FPGA to any n is the number of DK. For example, the maximum DK delay for two DK is expressedby the following equation:max2DK1PathDelay,DK2PathDelayAv erage delay differencebetween DK and CKThe average delay difference between the DK signals and the CK signal, calculated byaveraging the longest and smallest DK delay minus the CK delay. Positive values representDK signals that are longer than CK signals and negative values represent DK signals thatare shorter than CK signals. The Quartus Prime software uses this skew to optimize thedelay of the DK signals to have appropriate setup and hold ,mCKnPathDelay DKmPathDelay+ minn,mCKnPathDelay DKmPathDelay2where n is the number of memory clocks and m is the number of system skewwithin address/commandbusMaxAC MinACThe largest skew between the address and command signals. Enter combined board andpackage delay differencebetween address/commandand CKThe average delay difference between the address and command signals and the CK signal,calculated by averaging the longest and smallest Address/Command signal delay minus theCK delay. Positive values represent address and command signals that are longer than CKsignals and negative values represent address and command signals that are shorter thanCK signals. The Quartus Prime software uses this skew to optimize the delay of the addressand command signals to have appropriate setup and hold margins. n = nn = 1LongestACPathDelay + ShortestACPathDelay2 CKnPathDelaynMaximum board skew withinQK groupThe largest skew between all DQ and DM pins in a QK group. Enter your board skew skew will be calculated automatically, based on the memory interfaceconfiguration, and added to this value. This value affects the read capture and minDQnwhere n is the number of skew between DKgroupsThe largest skew between DK signals in different DK 9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide327ParameterDescription/Equationmax nmaxDKn minDKnwhere n is the number of Pin and Resource PlanningThe following topics provide guidelines on pin placement for external , all external memory interfaces require the following FPGA resources: Interface pins PLL and clock network Other FPGA resources for example, core fabric logic, and on-chip termination(OCT) calibration blocksOnce all the requirements are known for your external memory interface, you canbegin planning your Interface PinsAny I/O banks that do not support transceiver operations in Intel Stratix 10 devicessupport external memory interfaces. However, DQS (data strobe or data clock) andDQ (data) pins are listed in the device pin tables and are fixed at specific locations inthe device. You must adhere to these pin locations to optimize routing, minimize skew,and maximize margins. Always check the pin table for the actual locations of the DQSand DQ : Maximum interface width varies from device to device depending on the number ofI/O pins and DQS or DQ groups available. Achievable interface width also depends onthe number of address and command pins that the design requires. To ensureadequate PLL, clock, and device routing resources are available, you should alwaystest fit any IP in the Intel Quartus Prime Prime software before PCB devices do not limit the width of external memory interfaces beyond thefollowing requirements: Maximum possible interface width in any particular device is limited by thenumber of DQS groups available. Sufficient clock networks are available to the interface PLL as required by the IP. Sufficient spare pins exist within the chosen bank or side of the device to includeall other address and command, and clock pin placement requirements. The greater the number of banks, the greater the skew, hence Intel recommendsthat you always generate a test project of your desired configuration and confirmthat it meets Estimating Pin RequirementsYou should use the Intel Quartus Prime software for final pin fitting. However, you canestimate whether you have enough pins for your memory interface using the EMIFDevice Selector on , or perform the following steps:9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide3281. Determine how many read/write data pins are associated per data strobe or Calculate the number of other memory interface pins needed, including any otherclocks (write clock or memory system clock), address, command, and RZQ. Referto the External Memory Interface Pin Table to determine necessary Address/Command/Clock pins based on your desired Calculate the total number of I/O banks required to implement the memoryinterface, given that an I/O bank supports up to 48 GPIO should test the proposed pin-outs with the rest of your design in the Intel QuartusPrime software (with the correct I/O standard and OCT connections) before finalizingthe pin-outs. There can be interactions between modules that are illegal in the IntelQuartus Prime software that you might not know about unless you compile the designand use the Intel Quartus Prime Pin LinksExternal Memory Interfaces Support Maximum Number of InterfacesThe maximum number of interfaces supported for a given memory protocol varies,depending on the FPGA in otherwise noted, the calculation for the maximum number of interfaces isbased on independent interfaces where the address or command pins are not : You may need to share PLL clock outputs depending on your clock network interface information for Intel Stratix 10, consult the EMIF Device Selector closure depends on device resource and routing utilization. For moreinformation about timing closure, refer to the Area and Timing OptimizationTechniques chapter in the Intel Quartus Prime Links External Memory Interfaces Support Center Intel Stratix 10 EMIF Architecture: PLL Reference Clock Networks on page 20 External Memory Interface Device Selector Intel Quartus Prime Pro Edition FPGA ResourcesThe Intel FPGA memory interface IP uses FPGA fabric, including registers and theMemory Block to implement the memory OCT calibration block is used if you are using the FPGA OCT feature in thememory interface. The OCT calibration block uses a single pin (RZQ). You can selectany of the available OCT calibration block as you do not need to place this block in thesame bank or device side of your memory interface. The only requirement is that theI/O bank where you place the OCT calibration block uses the same VCCIO voltage asthe memory interface. You can share multiple memory interfaces with the same OCTcalibration block if the VCCIO voltage is the Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User OCTIf the memory interface uses any FPGA OCT calibrated series, parallel, or dynamictermination for any I/O in your design, you need a calibration block for the OCTcircuitry. This calibration block is not required to be within the same bank or side ofthe device as the memory interface RZQ pin in Intel Stratix 10 devices can be used as a general purpose I/O pin whenit is not used to support OCT, provided the signal conforms to the bank PLLWhen using PLL for external memory interfaces, you must consider the followingguidelines: For the clock source, use the clock input pin specifically dedicated to the PLL thatyou want to use with your external memory interface. The input and output pinsare only fully compensated when you use the dedicated PLL clock input pin. If theclock source for the PLL is not a dedicated clock input pin for the dedicated PLL,you would need an additional clock network to connect the clock source to the PLLblock. Using additional clock network may increase clock jitter and degrade thetiming margin. Pick a PLL and PLL input clock pin that are located on the same side of the deviceas the memory interface pins. Share the DLL and PLL static clocks for multiple memory interfaces provided thecontrollers are on the same or adjacent side of the device and run at the samememory clock frequency. If your design uses a dedicated PLL to only generate a DLL input reference clock,you must set the PLL mode to No Compensation in the Intel Quartus Primesoftware to minimize the jitter, or the software forces this setting PLL does not generate other output, so it does not need to compensate forany clock Pin Guidelines for Intel Stratix 10 EMIF IPThe Intel Stratix 10 device contains up to three I/O columns that can be used byexternal memory Intel Stratix 10 I/O subsystem resides in the I/Ocolumns. Each column contains multiple I/O banks, each of which consists of four I/Olanes. An I/O lane is a group of twelve I/O Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide330The I/O column, I/O bank, I/O lane, adjacent I/O bank, and pairing pin for everyphysical I/O pin can be uniquely identified using the Bank Number and Indexwithin I/O Bank values which are defined in each Intel Stratix 10 device pin-outfile. The numeric component of the Bank Number value identifies the I/O column,while the letter represents the I/O bank. The Index within I/O Bank value falls within one of the following ranges: 0 to11, 12 to 23, 24 to 35, or 36 to 47, and represents I/O lanes 1, 2, 3, and 4,respectively. The adjacent I/O bank is defined as the I/O bank with same column number butthe letter is either before or after the respective I/O bank letter in the A-Z system. The pairing pin for an I/O pin is located in the same I/O bank. You can identify thepairing pin by adding one to its Index within I/O Bank number (if it is aneven number), or by subtracting one from its Index within I/O Bank number(if it is an odd number).For example, a physical pin with a Bank Number of 2M and Index within I/OBank of 22, indicates that the pin resides in I/O lane 2, in I/O bank 2M, in column adjacent I/O banks are 2L and 2N. The pairing pin for this physical pin is the pinwith an Index within I/O Bank of 23 and Bank Number of General GuidelinesYou should follow the recommended guidelines when performing pin placement for allexternal memory interface pins targeting Intel Stratix 10 devices, whether you areusing the hard memory controller or your own you are using the hard memory controller, you should employ the relative pinlocations defined in the <variation_name>/altera_emif_arch_nd_versionnumber/<synth|sim>/<variation_name>_altera_emif_arch_nd_versionnumber_<unique ID> file, w+ted with your : 1. EMIF IP pin-out requirements for the Intel Stratix 10 Hard Processor Subsystem(HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IPdefines a fixed pin-out in the Intel Quartus Prime IP file (.qip), based on the IPconfiguration. When targeting Intel Stratix 10 HPS, you do not need to makelocation assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the IntelQuartus Prime software. Alternatively, consult the device handbook or the devicepin-out files. For information on how you can customize the HPS EMIF pin-out,refer to Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP with Ping Pong PHY, PHY only, RLDRAMx , QDRx and LPDDR3 are not supported Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide331Observe the following general guidelines when placing pins for your Intel Stratix 10external memory interface:1. Ensure that the pins of a single external memory interface reside within a singleI/O An external memory interface can occupy one or more banks in the same I/Ocolumn. When an interface must occupy multiple banks, ensure that those banksare adjacent to one Any pin in the same bank that is not used by an external memory interface isavailable for use as a general purpose I/O of compatible voltage and All address and command pins and their associated clock pins (CK and CK#) mustreside within a single bank. The bank containing the address and command pins isidentified as the address and command To minimize latency, when the interface uses more than two banks, you mustselect the center bank of the interface as the address and command The address and command pins and their associated clock pins in the address andcommand bank must follow a fixed pin-out scheme, as defined in the Intel Stratix10 External Memory Interface Pin Information File, which is available do not have to place every address and command pin manually. If you assignthe location for one address and command pin, the Fitter automatically places theremaining address and command : The pin-out scheme is a hardware requirement that you must follow, andcan vary according to the topology of the memory device. Some schemesrequire three lanes to implement address and command pins, while othersrequire four lanes. To determine which scheme to follow, refer to themessages window during parameterization of your IP, or to the<variation_name>/altera_emif_arch_nd_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nd_<version>_<uniqueID> file after you have generated your An unused I/O lane in the address and command bank can serve to implement adata group, such as a x8 DQS group. The data group must be from the samecontroller as the address and command An I/O lane must not be used by both address and command pins and data Place read data groups according to the DQS grouping in the pin table and PinPlanner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQand CQ# / QK and QK#) must reside at physical pins capable of functioning asDQS/CQ and DQSn/CQn for a specific read data group size. You must place theassociated read data pins (such as DQ and Q), within the same Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide332Note: other device families, there is no need to swap CQ/CQ# pins incertain QDR II and QDR II+ latency requires that the polarity of all QKB/QKB# pins be swapped withrespect to the polarity of the differential buffer inputs on the FPGA toensure correct data capture on port B. All QKB pins on the memorydevice must be connected to the negative pins of the input buffers onthe FPGA side, and all QKB# pins on the memory device must beconnected to the positive pins of the input buffers on the FPGA that the port names at the top-level of the IP already reflect thisswap (that is, mem_qkb is assigned to the negative buffer leg, andmem_qkb_n is assigned to the positive buffer leg).10. You can implement two x4 DQS groups with a single I/O lane. The pin tablespecifies which pins within an I/O lane can be used for the two pairs of DQS andDQS# signals. In addition, for x4 DQS groups you must observe the followingrules: There must be an even number of x4 groups in an external memory interface. DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly,DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS groupX and DQS group X+1 must be in the same I/O lane, where X is an You should place the write data groups according to the DQS grouping in the pintable and Pin Planner. Output-only data clocks for QDR II, QDR II+, and QDR II+Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, butmust be placed on a differential pin pair. They must be placed in the same I/Obank as the corresponding DQS : For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced toDK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.12. For protocols and topologies with bidirectional data pins where a write data groupconsists of multiple read data groups, you should place the data groups and theirrespective write and read clock in the same bank to improve I/O do not need to specify the location of every data pin manually. If you assignthe location for the read capture strobe/clock pin pairs, the Fitter willautomatically place the remaining data Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/Opin and another in the pairing pin for that I/O pin. It is recommended though notrequired that you follow the same rule for DBI pins, so that at a later date youhave the freedom to repurpose the pin as : 1. x4 mode does not support DM/DBI, or Intel Stratix 10 EMIF IP for If you are using an Intel Stratix 10 EMIF IP-based RLDRAM 3 external memoryinterface, you should ensure that all the pins in a DQS group (that is, DQ, DM, DK,and QK) are placed in the same I/O bank. This requirement facilitates timingclosure and is necessary for successful compilation of your Interfaces in the Same I/O ColumnTo place multiple interfaces in the same I/O column, you must ensure that the globalreset signals (global_reset_n) for each individual interface all come from the sameinput pin or Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide333I/O Banks Selection For each memory interface, select consecutive I/O banks. (That is, select banksthat contain the same column number and letter before or after the respective I/Obank letter.) A memory interface can only span across I/O banks in the same I/O column. The number of I/O banks that you require depends on the memory interfacewidth. In some device packages, the number of I/O pins in some LVDS I/O banks is lessthat 48 Pins Location All address/command pins for a controller must be in a single I/O bank. If your interface uses multiple I/O banks, the address/command pins must use themiddle bank. If the number of banks used by the interface is even, any of the twomiddle I/O banks can be used for address/command pins. Address/command pins and data pins cannot share an I/O lane but can share anI/O bank. The address/command pin locations for the soft and hard memory controllers arepredefined. In the External Memory Interface Pin Information for Devicesspreadsheet, each index in the "Index within I/O bank" column denotes adedicated address/command pin function for a given protocol. The index numberof the pin specifies to which I/O lane the pin belongs: I/O lane 0 Pins with index 0 to 11 I/O lane 1 Pins with index 12 to 23 I/O lane 2 Pins with index 24 to 35 I/O lane 3 Pins with index 36 to 47 For memory topologies and protocols that require only three I/O lanes for theaddress/command pins, use I/O lanes 0, 1, and 2. Unused address/command pins in an I/O lane can be used as general-purpose Pins AssignmentAssign the clock pin (CK pin) according to the number of I/O banks in an interface: If the number of I/O banks is odd, assign one CK pin to the middle I/O bank. If the number of I/O banks is even, assign the CK pin to either of the middle twoI/O the Fitter can automatically select the required I/O banks, Intel recommendsthat you make the selection manually to reduce the pre-fit run Reference Clock Pin PlacementPlace the PLL reference clock pin in the address/command bank. Other I/O banks maynot have free pins that you can use as the PLL reference clock pin: If you are sharing the PLL reference clock pin between several interfaces, the I/Obanks must be adjacent. (That is, the banks must contain the same columnnumber and letter before or after the respective I/O bank letter.)9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide334The Intel Stratix 10 external memory interface IP does not support PLL Pin PlacementYou may place the RZQ pin in any I/O bank in an I/O column with the correct VCCIO andVCCPT for the memory interface I/O standard in use. However, the recommendedlocation is in the address/command I/O bank, for greater flexibility during debug if anarrower interface project is required for and DQS Pins AssignmentIntel recommends that you assign the DQS pins to the remaining I/O lanes in the I/Obanks as required: Constrain the DQ and DQS signals of the same DQS group to the same I/O lane. You cannot constrain DQ signals from two different DQS groups to the same you do not specify the DQS pins assignment, the Fitter selects the DQS an I/O Bank Across Multiple InterfacesIf you are sharing an I/O bank across multiple external memory interfaces, followthese guidelines: The interfaces must use the same protocol, voltage, data rate, frequency, and PLLreference clock. You cannot use an I/O bank as the address/command bank for more than oneinterface. The memory controller and sequencer cannot be shared. You cannot share an I/O lane. There is only one DQS input per I/O lane, and anI/O lane can connect to only one memory RLDRAM 3 Commands and AddressesThe CK and CK# signals clock the commands and addresses into the memory pins operate at single data rate using only one clock edge. RLDRAM 3 supportsboth non-multiplexed and multiplexed addressing. Multiplexed addressing allows youto save a few user I/O pins while non-multiplexed addressing allows you to send theaddress signal within one clock cycle instead of two clock cycles. CS#, REF#, and WE#pins are input commands to the RLDRAM 3 commands and addresses must meet the memory address and command setup(tAS, tCS) and hold (tAH, tCH) time : The RLDRAM 3 external memory interface IP does not support multiplexed RLDRAM 3 Clock SignalsRLDRAM 3 devices use CK and CK# signals to clock the command and address bus insingle data rate (SDR).There is one pair of CK and CK# pins per RLDRAM 3 of a strobe, RLDRAM 3 devices use two sets of free-running differential clocksto accompany the data. The DK and DK# clocks are the differential input data clocksused during writes while the QK or QK# clocks are the output data clocks used during9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide335reads. Even though QK and QK# signals are not differential signals according to theRLDRAM 3 data sheet, Micron treats these signals as such for their testing andcharacterization. Each pair of DK and DK#, or QK and QK# clocks are associated witheither 9 or 18 data exact clock-data relationships are as follows: RLDRAM 3: For 36 data bus width configuration, there are 18 data bitsassociated with each pair of write clocks. There are 9 data bits associated witheach pair of read clocks. So, there are two pairs of DK and DK# pins and four pairsof QK and QK# pins. RLDRAM 3: For 18 data bus width configuration, there are 9 data bits per onepair of write clocks and nine data bits per one pair of read clocks. So, there aretwo pairs of DK and DK# pins, and two pairs of QK and QK# pins RLDRAM 3: RLDRAM 3 does not have the 9 data bus width are tCKDK timing requirements for skew between CK and DK or CK# and DK#.For RLDRAM 3, because of the loads on these I/O pins, the maximum frequency youcan achieve depends on the number of memory devices you are connecting to theIntel device. Perform SPICE or IBIS simulations to analyze the loading effects of thepin-pair on multiple RLDRAM 3 RLDRAM 3 Data, DM and QVLD SignalsThe read data is edge-aligned with the QK or QK# clocks while the write data iscenter-aligned with the DK and DK# clocks (see the following figures).The memorycontroller shifts the DK and DK# signals to center align the DQ and DK or DK# signalsduring a write. It also shifts the QK signal during a read, so that the read data (DQsignals) and QK clock is center-aligned at the capture devices use dedicated DQS phase-shift circuitry to shift the incoming QK signalduring reads and use a PLL to center-align the DK and DK# signals with respect to theDQ signals during DQ and QK Relationship During RLDRAM 3 ReadQK atFPGA PinDQ atFPGA PinQK at DQLE RegistersDQ at DQLE RegistersDQS Phase Shift9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide336Figure DQ and DK Relationship During RLDRAM 3 WriteDK atFPGA PinDQ atFPGA PinFor RLDRAM 3, data mask (DM) pins are used only during a write. The memorycontroller drives the DM signal low when the write is valid and drives it high to maskthe DQ RLDRAM 3, there are two DM pins per memory device. DM0 is used to mask thelower byte for the x18 device and (DQ[8:0],DQ[26:18]) for the x36 device. DM1 isused to mask the upper byte for the x18 device and (DQ[17:9], DQ[35:27]) for thex36 DM timing requirements at the input to the memory device are identical to thosefor DQ data. The DDR registers, clocked by the write clock, create the DM signals. Thisreduces any skew between the DQ and DM RLDRAM 3 device's setup time (tDS) and hold (tDH) time for the write DQ and DMpins are relative to the edges of the DK or DK# clocks. The DK and DK# signals aregenerated on the positive edge of system clock, so that the positive edge of CK or CK#is aligned with the positive edge of DK or DK# respectively to meet the tCKDKrequirement. The DQ and DM signals are clocked using a shifted clock so that theedges of DK or DK# are center-aligned with respect to the DQ and DM signals whenthey arrive at the RLDRAM 3 clocks, data, and DM board trace lengths should be tightly matched to minimizethe skew in the arrival time of these 3 devices also have a QVLD pin indicating valid read data. The QVLD signal isedge-aligned with QK or QK# and is high approximately half a clock cycle before datais output from the : The Intel FPGA external memory interface IP does not use the QVLD Resource Sharing Guidelines (Multiple Interfaces)In Intel Cyclone 10Intel Stratix 10 external memory interface IP, different externalmemory interfaces can share PLL reference clock pins, core clock networks, I/O banks,and hard Nios processors. Each I/O bank has DLL and PLL resources, therefore thesedo not need to be shared. The Intel Quartus Prime Fitter automatically merges DLLand PLL resources when a bank is shared by different external memory interfaces, andduplicates them for a multi-I/O-bank external memory Reference Clock PinTo conserve pin usage and enable core clock network and I/O bank sharing, you canshare a PLL reference clock pin between multiple external memory interfaces; theinterfaces must be of the same protocol, rate, and frequency. Sharing of a PLLreference clock pin also implies sharing of the reference clock Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide337Observe the following guidelines for sharing the PLL reference clock share a PLL reference clock pin, connect the same signal to the pll_ref_clkport of multiple external memory interfaces in the RTL Place related external memory interfaces in the same I/O Place related external memory interfaces in adjacent I/O banks. If you leave anunused I/O bank between the I/O banks used by the external memory interfaces,that I/O bank cannot be used by any other external memory interface with adifferent PLL reference clock : You can place the pll_ref_clk pin in the address and command I/O bank or in adata I/O bank, there is no impact on timing. However, for greatest flexibility duringdebug (such as when creating designs with narrower interfaces), the recommendedplacement is in the address and command I/O Clock NetworkTo access all external memory interfaces synchronously and to reduce global clocknetwork usage, you may share the same core clock network with other externalmemory the following guidelines for sharing the core clock share a core clock network, connect the clks_sharing_master_out of themaster to the clks_sharing_slave_in of all slaves in the RTL Place related external memory interfaces in the same I/O Related external memory interface must have the same rate, memory clockfrequency, and PLL reference BankTo reduce I/O bank utilization, you may share an I/O Bank with other externalmemory the following guidelines for sharing an I/O Bank:1. Related external memory interfaces must have the same protocol, rate, memoryclock frequency, and PLL reference You cannot use a given I/O bank as the address and command bank for more thanone external memory You cannot share an I/O lane between external memory interfaces, but an unusedpin can serve as a general purpose I/O pin, of compatible voltage and Nios ProcessorAll external memory interfaces residing in the same I/O column will share the samehard Nios processor. The shared hard Nios processor calibrates the external memoryinterfaces Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User RLDRAM 3 Board Design GuidelinesThe following topics provide layout guidelines for you to improve your system's signalintegrity and to successfully implement an RLDRAM 3 following topics focus on the following key factors that affect signal integrity: I/O standards RLDRAM 3 configurations Signal terminations Printed circuit board (PCB) layout guidelinesI/O StandardsRLDRAM 3 interface signals use the following JEDEC I/O signalling standards:HSTL V and RLDRAM 3 IP defaults to HSTL V Class I outputs and HSTL V RLDRAM 3 ConfigurationsThe Intel Stratix 10 EMIF IP for RLDRAM 3 supports interfaces for CIO RLDRAM 3 withone or two devices. With two devices, the interface supports a width expansionconfiguration up to 72-bits. The termination and layout principles for SIO RLDRAM 3interfaces are similar to CIO RLDRAM 3, except that SIO RLDRAM 3 interfaces haveunidirectional data following figure shows the main signal connections between the FPGA and a singleCIO RLDRAM 3 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide339Figure with a Single CIO RLDRAM 3 ComponentFGPARLDRAM 3 DeviceZQRQDK/DKDQDMCK/CKA/BAWEREFQK/QKDQ DMCK/CKADDRESS/BANK ADDRESSWEREFCSQK/QKDK/DKCSRESET(2)(2)(3) (3)(3)(1)(5)(5)VTT or VDD(6)VTT or VDD(6)VTT(4)RESETNotes to external differential termination on CK/CK#. FPGA parallel on-chip termination (OCT) for terminating QK/QK# and DQ RLDRAM 3 component on-die termination (ODT) for terminating DQ, DM, andDK, DK# on Use external discrete termination with fly-by placement to avoid Use external discrete termination for this signal, as shown for Use external discrete termination, as shown for REF, but you may require a pull-upresistor to VDD as an alternative option. Refer to the RLDRAM 3 device data sheetfor more information about RLDRAM 3 power-up following figure shows the main signal connections between the FPGA and twoCIO RLDRAM 3 components in a width expansion Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide340Figure with Two CIO RLDRAM 3 Components in a Width ExpansionConfigurationCK/CKA/BA/REF/WECS Device 1 QK/QKDevice 2 QK/QKDevice 2 DK/DK(1)(1)(1)(1)Device 1 DQDevice 2 DQDevice 1 DMDevice 2 DMRLDRAM 3 Device 1ZQRQRLDRAM 3 Device 2ZQRQ(3)(2)(5)VTT or VDD(5)VTT or VDD(4)VTTDK/DKQK/QKDDMCK/CKA/BA/REF/WECS Device 1 DK/DKFPGADK/DKQK/QKDDMCSRESETRESETRESETC K/CKA/BA/REF/WE(2)(2)(2)(3)(3)(3)Notes to FPGA parallel OCT for terminating QK/QK# and DQ on RLDRAM 3 component ODT for terminating DQ, DM, and DK on Use external dual 200 differential Use external discrete termination at the trace split of the balanced T or Y Use external discrete termination at the trace split of the balanced T or Y topology,but you may require a pull-up resistor to VDD as an alternative option. Refer tothe RLDRAM 3 device data sheet for more information about RLDRAM 3 General Layout GuidelinesThe following table lists general board design layout guidelines. These guidelines areIntel recommendations, and should not be considered as hard requirements. Youshould perform signal integrity simulation on all the traces to verify the signal integrityof the interface. You should extract the slew rate and propagation delay information,enter it into the IP and compile the design to ensure that timing requirements Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide341Table Layout GuidelinesParameterGuidelinesImpedance All unused via pads must be removed, because they cause unwantedcapacitance. Trace impedance plays an important role in the signal integrity. You mustperform board level simulation to determine the best characteristic impedancefor your PCB. For example, it is possible that for multi rank systems 40 ohmscould yield better results than a traditional 50 ohm characteristic Parameter Use uF in 0402 size to minimize inductance Make VTT voltage decoupling close to termination resistors Connect decoupling caps between VTT and ground Use a uF cap for every other VTT pin and uF cap for every VDD andVDDQ pin Verify the capacitive decoupling using the Intel Power Distribution NetworkDesign ToolPower Route GND and VCC as planes Route VCCIO for memories in a single split plane with at least a 20-mil( inches, or mm) gap of separation Route VTT as islands or 250-mil ( ) power traces Route oscillators and PLL power as islands or 100-mil ( ) power tracesGeneral RoutingAll specified delay matching requirements include PCB trace delays, different layerpropagation velocity variance, and crosstalk. To minimize PCB layer propogationvariance, Intel recommends that signals from the same net group always berouted on the same layer. Use 45 angles (not 90 corners) Avoid T-Junctions for critical nets or clocks Avoid T-junctions greater than 250 mils ( mm) Disallow signals across split planes Restrict routing other signals close to system reset signals Avoid routing memory signals closer than inch ( mm) to PCI orsystem clocksRelated LinksPower Distribution RLDRAM 3 Layout GuidelinesThe following table lists the RLDRAM 3 general routing layout guidelines. Theseguidelines apply to Intel Stratix 10 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide342Table 3 Layout GuidelinesParameterGuidelinesGeneral Routing If you must route signals of the same net group on different layers with thesame impedance characteristic, simulate your worst case PCB trace tolerancesto ascertain actual propagation delay differences. Typical layer to layer tracedelay variations are of 15 ps/inch order. Avoid T-junctions greater than 150 ps. Match all signals within a given DQ group with a maximum skew of 10 ps androute on the same Routing Route clocks on inner layers with outer-layer run lengths held to under 150 ps. These signals should maintain a 10-mil ( mm) spacing from other nets. Clocks should maintain a length-matching between clock pairs of 5 ps. Differential clocks should maintain a length-matching between P and N signalsof 2 ps. Space between different clock pairs should be at least three times the spacebetween the traces of a differential and Command Routing To minimize crosstalk, route address, bank address, and command signals on adifferent layer than the data and data mask signals. Do not route the differential clock signals close to the address signals. Keep the distance from the pin on the RLDRAM 3 component to the stubtermination resistor (VTT) to less than 50 ps for the address/command signalgroup. Keep the distance from the pin on the RLDRAM 3 component to the fly-bytermination resistor (VTT) to less than 100 ps for the address/command Memory Routing Rules Apply the following parallelism rules for the RLDRAM 3 data/address/commandgroups: 4 mils for parallel runs < inch (approximately 1 spacing relative toplane distance). 5 mils for parallel runs < inch (approximately 1 spacing relative toplane distance). 10 mils for parallel runs between and inches (approximately 2 spacing relative to plane distance). 15 mils for parallel runs between and inch (approximately 3 spacing relative to plane distance).Maximum Trace Length Keep the maximum trace length of all signals from the FPGA to the RLDRAM 3components to 600 Matching GuidanceThe following layout approach is recommended, based on the precedingguidelines:1. If the RLDRAM 3 interface has multiple DQ groups ( 18 or 36 RLDRAM 3component or width expansion configuration), match all the DK/DK# andQK ,QK # clocks as tightly as possible to optimize the timing margins in the DK/DK# write clock and QK/QK# read clock associated with a DQgroup on the same PCB layer. Match these clock pairs to within 5 the DK/DK# or QK/QK# clock as the target trace propagation delay for theassociated data and data mask Route the data and data mask signals for the DQ group ideally on the samelayer as the associated QK/QK# and DK/DK# clocks to within 10 ps skew ofthe target the CK/CK# clocks and set as the target trace propagation delays for theaddress/command signal group. Match the CK/CK# clock to within 50 ps ofall the DK/DK# the address/control signal group (address, bank address, CS, WE, andREF) ideally on the same layer as the CK/CK# clocks, to within 20 ps skew ofthe CK/CK# 9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide343ParameterGuidelinesNote: It is important to match the delays of CK vs. DK, and CK vs. Addr-Cmd asmuch as layout approach provides a good starting point for a design requirement ofthe highest clock frequency supported for the RLDRAM 3 Layout ApproachFor all practical purposes, you can regard the Timing Analyzer report on your memoryinterface as definitive for a given set of memory and board timing will find timing under Report DDR in the Timing Analyzer and on the TimingAnalysis tab in the parameter following flowchart illustrates the recommended process to follow during theboard design phase, to determine timing margin and make iterative improvements toyour LayoutCalculate Setupand Hold DeratingCalculate ChannelSignal IntegrityCalculate BoardSkewsFind MemoryTiming ParametersGenerate an IP Core that Accurately Represents Your Memory Subsystem, Including pin-out and Accurate Parameters in the Parameter Editor s Board Settings TabRun Quartus Prime Compilation with the Generated IP CoreAny Non-Core TimingViolations in the ReportDDR Panel?yesnoDoneAdjust Layout to Improve: Trace Length Mis-Match Signal Reflections (ISI) Cross Talk Memory Speed GradeBoard SkewFor information on calculating board skew parameters, refer to Board Skew Equations,in this Board Skew Parameter Tool is an interactive tool that can help you calculate boardskew parameters if you know the absolute delay values for all the memory Timing ParametersFor information on the memory timing parameters to be entered into the parametereditor, refer to the datasheet for your external memory Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide344Related LinksBoard Skew Parameter Package DeskewYou should follow Intel's package deskew LinksPackage Deskew9 Intel Stratix 10 EMIF IP for RLDRAM 3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide34510 Intel Stratix 10 EMIF IP for LPDDR3This chapter contains IP parameter descriptions, board skew equations, pin planninginformation, and board design guidance for Intel Stratix 10 external memoryinterfaces for Parameter DescriptionsThe following topics describe the parameters available on each tab of the IP parametereditor, which you can use to configure your Intel Stratix 10 EMIF IP LPDDR3 Parameters: GeneralTable : General / InterfaceDisplay NameDescriptionConfigurationSpecifies the configuration of the memory interface. The available optionsdepend on the protocol in use. Options include Hard PHY and HardController, Hard PHY and Soft Controller, or Hard PHY only. If youselect Hard PHY only, the AFI interface is exported to allow connection ofa custom memory controller or third-party IP. (Identifier:PHY_LPDDR3_CONFIG_ENUM)Table : General / ClocksDisplay NameDescriptionMemory clock frequencySpecifies the operating frequency of the memory interface in MHz. If youchange the memory frequency, you should update the memory latencyparameters on the Memory tab and the memory timing parameters on theMem Timing tab. (Identifier: PHY_LPDDR3_MEM_CLK_FREQ_MHZ)Use recommended PLL reference clockfrequencySpecifies that the PLL reference clock frequency is automatically calculatedfor best performance. If you want to specify a different PLL reference clockfrequency, uncheck the check box for this parameter. (Identifier:PHY_LPDDR3_DEFAULT_REF_CLK_FREQ)PLL reference clock frequencyThis parameter tells the IP what PLL reference clock frequency the user willsupply. Users must select a valid PLL reference clock frequency from thelist. The values in the list can change when the memory interface frequencychanges and/or the clock rate of user logic changes. It is recommended touse the fastest possible PLL reference clock frequency because it leads tobetter jitter performance. Selection is required only if the user does notcheck the "Use recommended PLL reference clock frequency" option.(Identifier: PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ) UG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008RegisteredDisplay NameDescriptionPLL reference clock jitterSpecifies the peak-to-peak jitter on the PLL reference clock source. Theclock source of the PLL reference clock must meet or exceed the followingjitter requirements: 10ps peak to peak, or RMS at 1e-12 BER, at 1e-16 BER. (Identifier: PHY_LPDDR3_REF_CLK_JITTER_PS)Clock rate of user logicSpecifies the relationship between the user logic clock frequency and thememory clock frequency. For example, if the memory clock sent from theFPGA to the memory device is toggling at 800MHz, a quarter-rate interfacemeans that the user logic in the FPGA runs at 200MHz. (Identifier:PHY_LPDDR3_RATE_ENUM)Core clocks sharingWhen a design contains multiple interfaces of the same protocol, rate,frequency, and PLL reference clock source, they can share a common set ofcore clock domains. By sharing core clock domains, they reduce clocknetwork usage and avoid clock synchronization logic between share core clocks, denote one of the interfaces as "Master", and theremaining interfaces as "Slave". In the RTL, connect theclks_sharing_master_out signal from the master interface to theclks_sharing_slave_in signal of all the slave master and slave interfaces still expose their own output clock ports inthe RTL (for example, emif_usr_clk, afi_clk), but the physical signalsare equivalent, hence it does not matter whether a clock port from a masteror a slave is used. As the combined width of all interfaces sharing the samecore clock increases, you may encounter timing closure difficulty fortransfers between the FPGA core and the periphery.(Identifier: PHY_LPDDR3_CORE_CLKS_SHARING_ENUM)Specify additional core clocks based onexisting PLLDisplays additional parameters allowing you to create additional outputclocks based on the existing PLL. This parameter provides an alternativeclock-generation mechanism for when your design exhaustsavailable PLL resources. The additional output clocks that you create canbe fed into the core. Clock signals created with this parameter aresynchronous to each other, but asynchronous to the memory interface coreclock domains (such as emif_usr_clk or afi_clk). You must followproper clock-domain-crossing techniques when transferring data betweenclock domains. (Identifier: PLL_ADD_EXTRA_CLKS)Table : General / Clocks / Additional Core ClocksDisplay NameDescriptionNumber of additional core clocksSpecifies the number of additional output clocks to create from the PLL.(Identifier: PLL_USER_NUM_OF_EXTRA_CLKS)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_0Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_1Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6)10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide347Table : General / Clocks / Additional Core Clocks / pll_extra_clk_2Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7)Table : General / Clocks / Additional Core Clocks / pll_extra_clk_3Display NameDescriptionFrequencySpecifies the frequency of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8)Phase shiftSpecifies the phase shift of the core clock signal. (Identifier:PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8) Intel Stratix 10 EMIF IP LPDDR3 Parameters: MemoryTable : Memory / TopologyDisplay NameDescriptionDQ widthTotal number of DQ pins in the interface. (Identifier:MEM_LPDDR3_DQ_WIDTH)Number of clocksNumber of CK/CK# clock pairs exposed by the memory interface.(Identifier: MEM_LPDDR3_CK_WIDTH)Number of chip selectsTotal number of chip selects in the interface. (Identifier:MEM_LPDDR3_DISCRETE_CS_WIDTH)Row address widthThe number of row address bits. (Identifier:MEM_LPDDR3_ROW_ADDR_WIDTH)Column address widthThe number of column address bits. (Identifier:MEM_LPDDR3_COL_ADDR_WIDTH)Bank address widthThe number of bank address bits. (Identifier:MEM_LPDDR3_BANK_ADDR_WIDTH)Enable DM pinsIndicates whether interface uses data mask (DM) pins. This feature allowsspecified portions of the data bus to be written to memory (not available inx4 mode). One DM pin exists per DQS group. (Identifier:MEM_LPDDR3_DM_EN)Table : Memory / Latency and BurstDisplay NameDescriptionData latencyDetermines the mode register setting that controls the data latency. Setsboth READ and WRITE latency (RL and WL). (Identifier:MEM_LPDDR3_DATA_LATENCY)Burst lengthBurst length of the memory device. (Identifier: MEM_LPDDR3_BL) Intel Stratix 10 EMIF IP LPDDR3 Parameters: Mem I/O10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide348Table : Mem I/O / Memory I/O SettingsDisplay NameDescriptionOutput drive strength settingSpecifies the output driver impedance setting at the memory device.(Identifier: MEM_LPDDR3_DRV_STR)DQ ODTThe ODT setting for the DQ pins during writes. (Identifier:MEM_LPDDR3_DQODT)Power down ODTTurn on turn off ODT during power down. (Identifier:MEM_LPDDR3_PDODT)Table : Mem I/O / ODT ActivationDisplay NameDescriptionUse Default ODT Assertion TablesEnables the default ODT assertion pattern as determined from vendorguidelines. These settings are provided as a default only; you shouldsimulate your memory interface to determine the optimal ODT settings andassertion patterns. (Identifier: MEM_LPDDR3_USE_DEFAULT_ODT) Intel Stratix 10 EMIF IP LPDDR3 Parameters: FPGA I/OYou should use Hyperlynx* or similar simulators to determine the best settings foryour board. Refer to the EMIF Simulation Guidance wiki page for : FPGA I/O / FPGA I/O SettingsDisplay NameDescriptionVoltageThe voltage level for the I/O pins driving the signals between the memorydevice and the FPGA memory interface. (Identifier:PHY_LPDDR3_IO_VOLTAGE)Periodic OCT re-calibrationSpecifies that the system periodically recalibrate on-chip termination (OCT)to minimize variations in termination value caused by changing operatingconditions (such as changes in temperature). By recalibrating OCT, I/Otiming margins are improved. When enabled, this parameter causes thePHY to halt user traffic about every seconds for about 1900 memoryclock cycles, to perform OCT recalibration. Efficiency is reduced byabout 1% when this option is enabled. (Identifier:PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM)Use default I/O settingsSpecifies that a legal set of I/O settings are automatically selected. Thedefault I/O settings are not necessarily optimized for a specific board. Toachieve optimal signal integrity, perform I/O simulations with IBIS modelsand enter the I/O settings manually, based on simulation results.(Identifier: PHY_LPDDR3_DEFAULT_IO)10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide349Table : FPGA I/O / FPGA I/O Settings / Address/CommandDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the address/command pins of thememory interface. The selected I/O standard configures the circuit withinthe I/O buffer to match the industry standard. (Identifier:PHY_LPDDR3_USER_AC_IO_STD_ENUM)Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_LPDDR3_USER_AC_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM)Table : FPGA I/O / FPGA I/O Settings / Memory ClockDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the memory clock pins. Theselected I/O standard configures the circuit within the I/O buffer to matchthe industry standard. (Identifier: PHY_LPDDR3_USER_CK_IO_STD_ENUM)Output modeThis parameter allows you to change the current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_LPDDR3_USER_CK_MODE_ENUM)Slew rateSpecifies the slew rate of the address/command output pins. The slew rate(or edge rate) describes how quickly the signal can transition, measured involtage per unit time. Perform board simulations to determine the slew ratethat provides the best eye opening for the address and command signals.(Identifier: PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM)Table : FPGA I/O / FPGA I/O Settings / Data BusDisplay NameDescriptionI/O standardSpecifies the I/O electrical standard for the data and data clock/strobe pinsof the memory interface. The selected I/O standard option configures thecircuit within the I/O buffer to match the industry standard. (Identifier:PHY_LPDDR3_USER_DATA_IO_STD_ENUM)Output modeThis parameter allows you to change the output current drive strength ortermination settings for the selected I/O standard. Perform boardsimulation with IBIS models to determine the best settings for your design.(Identifier: PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM)Input modeThis parameter allows you to change the input termination settings for theselected I/O standard. Perform board simulation with IBIS models todetermine the best settings for your design. (Identifier:PHY_LPDDR3_USER_DATA_IN_MODE_ENUM)Use recommended initial VrefinSpecifies that the initial Vrefin setting is calculated automatically, to areasonable value based on termination settings. (Identifier:PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN)Initial VrefinSpecifies the initial value for the reference voltage on the datapins(Vrefin). This value is entered as a percentage of the supply voltagelevel on the I/O pins. The specified value serves as a starting point and maybe overridden by calibration to provide better timing margins. If you chooseto skip Vref calibration (Diagnostics tab), this is the value that is usedas the Vref for the interface. (Identifier:PHY_LPDDR3_USER_STARTING_VREFIN)10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide350Table : FPGA I/O / FPGA I/O Settings / PHY InputsDisplay NameDescriptionPLL reference clock I/O standardSpecifies the I/O standard for the PLL reference clock of the memoryinterface. (Identifier: PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM)RZQ I/O standardSpecifies the I/O standard for the RZQ pin used in the memory interface.(Identifier: PHY_LPDDR3_USER_RZQ_IO_STD_ENUM) Intel Stratix 10 EMIF IP LPDDR3 Parameters: Mem TimingThese parameters should be read from the table in the datasheet associated with thespeed bin of the memory device (not necessarily the frequency at which the interfaceis running).Table : Mem Timing / Parameters dependent on Speed BinDisplay NameDescriptionSpeed binThe speed grade of the memory device used. This parameter refers to themaximum rate at which the memory device is specified to run. (Identifier:MEM_LPDDR3_SPEEDBIN_ENUM)tISCA (base)Address and control setup to CK clock rise (Identifier:MEM_LPDDR3_TIS_PS)tISCA (base) AC levelAC level of tIS (base) for derating purpose (Identifier:MEM_LPDDR3_TIS_AC_MV)tIHCA (base)Address and control hold after CK clock rise (Identifier:MEM_LPDDR3_TIH_PS)tIHCA (base) DC levelDC level of tIH (base) for derating purpose (Identifier:MEM_LPDDR3_TIH_DC_MV)tDS (base)tDS(base) refers to the setup time for the Data (DQ) bus before therising edge of the DQS strobe. (Identifier: MEM_LPDDR3_TDS_PS)tDS (base) AC leveltDS (base) AC level refers to the voltage level which the data bus mustcross and remain above during the setup margin window. The signalis considered stable only if it remains above this voltage level (for a logic 1)or below this voltage level (for a logic 0) for the entire setup period.(Identifier: MEM_LPDDR3_TDS_AC_MV)tDH (base)tDH (base) refers to the hold time for the Data (DQ) bus after the risingedge of CK. (Identifier: MEM_LPDDR3_TDH_PS)tDH (base) DC leveltDH (base) DC level refers to the voltage level which the data bus mustnot cross during the hold window. The signal is considered stable only ifit remains above this voltage level (for a logic 1) or below this voltage level(for a logic 0) for the entire hold period. (Identifier:MEM_LPDDR3_TDH_DC_MV)tDQSQtDQSQ describes the latest valid transition of the associated DQ pinsfor a READ. tDQSQ specifically refers to the DQS, DQS# to DQ skew. It isthe length of time between the DQS, DQS# crossing to the last validtransition of the slowest DQ pin in the DQ group associated with that DQSstrobe. (Identifier: MEM_LPDDR3_TDQSQ_PS)tQHtQH specifies the output hold time for the DQ in relation to DQS,DQS#. It is the length of time between the DQS, DQS# crossing to theearliest invalid transition of the fastest DQ pin in the DQ group associatedwith that DQS strobe. (Identifier: MEM_LPDDR3_TQH_CYC)tDQSCKDLAbsolute difference between any two tDQSCK measurements (within a bytelane) within a contiguous sequence of bursts within a 32ms rolling window(Identifier: MEM_LPDDR3_TDQSCKDL) 10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide351Display NameDescriptiontDQSS (max)First latching edge of DQS to associated clock edge (percentage of tCK)(Identifier: MEM_LPDDR3_TDQSS_CYC)tQSHtQSH refers to the differential High Pulse Width, which is measured as apercentage of tCK. It is the time during which the DQS is high for aread. (Identifier: MEM_LPDDR3_TQSH_CYC)tDSHtDSH specifies the write DQS hold time. This is the time differencebetween the rising CK edge and the falling edge of DQS, measured as apercentage of tCK. (Identifier: MEM_LPDDR3_TDSH_CYC)tWLStWLS describes the write leveling setup time. It is measured from therising edge of CK to the rising edge of DQS. (Identifier:MEM_LPDDR3_TWLS_PS)tWLHtWLH describes the write leveling hold time. It is measured from therising edge of DQS to the rising edge of CK. (Identifier:MEM_LPDDR3_TWLH_PS)tDSStDSS describes the time between the falling edge of DQS to the risingedge of the next CK transition. (Identifier: MEM_LPDDR3_TDSS_CYC)tINITtINIT describes the time duration of the memory initialization after adevice power-up. After RESET_n is de-asserted, wait for another 500usuntil CKE becomes active. During this time, the DRAM will start internalinitialization; this will be done independently of external clocks. (Identifier:MEM_LPDDR3_TINIT_US)tMRRtMRR describes the minimum MODE REGISTER READ command period.(Identifier: MEM_LPDDR3_TMRR_CK_CYC)tMRWtMRW describes the minimum MODE REGISTER WRITE command period.(Identifier: MEM_LPDDR3_TMRW_CK_CYC)tRAStRAS describes the activate to precharge duration. A row cannot bedeactivated until the tRAS time has been met. Therefore tRAS determineshow long the memory has to wait after a activate command before aprecharge command can be issued to close the row. (Identifier:MEM_LPDDR3_TRAS_NS)tRCDtRCD, row command delay, describes the active to read/write time. Itis the amount of delay between the activation of a row through the RAScommand and the access to the data through the CAS command.(Identifier: MEM_LPDDR3_TRCD_NS)tRPpbPrecharge command period (per bank) (Identifier: MEM_LPDDR3_TRP_NS)tWRtWR refers to the Write Recovery time. It specifies the amount of clockcycles needed to complete a write before a precharge command can beissued. (Identifier: MEM_LPDDR3_TWR_NS)10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide352Table : Mem Timing / Parameters dependent on Speed Bin, OperatingFrequency, and Page SizeDisplay NameDescriptiontRRDtRRD refers to the Row Active to Row Active Delay. It is the minimumtime interval (measured in memory clock cycles) between two activatecommands to rows in different banks in the same rank (Identifier:MEM_LPDDR3_TRRD_CYC)tFAWtFAW refers to the four activate window time. It describes the period oftime during which only four banks can be active. (Identifier:MEM_LPDDR3_TFAW_NS)tWTRtWTR or Write Timing Parameter describes the delay from start ofinternal write transaction to internal read command, for accesses tothe same bank. The delay is measured from the first rising memory clockedge after the last write data is received to the rising memory clock edgewhen a read command is received. (Identifier: MEM_LPDDR3_TWTR_CYC)tRTPtRTP refers to the internal READ Command to PRECHARGE Commanddelay. It is the number of memory clock cycles that is needed between aread command and a precharge command to the same rank. (Identifier:MEM_LPDDR3_TRTP_CYC)Table : Mem Timing / Parameters dependent on Density and TemperatureDisplay NameDescriptiontRFCabAuto-refresh command interval (all banks) (Identifier:MEM_LPDDR3_TRFC_NS)tREFItREFI refers to the average periodic refresh interval. It is the maximumamount of time the memory can tolerate in between each refresh command(Identifier: MEM_LPDDR3_TREFI_US) Intel Stratix 10 EMIF IP LPDDR3 Parameters: BoardTable : Board / Intersymbol Interference/CrosstalkDisplay NameDescriptionUse default ISI/crosstalk valuesYou can enable this option to use default intersymbol interference andcrosstalk values for your topology. Note that the default values are notoptimized for your board. For optimal signal integrity, it is recommendedthat you do not enable this parameter, but instead perform I/O simulationusing IBIS models and Hyperlynx)*, and manually enter values based onyour simulation results, instead of using the default values. (Identifier:BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES)Address and command ISI/crosstalkThe address and command window reduction due to intersymbolinterference and crosstalk effects. The number to be entered is the totalloss of margin on the setup and hold sides (measured loss on thesetup side + measured loss on the hold side). Refer to the EMIFSimulation Guidance wiki page for additional information. (Identifier:BOARD_LPDDR3_USER_AC_ISI_NS)Read DQS/DQS# ISI/crosstalkThe reduction of the read data window due to ISI and crosstalk effects onthe DQS/DQS# signal when driven by the memory device during a number to be entered is the total loss of margin on the setup andhold sides (measured loss on the setup side + measured loss on thehold side). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_LPDDR3_USER_RCLK_ISI_NS) 10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide353Display NameDescriptionRead DQ ISI/crosstalkThe reduction of the read data window due to intersymbol inteference andcrosstalk effects on the DQ signal when driven by the memory deviceduring a read. The number to be entered is the total loss of margin onthe setup and hold sides (measured loss on the setup side +measured loss on the hold side). Refer to the EMIF Simulation Guidancewiki page for additional information. (Identifier:BOARD_LPDDR3_USER_RDATA_ISI_NS)Write DQS/DQS# ISI/crosstalkThe reduction of the write data window due to intersymbol interference andcrosstalk effects on the DQS/DQS# signal when driven by the FPGA duringa write. The number to be entered is the total loss of margin on thesetup and hold sides (measured loss on the setup side + measuredloss on the hold side). Refer to the EMIF Simulation Guidance wiki pagefor additional information. (Identifier:BOARD_LPDDR3_USER_WCLK_ISI_NS)Write DQ ISI/crosstalkThe reduction of the write data window due to intersymbol interference andcrosstalk effects on the DQ signal when driven by the FPGA during a number to be entered is the total loss of margin on the setup andhold sides (measured loss on the setup side + measured loss on thehold side). Refer to the EMIF Simulation Guidance wiki page for additionalinformation. (Identifier: BOARD_LPDDR3_USER_WDATA_ISI_NS)Table : Board / Board and Package SkewsDisplay NameDescriptionPackage deskewed with board layout(DQS group)Enable this parameter if you are compensating for package skew on the DQ,DQS, and DM buses in the board layout. Include package skew incalculating the following board skew parameters. (Identifier:BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED)Maximum board skew within DQS groupThe largest skew between all DQ and DM pins in a DQS group. This valueaffects the read capture and write margins. (Identifier:BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS)Maximum system skew within DQSgroupThe largest skew between all DQ and DM pins in a DQS group. Entercombined board and package skew. This value affects the read capture andwrite margins. (Identifier:BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS)Package deskewed with board layout(address/command bus)Enable this parameter if you are compensating for package skew on theaddress, command, control, and memory clock buses in the board package skew in calculating the following board skewparameters. (Identifier:BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED)Maximum board skew within address/command busThe largest skew between the address and command signals. Enter theboard skew only; package skew is calculated automatically, based on thememory interface configuration, and added to this value. (Identifier:BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS)Maximum system skew within address/command busMaximum system skew within address/command bus refers to the largestskew between the address and command signals. (Identifier:BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS)Average delay difference between DQSand CKThe average delay difference between the DQS signals and the CK signal,calculated by averaging the longest and smallest DQS trace delay minus theCK trace delay. Positive values represent DQS signals that are longer thanCK signals and negative values represent DQS signals that are shorter thanCK signals. (Identifier: BOARD_LPDDR3_DQS_TO_CK_SKEW_NS)Maximum delay difference betweendevicesThis parameter describes the largest propagation delay on the DQ signalsbetween example, in a two-rank configuration where devices are placed in series,there is an extra propagation delay for DQ signals going to and coming backfrom the furthest device compared to the nearest device. This parameter isonly applicable when there is more than one 10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide354Display NameDescription(Identifier: BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS)Maximum skew between DQS groupsThe largest skew between DQS signals. (Identifier:BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS)Average delay difference betweenaddress/command and CKThe average delay difference between the address/command signals andthe CK signal, calculated by averaging the longest and smallest address/command signal trace delay minus the maximum CK trace delay. Positivevalues represent address and command signals that are longer than CKsignals and negative values represent address and command signals thatare shorter than CK signals. (Identifier:BOARD_LPDDR3_AC_TO_CK_SKEW_NS)Maximum CK delay to deviceThe maximum CK delay to device refers to the delay of the longest CK tracefrom the FPGA to any device. (Identifier:BOARD_LPDDR3_MAX_CK_DELAY_NS)Maximum DQS delay to deviceThe maximum DQS delay to device refers to the delay of the longest DQStrace from the FPGA to any device (Identifier:BOARD_LPDDR3_MAX_DQS_DELAY_NS) Intel Stratix 10 EMIF IP LPDDR3 Parameters: ControllerTable : Controller / Avalon InterfaceDisplay NameDescriptionAvalon InterfaceSelects the Avalon Interface through which the controller interacts with userlogic (Identifier: CTRL_LPDDR3_AVL_PROTOCOL_ENUM)Table : Controller / Low Power ModeDisplay NameDescriptionEnable Self-Refresh ControlSelect this option to enable the self-refresh control on the controller toplevel. The control signal allows you to place the memory device into self-refresh mode, on a per chip-select basis. (Identifier:CTRL_LPDDR3_SELF_REFRESH_EN)Enable Auto Power-DownEnable this parameter to have the controller automatically place thememory device into power-down mode after a specified number of idlecontroller clock cycles. The idle wait time is configurable. All ranks mustbe idle to enter auto power-down. (Identifier:CTRL_LPDDR3_AUTO_POWER_DOWN_EN)Auto Power-Down CyclesSpecifies the number of idle controller cycles after which the memorydevice is placed into power-down mode. You can configure the idle waitingtime. The supported range for number of cycles is from 1 to 65534.(Identifier: CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS)Table : Controller / EfficiencyDisplay NameDescriptionEnable User Refresh ControlWhen enabled, user logic has complete control and is responsible for issuingadaquate refresh commands to the memory devices, via the MMR feature provides increased control over worst-case read latency andenables you to issue refresh bursts during idle periods. (Identifier:CTRL_LPDDR3_USER_REFRESH_EN)Enable Auto-Precharge ControlSelect this parameter to enable the auto-precharge control on the controllertop level. If you assert the auto-precharge control signal while requesting aread or write burst, you can specify whether the controller should 10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide355Display NameDescription(auto-precharge) the currently open page at the end of the read or writeburst, potentially making a future access to a different page of the samebank faster. (Identifier: CTRL_LPDDR3_AUTO_PRECHARGE_EN)Address OrderingControls the mapping between Avalon addresses and memory deviceaddresses. By changing the value of this parameter, you can change themappings between the Avalon-MM address and the DRAM address.(Identifier: CTRL_LPDDR3_ADDR_ORDER_ENUM)Enable ReorderingEnable this parameter to allow the controller to perform command and datareordering. Reordering can improve efficiency by reducing busturnaround time and row/bank switching time. Data reordering allowsthe single-port memory controller to change the order of read and writecommands to achieve highest efficiency. Command reordering allows thecontroller to issue bank management commands early based on incomingpatterns, so that the desired row in memory is already open when thecommand reaches the memory interface. For more information, refer to theData Reordering topic in the EMIF Handbook. (Identifier:CTRL_LPDDR3_REORDER_EN)Starvation limit for each commandSpecifies the number of commands that can be served before awaiting command is served. The controller employs a counter to ensurethat all requests are served after a pre-defined interval -- this ensures thatlow priority requests are not ignored, when doing data reordering forefficiency. The valid range for this parameter is from 1 to 63. For moreinformation, refer to the Starvation Control topic in the EMIF Handbook.(Identifier: CTRL_LPDDR3_STARVE_LIMIT)Enable Command Priority ControlSelect this parameter to enable user-requested command priority control onthe controller top level. This parameter instructs the controller to treat aread or write request as high-priority. The controller attempts to fill high-priority requests sooner, to reduce latency. Connect this interface to theconduit of your logic block that determines when the externalmemory interface IP treats the read or write request as a high-priority command. (Identifier: CTRL_LPDDR3_USER_PRIORITY_EN)Table : Controller / Configuration, Status and Error HandlingDisplay NameDescriptionEnable Memory-Mapped Configurationand Status Register (MMR) InterfaceEnable this parameter to change or read memory timing parameters,memory address size, mode register settings, controller status, and requestsideband operations. (Identifier: CTRL_LPDDR3_MMR_EN)Table : Controller / Data Bus Turnaround TimeDisplay NameDescriptionAdditional read-to-write turnaroundtime (same rank)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a read to a write within the same logicalrank. This can help resolve bus contention problems specific to your boardtopology. The value is added to the default which is calculatedautomatically. Use the default setting unless you suspect a problem exists.(Identifier: CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS)Additional write-to-read turnaroundtime (same rank)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a write to a read within the same logicalrank. This can help resolve bus contention problems specific to your boardtopology. The value is added to the default which is calculatedautomatically. Use the default setting unless you suspect a problem exists.(Identifier: CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS)Additional read-to-read turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a read of one logical rank to a read ofanother logical rank. This can resolve bus contention problems specific 10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide356Display NameDescriptionyour board topology. The value is added to the default which is calculatedautomatically. Use the default setting unless you suspect a problem exists.(Identifier: CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS)Additional read-to-write turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a read of one logical rank to a write ofanother logical rank. This can help resolve bus contention problemsspecific to your board topology. The value is added to the default which iscalculated automatically. Use the default setting unless you suspect aproblem exists. (Identifier:CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS)Additional write-to-write turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a write of one logical rank to a write ofanother logical rank. This can help resolve bus contention problemsspecific to your board topology. The value is added to the default which iscalculated automatically. Use the default setting unless you suspect aproblem exists. (Identifier:CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS)Additional write-to-read turnaroundtime (different ranks)Specifies additional number of idle controller (not DRAM) cycles whenswitching the data bus from a write of one logical rank to a read ofanother logical rank. This can help resolve bus contention problemsspecific to your board topology. The value is added to the default which iscalculated automatically. Use the default setting unless you suspect aproblem exists. (Identifier:CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS) Intel Stratix 10 EMIF IP LPDDR3 Parameters: DiagnosticsTable : Diagnostics / Simulation OptionsDisplay NameDescriptionCalibration modeSpecifies whether to skip memory interface calibration duringsimulation, or to simulate the full calibration the full calibration process can take hours (or even days),depending on the width and depth of the memory interface. You canachieve much faster simulation times by skipping the calibration process,but that is only expected to work when the memory model is ideal and theinterconnect delays are you enable this parameter, the interface still performs some memoryinitialization before starting normal operations. Abstract PHY is supportedwith skip calibration.(Identifier: DIAG_LPDDR3_SIM_CAL_MODE_ENUM)Abstract phy for fast simulationSpecifies that the system use Abstract PHY for simulation. Abstract PHYreplaces the PHY with a model for fast simulation and can reducesimulation time by 2-3 times. Abstract PHY is available for certainprotocols and device families, and only when you select Skip Calibration.(Identifier: DIAG_LPDDR3_ABSTRACT_PHY)Table : Diagnostics / Calibration Debug OptionsDisplay NameDescriptionQuartus Prime EMIF Debug Toolkit/On-Chip Debug PortSpecifies the connectivity of an Avalon slave interface for use by theQuartus Prime EMIF Debug Toolkit or user core you set this parameter to "Disabled", no debug features are enabled. Ifyou set this parameter to "Export", an Avalon slave interface named"cal_debug" is exported from the IP. To use this interface with the EMIFDebug Toolkit, you must instantiate and connect an EMIF debug interface 10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide357Display NameDescriptioncore to it, or connect it to the cal_debug_out interface of another EMIFcore. If you select "Add EMIF Debug Interface", an EMIF debug interfacecomponent containing a JTAG Avalon Master is connected to the debug port,allowing the core to be accessed by the EMIF Debug one EMIF debug interface should be instantiated per I/O column. Youcan chain additional EMIF or PHYLite cores to the first by enabling the"Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option for all cores in the chain, and selecting "Export"for the "Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port"option on all cores after the first.(Identifier: DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE)Use Soft NIOS Processor for On-ChipDebugEnables a soft Nios processor as a peripheral component to access the On-Chip Debug Port. Only one interface in a column can activate this option.(Identifier: DIAG_SOFT_NIOS_MODE)Enable Daisy-Chaining for QuartusPrime EMIF Debug Toolkit/On-ChipDebug PortSpecifies that the IP export an Avalon-MM master interface(cal_debug_out) which can connect to the cal_debug interface of otherEMIF cores residing in the same I/O column. This parameter applies onlyif the EMIF Debug Toolkit or On-Chip Debug Port is enabled. Refer tothe Debugging Multiple EMIFs wiki page for more information aboutdebugging multiple EMIFs. (Identifier:DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER)Interface IDIdentifies interfaces within the I/O column, for use by the EMIF DebugToolkit and the On-Chip Debug Port. Interface IDs should be unique amongEMIF cores within the same I/O column. If the Quartus Prime EMIFDebug Toolkit/On-Chip Debug Port parameter is set to Disabled, theinterface ID is unused. (Identifier: DIAG_LPDDR3_INTERFACE_ID)Skip address/command levelingcalibrationSpecifies to skip the address/command leveling stage during leveling attempts to center the memory clock edgeagainst CS# by adjusting delay elements inside the PHY, and then applyingthe same delay offset to the rest of the address and command pins.(Identifier: DIAG_LPDDR3_SKIP_CA_LEVEL)Skip address/command deskewcalibrationSpecifies to skip the address/command deskew calibration stage. Address/command deskew performs per-bit deskew for the address and commandpins. (Identifier: DIAG_LPDDR3_SKIP_CA_DESKEW)Table : Diagnostics / Example DesignDisplay NameDescriptionNumber of core clocks sharing slaves toinstantiate in the example designSpecifies the number of core clock sharing slaves to instantiate in theexample design. This parameter applies only if you set the "Core clockssharing" parameter in the "General" tab to "Master" or "Slave".(Identifier: DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES)Enable In-System-Sources-and-ProbesEnables In-System-Sources-and-Probes in the example design for commondebug signals, such as calibration status or example traffic generator per-bit status. This parameter must be enabled if you want to do drivermargining. (Identifier: DIAG_LPDDR3_EX_DESIGN_ISSP_EN)Table : Diagnostics / Traffic GeneratorDisplay NameDescriptionUse configurable Avalon trafficgenerator option allows users to add the new configurable Avalon trafficgenerator to the example design. (Identifier:DIAG_LPDDR3_USE_TG_AVL_2)Export Traffic Generator interfaceSpecifies that the IP export an Avalon-MM slave port for configuring theTraffic Generator. This is required only if you are configuring the trafficgenerator through user logic and not through through the EMIF DebugToolkit. (Identifier: DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE) 10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide358Display NameDescriptionBypass the default traffic patternSpecifies that the controller/interface bypass the traffic generator pattern after reset. If you do not enable this parameter, the trafficgenerator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN)Bypass the user-configured traffic stageSpecifies that the controller/interface bypass the user-configured trafficgenerator's pattern after reset. If you do not enable this parameter, thetraffic generator does not assert a pass or fail status until the generator isconfigured and signaled to start by its Avalon configuration can be done by connecting to the traffic generator via theEMIF Debug Toolkit, or by using custom logic connected to the Avalon-MMconfiguration slave port on the traffic generator. Configuration can also besimulated using the example testbench provided in file.(Identifier: DIAG_LPDDR3_BYPASS_USER_STAGE)Bypass the traffic generator repeated-writes/repeated-reads test patternSpecifies that the controller/interface bypass the traffic generator's repeattest stage. If you do not enable this parameter, every write and read isrepeated several times. (Identifier:DIAG_LPDDR3_BYPASS_REPEAT_STAGE)Bypass the traffic generator stresspatternSpecifies that the controller/interface bypass the traffic generator's stresspattern stage. (Stress patterns are meant to create worst-case signalintegrity patterns on the data pins.) If you do not enable this parameter,the traffic generator does not assert a pass or fail status until the generatoris configured and signaled to start by its Avalon configuration interface.(Identifier: DIAG_LPDDR3_BYPASS_STRESS_STAGE)Table : Diagnostics / PerformanceDisplay NameDescriptionEnable Efficiency MonitorAdds an Efficiency Monitor component to the Avalon-MM interface of thememory controller, allowing you to view efficiency statistics of the can access the efficiency statistics using the EMIF Debug Toolkit.(Identifier: DIAG_LPDDR3_EFFICIENCY_MONITOR)Table : Diagnostics / MiscellaneousDisplay NameDescriptionUse short Qsys interface namesSpecifies the use of short interface names, for improved usability andconsistency with other Qsys components. If this parameter is disabled, thenames of Qsys interfaces exposed by the IP will include the type anddirection of the interface. Long interface names are supported forbackward-compatibility and will be removed in a future release. (Identifier:SHORT_QSYS_INTERFACE_NAMES) Intel Stratix 10 EMIF IP LPDDR3 Parameters: Example DesignsTable : Example Designs / Available Example DesignsDisplay NameDescriptionSelect designSpecifies the creation of a full Quartus Prime project, instantiating anexternal memory interface and an example traffic generator, according toyour parameterization. After the design is created, you can specify thetarget device and pin location assignments, run a full compilation, verifytiming closure, and test the interface on your board using the programmingfile created by the Quartus Prime assembler. The 'Generate ExampleDesign' button lets you generate simulation or synthesis file sets.(Identifier: EX_DESIGN_GUI_LPDDR3_SEL_DESIGN)10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide359Table : Example Designs / Example Design FilesDisplay NameDescriptionSimulationSpecifies that the 'Generate Example Design' button create all necessaryfile sets for simulation. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, simulation file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the simulation example design, and file with other corresponding tcl files. You canrun from a command line to generate thesimulation example design. The generated example designs for varioussimulators are stored in the /sim sub-directory. (Identifier:EX_DESIGN_GUI_LPDDR3_GEN_SIM)SynthesisSpecifies that the 'Generate Example Design' button create all necessaryfile sets for synthesis. Expect a short additional delay as the file set iscreated. If you do not enable this parameter, synthesis file sets are notcreated. Instead, the output directory will contain the filewhich holds Qsys details of the synthesis example design, and script with other corresponding tcl files. You canrun from a command line to generate thesynthesis example design. The generated example design is stored inthe /qii sub-directory. (Identifier:EX_DESIGN_GUI_LPDDR3_GEN_SYNTH)Table : Example Designs / Generated HDL FormatDisplay NameDescriptionSimulation HDL formatThis option lets you choose the format of HDL in which generatedsimulation files are created. (Identifier:EX_DESIGN_GUI_LPDDR3_HDL_FORMAT)Table : Example Designs / Target Development KitDisplay NameDescriptionSelect boardSpecifies that when you select a development kit with a memory module,the generated example design contains all settings and fixed pinassignments to run on the selected board. You must select a developmentkit preset to generate a working example design for the specifieddevelopment kit. Any IP settings not applied directly from a developmentkit preset will not have guaranteed results when testing the developmentkit. To exclude hardware support of the example design, select 'none' fromthe 'Select board' pull down menu. When you apply a development kitpreset, all IP parameters are automatically set appropriately to match theselected preset. If you want to save your current settings, you should do sobefore you apply the preset. You can save your settings under a differentname using File->Save as. (Identifier:EX_DESIGN_GUI_LPDDR3_TARGET_ DEV_KIT)10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Board Skew EquationsThe following table presents the underlying equations for the board skew Equations for LPDDR3 Board Skew ParametersTable Skew Parameter EquationsParameterDescription/EquationMa ximum CK delay toDIMM/deviceThe delay of the longest CK trace from the FPGA to any n is the number of memory clock and r is the number rank of DIMM/device. Forexample in dual-rank DIMM implementation, if there are 2 pairs of memory clocks in eachrank DIMM, the maximum CK delay is expressed by the following equation:maxCK1PathDelayrank1,CK2PathDel ayrank1,CK1PathDelayrank2,CK2PathDelayra nk2Maximum DQS delay toDIMM/deviceThe delay of the longest DQS trace from the FPGA to the n is the number of DQS and r isthe number of rank of DIMM/device. For example indual-rank DIMM implementation, if there are 2 DQS in each rank DIMM, the maximum DQSdelay is expressed by the following equation:maxDQS1PathDelayrank1,DQS2PathD elayrank1,DQS1PathDelayrank2,DQS2PathDel ayrank2Average delay differencebetween DQS and CKThe average delay difference between the DQS signals and the CK signal, calculated byaveraging the longest and smallest DQS delay minus the CK delay. Positive valuesrepresent DQS signals that are longer than CK signals and negative values represent DQSsignals that are shorter than CK signals. The Quartus Prime software uses this skew tooptimize the delay of the DQS signals for appropriate setup and hold ,mDQSm_rDelay CKn_rDelay+ minrminn,mDQSm_rDelay CKn_rDelay2Where n is the number of memory clock, m is the number of DQS, and r is the number ofrank of using discete components, the calculation differs slightly. Find the minimum andmaximum values for (DQS-CK) over all groups and then divide by 2. Calculate the (DQS-CK) for each DQS group, by using the appropriate CLK for that example, in a configuration with 5 x16 components, with each component having twoDQS groups: To find the minimum and maximum, calculate the minimum and maximum of(DQS0 CK0, DQS1 CK0, DQS2 CK1, DQS3 CK1, and so forth) and then divide theresult by Board skew withinDQS groupThe largest skew between all DQ and DM pins in a DQS group. Enter your board skew skew is calculated automatically, based on the memory interface configuration,and added to this value. This value affects the read capture and write minDQgMaximum skew betweenDQS groupsThe largest skew between DQS signals in different DQS 10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide361ParameterDescription/Equationgro upsMaxgDQSg groupsMingDQSgMaximum system skewwithin address/commandbusMaxAC MinACThe largest skew between the address and command signals. Enter combined board andpackage skew. In the case of a component, find the maximum address/command andminimum address/command values across all component address delay differencebetween address/commandand CKA value equal to the average of the longest and smallest address/command signal delays,minus the delay of the CK signal. The value can be positive or average delay difference between the address/command and CK is expressed by thefollowing equation: n=nn= 1LongestACPathDelay+ShortestACPathDelay2 CKnPathDelaynwhere n is the number of memory delay differencebetween DIMMs/devicesThe largest propagation delay on DQ signals betweek ranks. For example, in a two-rankconfiguration where you place DIMMs in different slots there is also a propagation delay forDQ signals going to and coming back from the furthest DIMM compared to the nearestDIMM. This parameter is applicable only when there is more than one { maxn,m [(DQn_r path delay DQn_r+1 path delay), (DQSm_r path delay DQSm_r+1 path delay)]}Where n is the number of DQ, m is the number of DQS and r is number of rank of DIMM/device . Pin and Resource PlanningThe following topics provide guidelines on pin placement for external , all external memory interfaces require the following FPGA resources: Interface pins PLL and clock network Other FPGA resources for example, core fabric logic, and on-chip termination(OCT) calibration blocksOnce all the requirements are known for your external memory interface, you canbegin planning your Interface PinsAny I/O banks that do not support transceiver operations in Intel Stratix 10 devicessupport external memory interfaces. However, DQS (data strobe or data clock) andDQ (data) pins are listed in the device pin tables and are fixed at specific locations inthe device. You must adhere to these pin locations to optimize routing, minimize skew,and maximize margins. Always check the pin table for the actual locations of the DQSand DQ : Maximum interface width varies from device to device depending on the number ofI/O pins and DQS or DQ groups available. Achievable interface width also depends onthe number of address and command pins that the design requires. To ensureadequate PLL, clock, and device routing resources are available, you should alwaystest fit any IP in the Intel Quartus Prime Prime software before PCB Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide362Intel devices do not limit the width of external memory interfaces beyond thefollowing requirements: Maximum possible interface width in any particular device is limited by thenumber of DQS groups available. Sufficient clock networks are available to the interface PLL as required by the IP. Sufficient spare pins exist within the chosen bank or side of the device to includeall other address and command, and clock pin placement requirements. The greater the number of banks, the greater the skew, hence Intel recommendsthat you always generate a test project of your desired configuration and confirmthat it meets Estimating Pin RequirementsYou should use the Intel Quartus Prime software for final pin fitting. However, you canestimate whether you have enough pins for your memory interface using the EMIFDevice Selector on , or perform the following steps:1. Determine how many read/write data pins are associated per data strobe or Calculate the number of other memory interface pins needed, including any otherclocks (write clock or memory system clock), address, command, and RZQ. Referto the External Memory Interface Pin Table to determine necessary Address/Command/Clock pins based on your desired Calculate the total number of I/O banks required to implement the memoryinterface, given that an I/O bank supports up to 48 GPIO should test the proposed pin-outs with the rest of your design in the Intel QuartusPrime software (with the correct I/O standard and OCT connections) before finalizingthe pin-outs. There can be interactions between modules that are illegal in the IntelQuartus Prime software that you might not know about unless you compile the designand use the Intel Quartus Prime Pin LinksExternal Memory Interfaces Support Maximum Number of InterfacesThe maximum number of interfaces supported for a given memory protocol varies,depending on the FPGA in otherwise noted, the calculation for the maximum number of interfaces isbased on independent interfaces where the address or command pins are not : You may need to share PLL clock outputs depending on your clock network interface information for Intel Stratix 10, consult the EMIF Device Selector closure depends on device resource and routing utilization. For moreinformation about timing closure, refer to the Area and Timing OptimizationTechniques chapter in the Intel Quartus Prime Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide363Related Links External Memory Interfaces Support Center Intel Stratix 10 EMIF Architecture: PLL Reference Clock Networks on page 20 External Memory Interface Device Selector Intel Quartus Prime Pro Edition FPGA ResourcesThe Intel FPGA memory interface IP uses FPGA fabric, including registers and theMemory Block to implement the memory OCT calibration block is used if you are using the FPGA OCT feature in thememory interface. The OCT calibration block uses a single pin (RZQ). You can selectany of the available OCT calibration block as you do not need to place this block in thesame bank or device side of your memory interface. The only requirement is that theI/O bank where you place the OCT calibration block uses the same VCCIO voltage asthe memory interface. You can share multiple memory interfaces with the same OCTcalibration block if the VCCIO voltage is the OCTIf the memory interface uses any FPGA OCT calibrated series, parallel, or dynamictermination for any I/O in your design, you need a calibration block for the OCTcircuitry. This calibration block is not required to be within the same bank or side ofthe device as the memory interface RZQ pin in Intel Stratix 10 devices can be used as a general purpose I/O pin whenit is not used to support OCT, provided the signal conforms to the bank PLLWhen using PLL for external memory interfaces, you must consider the followingguidelines: For the clock source, use the clock input pin specifically dedicated to the PLL thatyou want to use with your external memory interface. The input and output pinsare only fully compensated when you use the dedicated PLL clock input pin. If theclock source for the PLL is not a dedicated clock input pin for the dedicated PLL,you would need an additional clock network to connect the clock source to the PLLblock. Using additional clock network may increase clock jitter and degrade thetiming margin. Pick a PLL and PLL input clock pin that are located on the same side of the deviceas the memory interface pins. Share the DLL and PLL static clocks for multiple memory interfaces provided thecontrollers are on the same or adjacent side of the device and run at the samememory clock frequency. If your design uses a dedicated PLL to only generate a DLL input reference clock,you must set the PLL mode to No Compensation in the Intel Quartus Primesoftware to minimize the jitter, or the software forces this setting PLL does not generate other output, so it does not need to compensate forany clock Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Pin Guidelines for Intel Stratix 10 EMIF IPThe Intel Stratix 10 device contains up to three I/O columns that can be used byexternal memory Intel Stratix 10 I/O subsystem resides in the I/Ocolumns. Each column contains multiple I/O banks, each of which consists of four I/Olanes. An I/O lane is a group of twelve I/O I/O column, I/O bank, I/O lane, adjacent I/O bank, and pairing pin for everyphysical I/O pin can be uniquely identified using the Bank Number and Indexwithin I/O Bank values which are defined in each Intel Stratix 10 device pin-outfile. The numeric component of the Bank Number value identifies the I/O column,while the letter represents the I/O bank. The Index within I/O Bank value falls within one of the following ranges: 0 to11, 12 to 23, 24 to 35, or 36 to 47, and represents I/O lanes 1, 2, 3, and 4,respectively. The adjacent I/O bank is defined as the I/O bank with same column number butthe letter is either before or after the respective I/O bank letter in the A-Z system. The pairing pin for an I/O pin is located in the same I/O bank. You can identify thepairing pin by adding one to its Index within I/O Bank number (if it is aneven number), or by subtracting one from its Index within I/O Bank number(if it is an odd number).For example, a physical pin with a Bank Number of 2M and Index within I/OBank of 22, indicates that the pin resides in I/O lane 2, in I/O bank 2M, in column adjacent I/O banks are 2L and 2N. The pairing pin for this physical pin is the pinwith an Index within I/O Bank of 23 and Bank Number of General GuidelinesYou should follow the recommended guidelines when performing pin placement for allexternal memory interface pins targeting Intel Stratix 10 devices, whether you areusing the hard memory controller or your own you are using the hard memory controller, you should employ the relative pinlocations defined in the <variation_name>/altera_emif_arch_nd_versionnumber/<synth|sim>/<variation_name>_altera_emif_arch_nd_versionnumber_<unique ID> file, w+ted with your : 1. EMIF IP pin-out requirements for the Intel Stratix 10 Hard Processor Subsystem(HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IPdefines a fixed pin-out in the Intel Quartus Prime IP file (.qip), based on the IPconfiguration. When targeting Intel Stratix 10 HPS, you do not need to makelocation assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the IntelQuartus Prime software. Alternatively, consult the device handbook or the devicepin-out files. For information on how you can customize the HPS EMIF pin-out,refer to Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP with Ping Pong PHY, PHY only, RLDRAMx , QDRx and LPDDR3 are not supported Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide365Observe the following general guidelines when placing pins for your Intel Stratix 10external memory interface:1. Ensure that the pins of a single external memory interface reside within a singleI/O An external memory interface can occupy one or more banks in the same I/Ocolumn. When an interface must occupy multiple banks, ensure that those banksare adjacent to one Any pin in the same bank that is not used by an external memory interface isavailable for use as a general purpose I/O of compatible voltage and All address and command pins and their associated clock pins (CK and CK#) mustreside within a single bank. The bank containing the address and command pins isidentified as the address and command To minimize latency, when the interface uses more than two banks, you mustselect the center bank of the interface as the address and command The address and command pins and their associated clock pins in the address andcommand bank must follow a fixed pin-out scheme, as defined in the Intel Stratix10 External Memory Interface Pin Information File, which is available do not have to place every address and command pin manually. If you assignthe location for one address and command pin, the Fitter automatically places theremaining address and command : The pin-out scheme is a hardware requirement that you must follow, andcan vary according to the topology of the memory device. Some schemesrequire three lanes to implement address and command pins, while othersrequire four lanes. To determine which scheme to follow, refer to themessages window during parameterization of your IP, or to the<variation_name>/altera_emif_arch_nd_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nd_<version>_<uniqueID> file after you have generated your An unused I/O lane in the address and command bank can serve to implement adata group, such as a x8 DQS group. The data group must be from the samecontroller as the address and command An I/O lane must not be used by both address and command pins and data Place read data groups according to the DQS grouping in the pin table and PinPlanner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQand CQ# / QK and QK#) must reside at physical pins capable of functioning asDQS/CQ and DQSn/CQn for a specific read data group size. You must place theassociated read data pins (such as DQ and Q), within the same Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide366Note: other device families, there is no need to swap CQ/CQ# pins incertain QDR II and QDR II+ latency requires that the polarity of all QKB/QKB# pins be swapped withrespect to the polarity of the differential buffer inputs on the FPGA toensure correct data capture on port B. All QKB pins on the memorydevice must be connected to the negative pins of the input buffers onthe FPGA side, and all QKB# pins on the memory device must beconnected to the positive pins of the input buffers on the FPGA that the port names at the top-level of the IP already reflect thisswap (that is, mem_qkb is assigned to the negative buffer leg, andmem_qkb_n is assigned to the positive buffer leg).10. You can implement two x4 DQS groups with a single I/O lane. The pin tablespecifies which pins within an I/O lane can be used for the two pairs of DQS andDQS# signals. In addition, for x4 DQS groups you must observe the followingrules: There must be an even number of x4 groups in an external memory interface. DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly,DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS groupX and DQS group X+1 must be in the same I/O lane, where X is an You should place the write data groups according to the DQS grouping in the pintable and Pin Planner. Output-only data clocks for QDR II, QDR II+, and QDR II+Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, butmust be placed on a differential pin pair. They must be placed in the same I/Obank as the corresponding DQS : For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced toDK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.12. For protocols and topologies with bidirectional data pins where a write data groupconsists of multiple read data groups, you should place the data groups and theirrespective write and read clock in the same bank to improve I/O do not need to specify the location of every data pin manually. If you assignthe location for the read capture strobe/clock pin pairs, the Fitter willautomatically place the remaining data Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/Opin and another in the pairing pin for that I/O pin. It is recommended though notrequired that you follow the same rule for DBI pins, so that at a later date youhave the freedom to repurpose the pin as : 1. x4 mode does not support DM/DBI, or Intel Stratix 10 EMIF IP for If you are using an Intel Stratix 10 EMIF IP-based RLDRAM 3 external memoryinterface, you should ensure that all the pins in a DQS group (that is, DQ, DM, DK,and QK) are placed in the same I/O bank. This requirement facilitates timingclosure and is necessary for successful compilation of your Interfaces in the Same I/O ColumnTo place multiple interfaces in the same I/O column, you must ensure that the globalreset signals (global_reset_n) for each individual interface all come from the sameinput pin or Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide367I/O Banks Selection For each memory interface, select consecutive I/O banks. (That is, select banksthat contain the same column number and letter before or after the respective I/Obank letter.) A memory interface can only span across I/O banks in the same I/O column. The number of I/O banks that you require depends on the memory interfacewidth. In some device packages, the number of I/O pins in some LVDS I/O banks is lessthat 48 Pins Location All address/command pins for a controller must be in a single I/O bank. If your interface uses multiple I/O banks, the address/command pins must use themiddle bank. If the number of banks used by the interface is even, any of the twomiddle I/O banks can be used for address/command pins. Address/command pins and data pins cannot share an I/O lane but can share anI/O bank. The address/command pin locations for the soft and hard memory controllers arepredefined. In the External Memory Interface Pin Information for Devicesspreadsheet, each index in the "Index within I/O bank" column denotes adedicated address/command pin function for a given protocol. The index numberof the pin specifies to which I/O lane the pin belongs: I/O lane 0 Pins with index 0 to 11 I/O lane 1 Pins with index 12 to 23 I/O lane 2 Pins with index 24 to 35 I/O lane 3 Pins with index 36 to 47 For memory topologies and protocols that require only three I/O lanes for theaddress/command pins, use I/O lanes 0, 1, and 2. Unused address/command pins in an I/O lane can be used as general-purpose Pins AssignmentAssign the clock pin (CK pin) according to the number of I/O banks in an interface: If the number of I/O banks is odd, assign one CK pin to the middle I/O bank. If the number of I/O banks is even, assign the CK pin to either of the middle twoI/O the Fitter can automatically select the required I/O banks, Intel recommendsthat you make the selection manually to reduce the pre-fit run Reference Clock Pin PlacementPlace the PLL reference clock pin in the address/command bank. Other I/O banks maynot have free pins that you can use as the PLL reference clock pin: If you are sharing the PLL reference clock pin between several interfaces, the I/Obanks must be adjacent. (That is, the banks must contain the same columnnumber and letter before or after the respective I/O bank letter.)10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide368The Intel Stratix 10 external memory interface IP does not support PLL Pin PlacementYou may place the RZQ pin in any I/O bank in an I/O column with the correct VCCIO andVCCPT for the memory interface I/O standard in use. However, the recommendedlocation is in the address/command I/O bank, for greater flexibility during debug if anarrower interface project is required for and DQS Pins AssignmentIntel recommends that you assign the DQS pins to the remaining I/O lanes in the I/Obanks as required: Constrain the DQ and DQS signals of the same DQS group to the same I/O lane. You cannot constrain DQ signals from two different DQS groups to the same you do not specify the DQS pins assignment, the Fitter selects the DQS an I/O Bank Across Multiple InterfacesIf you are sharing an I/O bank across multiple external memory interfaces, followthese guidelines: The interfaces must use the same protocol, voltage, data rate, frequency, and PLLreference clock. You cannot use an I/O bank as the address/command bank for more than oneinterface. The memory controller and sequencer cannot be shared. You cannot share an I/O lane. There is only one DQS input per I/O lane, and anI/O lane can connect to only one memory LPDDR3 Clock SignalCK and CKn are differential clock inputs to the LPDDR3 the double datarate (DDR) inputs are sampled on both the positive and negative edges of the data rate (SDR) inputs, CSn and CKE, are sampled at the positive clock clock is defined as the differential pair which consists of CK and CKn. The positiveclock edge is defined by the cross point of a rising CK and a falling CKn. The negativeclock edge is defined by the cross point of a falling CK and a rising SDRAM data sheet specifies timing data for the following: tDSH is the DQS falling edge hold time from CK. tDSS is the DQS falling edge to the CK setup time. tDQSS is the Write command to the first DQS latching transition. tDQSCK is the DQS output access time from Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User LPDDR3 Command and Address SignalAll LPDDR3 devices use double data rate architecture on the command/address bus toreduce the number of input pins in the 10-bit command/address buscontains command, address, and bank/row buffer information. Each command usesone clock cycle, during which command information is transferred on both the positiveand negative edges of the LPDDR3 Data, Data Strobe, and DM SignalsLPDDR3 devices use bidirectional and differential data DQS operation enables improved system timing due to reduced crosstalkand less simultaneous switching noise on the strobe output drivers. The DQ pins arealso bidirectional. DQS is edge-aligned with the read data and centered with the is the input mask for the write data signal. Input data is masked when DM issampled high coincident with that input data during a write Resource Sharing Guidelines (Multiple Interfaces)In Intel Cyclone 10Intel Stratix 10 external memory interface IP, different externalmemory interfaces can share PLL reference clock pins, core clock networks, I/O banks,and hard Nios processors. Each I/O bank has DLL and PLL resources, therefore thesedo not need to be shared. The Intel Quartus Prime Fitter automatically merges DLLand PLL resources when a bank is shared by different external memory interfaces, andduplicates them for a multi-I/O-bank external memory Reference Clock PinTo conserve pin usage and enable core clock network and I/O bank sharing, you canshare a PLL reference clock pin between multiple external memory interfaces; theinterfaces must be of the same protocol, rate, and frequency. Sharing of a PLLreference clock pin also implies sharing of the reference clock the following guidelines for sharing the PLL reference clock share a PLL reference clock pin, connect the same signal to the pll_ref_clkport of multiple external memory interfaces in the RTL Place related external memory interfaces in the same I/O Place related external memory interfaces in adjacent I/O banks. If you leave anunused I/O bank between the I/O banks used by the external memory interfaces,that I/O bank cannot be used by any other external memory interface with adifferent PLL reference clock : You can place the pll_ref_clk pin in the address and command I/O bank or in adata I/O bank, there is no impact on timing. However, for greatest flexibility duringdebug (such as when creating designs with narrower interfaces), the recommendedplacement is in the address and command I/O Clock NetworkTo access all external memory interfaces synchronously and to reduce global clocknetwork usage, you may share the same core clock network with other externalmemory Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide370Observe the following guidelines for sharing the core clock share a core clock network, connect the clks_sharing_master_out of themaster to the clks_sharing_slave_in of all slaves in the RTL Place related external memory interfaces in the same I/O Related external memory interface must have the same rate, memory clockfrequency, and PLL reference BankTo reduce I/O bank utilization, you may share an I/O Bank with other externalmemory the following guidelines for sharing an I/O Bank:1. Related external memory interfaces must have the same protocol, rate, memoryclock frequency, and PLL reference You cannot use a given I/O bank as the address and command bank for more thanone external memory You cannot share an I/O lane between external memory interfaces, but an unusedpin can serve as a general purpose I/O pin, of compatible voltage and Nios ProcessorAll external memory interfaces residing in the same I/O column will share the samehard Nios processor. The shared hard Nios processor calibrates the external memoryinterfaces LPDDR3 Board Design GuidelinesThe following topics provide guidelines for improving the signal integrity of yoursystem and for successfully implementing an LPDDR3 interface on your following areas are discussed: comparison of various types of termination schemes, and their effects on thesignal quality on the receiver proper drive strength setting on the FPGA to optimize the signal integrity at thereceiver effects of different loading types, such as components versus DIMM configuration,on signal qualityIt is important to understand the trade-offs between different types of terminationschemes, the effects of output drive strengths, and different loading types, so thatyou can swiftly navigate through the multiple combinations and choose the bestpossible settings for your following key factors affect signal quality at the receiver: Leveling and dynamic ODT Proper use of termination Layout guidelines10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide371As memory interface performance increases, board designers must pay closerattention to the quality of the signal seen at the receiver because poorly transmittedsignals can dramatically reduce the overall data-valid margin at the receiver. Thefollowing figure shows the differences between an ideal and real signal seen by and Real Signal at the ReceiverIdealRealVoltageVoltageVIHVIHVIL VILTimeTimeRelated Terminations for DDR3 and DDR4 with Intel Stratix 10 DevicesThe following topics describe considerations specific to DDR3 and DDR4 externalmemory interface protocols on Intel Stratix 10 Dynamic On-Chip Termination (OCT) in Intel Stratix 10 DevicesDepending upon the Rs (series) and Rt (parallel) OCT values that you want, youshould choose appropriate values for the RZQ resistor and connect this resistor to theRZQ pin of the FPGA. Select a 240-ohm reference resistor to ground to implement Rs OCT values of 34-ohm, 40-ohm, 48-ohm, 60-ohm, and 80-ohm, and Rt OCT resistance values of 20-ohm, 30-ohm, 34-ohm, 40-ohm, 60-ohm, 80-ohm, 120-ohm and 240 ohm. Select a 100-ohm reference resistor to ground to implement Rs OCT values of 25-ohm and 50-ohm, and an RT OCT resistance of the FPGA I/O tab of the parameter editor to determine the I/O standards andtermination values supported for data, address and command, and memory LinksChoosing Terminations on Intel Stratix 10 Devices on page Choosing Terminations on Intel Stratix 10 DevicesTo determine optimal on-chip termination (OCT) and on-die termination (ODT) valuesfor best signal integrity, you should simulate your memory interface in HyperLynx or asimilar Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide372If the optimal OCT and ODT termination values as determined by simulation are notavailable in the list of available values in the parameter editor, select the closestavailable termination values for OCT and information about available ODT choices, refer to your memory vendor data LinksDynamic On-Chip Termination (OCT) in Intel Stratix 10 Devices on page On-Chip Termination Recommendations for Intel Stratix 10 Devices Output mode (drive strength) for Address/Command/Clock and Data Signals:Depending upon the I/O standard that you have selected, you would have a rangeof selections expressed in terms of ohms or miliamps. A value of 34 to 40 ohms or12 mA is a good starting point for output mode drive strength. Input mode (parallel termination) for Data and Data Strobe signals: A value of 40or 60 ohms is a good starting point for FPGA side input Channel Signal Integrity MeasurementAs external memory interface data rates increase, so does the importance of properchannel signal integrity measuring the actual channel loss during thelayout process and including that data in your parameterization, a realistic assessmentof margins is Importance of Accurate Channel Signal Integrity InformationDefault values for channel loss (or eye reductoin) can be used when calculating timingmargins, however those default values may not accurately reflect the channel loss inyour the channel loss in your system is different than the default values, thecalculated timing margins will vary your actual channel loss is greater than the default channel loss, and if you rely ondefault values, the available timing margins for the entire system will be lower thanthe values calculated during compilation. By relying on default values that do notaccurately reflect your system, you may be lead to believe that you have good timingmargin, while in reality, your design may require changes to achieve good channelsignal Understanding Channel Signal Integrity MeasurementTo measure channel signal integrity you need to measure the channel loss for a particular signal or signal trace, channel loss is defined as loss of the eyewidth at +/- VIH(ac and dc) +/- VIL(ac and dc). VIH/VIL above or below VREF is used toalign with various requirements of the timing model for memory example below shows a reference eye diagram where the channel loss on thesetup- or leading-side of the eye is equal to the channel loss on the hold- or lagging-side of the eye; howevever, it does not necessarily have to be that way. BecauseIntel's calibrating PHY will calibrate to the center of the read and write eye, the BoardSettings tab has parameters for the total extra channel loss for Write DQ and ReadDQ. For address and command signals which are not-calibrated, the Board Settings10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide373tab allows you to enter setup- and hold-side channel losses that are not equal,allowing the Intel Quartus Prime software to place the clock statically within the centerof the address and command Setup and Hold-side How to Enter Calculated Channel Signal Integrity ValuesYou should enter calculated channel loss values in the Channel Signal Integritysection of the Board (or Board Timing) tab of the parameter Intel Stratix 10 external memory interfaces, the default channel loss displayed inthe parameter editor is based on the selected configuration (different values for singlerank versus dual rank), and on internal Intel reference boards. You should replace thedefault value with the value that you Guidelines for Calculating DDR3 Channel Signal IntegrityAddress and Command ISI and CrosstalkSimulate the address/command and control signals and capture eye at the DRAM pins,using the memory clock as the trgger for the memory interface's address/commandand control signals. Measure the setup and hold channel losses at the voltagethresholds mentioned in the memory vendor's data and command channel loss = Measured loss on the setup side + measuredloss on the hold = VDD/2 = mV for DDR3You should select the VIH and VIL voltage levels appropriately for the DDR3L memorydevice that you are using. Check with your memory vendor for the correct voltagelevels, as the levels may vary for different speed grades of Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide374The following figure illustrates a DDR3 example where VIH(AC)/ VIL(AC) is +/- 150 mVand VIH(DC)/ VIL(DC) is +/- 100 DQ ISI and CrosstalkSimulate the write DQ signals and capture eye at the DRAM pins, using DQ Strobe(DQS) as a trigger for the DQ signals of the memory interface simulation. Measure thesetup and hold channel lossses at the VIH and VIL mentioned in the memory vendor'sdata sheet. The following figure illustrates a DDR3 example where VIH(AC)/ VIL(AC) is+/- 150 mV and VIH(DC)/ VIL(DC) is +/- 100 Channel Loss = Measured Loss on the Setup side + Measured Loss on the HoldsideVREF = VDD/2 = mV for DDR3Figure Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide375Read DQ ISI and CrosstalkSimulate read DQ signals and capture eye at the FPGA die. Do not measure at the pin,because you might see unwanted reflections that could create a false representation ofthe eye opening at the input buffer of the FPGA. Use DQ Strobe (DQS) as a trigger forthe DQ signals of your memory interface simulation. Measure the eye opening at +/-70 mV (VIH/VIL) with respect to Channel Loss = (UI) - (Eye opening at +/- 70 mV with respect to VREF)UI = Unit interval. For example, if you are running your interface at 800 Mhz, theeffective data is 1600 Mbps, giving a unit interval of 1/1600 = 625 psVREF = VDD/2 = mV for DDR3Figure DQS ISI and CrosstalkSimulate the Write/Read DQS and capture eye, and measure the uncertainty at = VDD/2 = mV for DDR310 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide376Figure Layout ApproachFor all practical purposes, you can regard the Timing Analyzer report on your memoryinterface as definitive for a given set of memory and board timing will find timing under Report DDR in the Timing Analyzer and on the TimingAnalysis tab in the parameter following flowchart illustrates the recommended process to follow during theboard design phase, to determine timing margin and make iterative improvements toyour Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide377Primary LayoutCalculate Setupand Hold DeratingCalculate ChannelSignal IntegrityCalculate BoardSkewsFind MemoryTiming ParametersGenerate an IP Core that Accurately Represents Your Memory Subsystem, Including pin-out and Accurate Parameters in the Parameter Editor s Board Settings TabRun Quartus Prime Compilation with the Generated IP CoreAny Non-Core TimingViolations in the ReportDDR Panel?yesnoDoneAdjust Layout to Improve: Trace Length Mis-Match Signal Reflections (ISI) Cross Talk Memory Speed GradeBoard SkewFor information on calculating board skew parameters, refer to Board Skew Equations,in this Board Skew Parameter Tool is an interactive tool that can help you calculate boardskew parameters if you know the absolute delay values for all the memory Timing ParametersFor information on the memory timing parameters to be entered into the parametereditor, refer to the datasheet for your external memory LinksBoard Skew Parameter Design Layout GuidelinesThe general layout guidelines in the following topic apply to DDR3 and DDR4 guidelines will help you plan your board layout, but are not meant as strict rulesthat must be adhered to. Intel recommends that you perform your own board-levelsimulations to ensure that the layout you choose for your board allows you to achieveyour desired Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide378For more information about how the memory manufacturers route these address andcontrol signals on their DIMMs, refer to the Cadence PCB browser from the Cadencewebsite, at The various JEDEC example DIMM layouts are availablefrom the JEDEC website, at assistance in calculating board skew parameters, refer to the board skewcalculator tool, which is available at the Intel : 1. The following layout guidelines include several +/- length based rules. Theselength based guidelines are for first order timing approximations if you cannotsimulate the actual delay characteristic of the interface. They do not include anymargin for To ensure reliable timing closure to and from the periphery of the device, signalsto and from the periphery should be registered before any further logic recommends that you get accurate time base skew numbers for your designwhen you simulate the specific Links Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits) on page195 Board Skew Parameter Tool General Layout GuidelinesThe following table lists general board design layout guidelines. These guidelines areIntel recommendations, and should not be considered as hard requirements. Youshould perform signal integrity simulation on all the traces to verify the signal integrityof the interface. You should extract the slew rate and propagation delay information,enter it into the IP and compile the design to ensure that timing requirements Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide379Table Layout GuidelinesParameterGuidelinesImpedance All unused via pads must be removed, because they cause unwantedcapacitance. Trace impedance plays an important role in the signal integrity. You mustperform board level simulation to determine the best characteristic impedancefor your PCB. For example, it is possible that for multi rank systems 40 ohmscould yield better results than a traditional 50 ohm characteristic Parameter Use uF in 0402 size to minimize inductance Make VTT voltage decoupling close to termination resistors Connect decoupling caps between VTT and ground Use a uF cap for every other VTT pin and uF cap for every VDD andVDDQ pin Verify the capacitive decoupling using the Intel Power Distribution NetworkDesign ToolPower Route GND and VCC as planes Route VCCIO for memories in a single split plane with at least a 20-mil( inches, or mm) gap of separation Route VTT as islands or 250-mil ( ) power traces Route oscillators and PLL power as islands or 100-mil ( ) power tracesGeneral RoutingAll specified delay matching requirements include PCB trace delays, different layerpropagation velocity variance, and crosstalk. To minimize PCB layer propogationvariance, Intel recommends that signals from the same net group always berouted on the same layer. Use 45 angles (not 90 corners) Avoid T-Junctions for critical nets or clocks Avoid T-junctions greater than 250 mils ( mm) Disallow signals across split planes Restrict routing other signals close to system reset signals Avoid routing memory signals closer than inch ( mm) to PCI orsystem clocksRelated LinksPower Distribution Layout GuidelinesThe following table lists layout otherwise specified, the guidelines in the following table apply to the followingtopologies: DIMM UDIMM topology DIMM RDIMM topology DIMM LRDIMM topology Not all versions of the Intel Quartus Prime software support LRDIMM. Discrete components laid out in UDIMM topology Discrete components laid out in RDIMM topologyThese guidelines are recommendations, and should not be considered as hardrequirements. You should perform signal integrity simulation on all the traces to verifythe signal integrity of the Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide380For supported frequencies and topologies, refer to the External Memory Interface SpecEstimator frequencies greater than 800 MHz, when you are calculating the delay associatedwith a trace, you must take the FPGA package delays into Guidelines (1)ParameterGuidelinesDecoupling Parameter Make VTT voltage decoupling close to the components and pull-up resistors. Connect decoupling caps between VTT and VDD using a F cap for everyother VTT pin. Use a uF cap and uF cap for every VDDQ Trace Length Even though there are no hard requirements for minimum trace length, youneed to simulate the trace to ensure the signal integrity. Shorter routes resultin better timing. For DIMM topology only: Maximum trace length for all signals from FPGA to the first DIMM slot is Maximum trace length for all signals from DIMM slot to DIMM slot is For discrete components only: Maximum trace length for address, command, control, and clock from FPGA tothe first component must not be more than 7 inches. Maximum trace length for DQ, DQS, DQS#, and DM from FPGA to the firstcomponent is 5 Routing Route over appropriate VCC and GND planes. Keep signal routing layers close to GND and power Guidelines Avoid routing two signal layers next to each other. Always make sure that thesignals related to memory interface are routed between appropriate GND orpower layers. For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) for these traces. (Where H is the vertical distance to the closest returnpath for that particular trace.) For Address/Command/Control traces: Maintain at least 3H spacing betweenthe edges (air-gap) these traces. (Where H is the vertical distance to theclosest return path for that particular trace.) For Clock traces: Maintain at least 5H spacing between two clock pair or aclock pair and any other memory interface trace. (Where H is the verticaldistance to the closest return path for that particular trace.)Clock Routing Route clocks on inner layers with outer-layer run lengths held to under 500mils ( mm). Route clock signals in a daisy chain topology from the first SDRAM to the lastSDRAM. The maximum length of the first SDRAM to the last SDRAM must notexceed tCK for DDR3 and tCK for DDR4. For different DIMMconfigurations, check the appropriate JEDEC specification. These signals should maintain the following spacings: Clocks should maintain a length-matching between clock pairs of 5 ps. Clocks should maintain a length-matching between positive (p) and negative(n) signals of 2 ps, routed in parallel. Space between different pairs should be at least two times the trace width ofthe differential pair to minimize loss and maximize interconnect density. To avoid mismatched transmission line to via, Intel recommends that you useGround Signal Signal Ground (GSSG) topology for your clock pattern GND|CLKP|CKLN|GND. Route all addresses and commands to match the clock signals to within 20 psto each discrete memory component. Refer to the following 10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide381ParameterGuidelinesAddress and Command Routing Route address and command signals in a daisy chain topology from the firstSDRAM to the last SDRAM. The maximum length of the first SDRAM to the lastSDRAM must not be more than tCK for DDR3 and tCK for DDR4. Fordifferent DIMM configurations, check the appropriate JEDEC specifications. UDIMMs are more susceptible to cross-talk and are generally noisier thanbuffered DIMMs. Therefore, route address and command signals of UDIMMs ona different layer than data signals (DQ) and data mask signals (DM) and withgreater spacing. Do not route differential clock (CK) and clock enable (CKE) signals close toaddress signals. Route all addresses and commands to match the clock signals to within 20 psto each discrete memory component. Refer to the following , DM, and DQS Routing Rules All the trace length matching requirements are from the FPGA package ball tothe SDRAM package ball, which means you must consider trace mismatchingon different DIMM raw cards. Match in length all DQ, DQS, and DM signals within a given byte-lane groupwith a maximum deviation of 10 ps. Ensure to route all DQ, DQS, and DM signals within a given byte-lane group onthe same layer to avoid layer to layer transmission velocity differences, whichotherwise increase the skew within the group. Do not count on FPGAs to deskew for more than 20 ps of DQ group skew. Theskew algorithm only removes the following possible uncertainties: Minimum and maximum die IOE skew or delay mismatch Minimum and maximum device package skew or mismatch Board delay mismatch of 20 ps Memory component DQ skew mismatch Increasing any of these four parameters runs the risk of the deskewalgorithm limiting, failing to correct for the total observed system skew. Ifthe algorithm cannot compensate without limiting the correction, timinganalysis shows reduced margins. For memory interfaces with leveling, the timing between the DQS and clocksignals on each device calibrates dynamically to meet tDQSS. To make surethe skew is not too large for the leveling circuit s capability, follow these rules: Propagation delay of clock signal must not be shorter than propagationdelay of DQS signal at every device: (CKi) DQSi > 0; 0 < i < number ofcomponents 1 . For DIMMs, ensure that the CK trace is longer than thelongest DQS trace at the DIMM connector. Total skew of CLK and DQS signal between groups is less than one clockcycle: (CKi+ DQSi) max (CKi+ DQSi) min < 1 tCK(If you are using aDIMM topology, your delay and skew must take into consideration valuesfor the actual DIMM.) 10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide382ParameterGuidelinesSpacing Guidelines Avoid routing two signal layers next to each other. Always ensure that thesignals related to the memory interface are routed between appropriate GNDor power layers. For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) of these traces, where H is the vertical distance to the closest return pathfor that particular trace. For Address/Command/Control traces: Maintain at least 3H spacing betweenthe edges (air-gap) of these traces, where H is the vertical distance to theclosest return path for that particular trace. For Clock traces: Maintain at least 5H spacing between two clock pairs or aclock pair and any other memory interface trace, where H is the verticaldistance to the closest return path for that particular Quartus Prime Software Settingsfor Board Layout To perform timing analyses on board and I/O buffers, use a third-partysimulation tool to simulate all timing information such as skew, ISI, crosstalk,and type the simulation result into the Board Settings tab in the parametereditor. Do not use advanced I/O timing model (AIOT) or board trace model unless youdo not have access to any third party tool. AIOT provides reasonable accuracybut tools like HyperLynx provide better to Table:1. For point-to-point and DIMM interface designs, refer to the Micron website, Links Package Deskew on page 198 External Memory Interface Spec Estimator Length Matching RulesThe following topics provide guidance on length matching for different types of all addresses and commands to match the clock signals to within 20 ps toeach discrete memory component. The following figure shows the component routingguidelines for address and command Component Address and Command Routing GuidelinesIf using discrete components:x = y 20 psx + x1 = y + y1 20 psx + x1 + x2 = y + y1 + y2 20 psaddress andcommandclockxyx1y1x2y2x3y3If using a DIMM topology: x=y +/- 20 psPropagation delay < for DDR3 VTTVTTSDRAMComponentSDRAMComponentSDRAMComponentSDRAMComponentFPGAx + x1 + x2 + x3 = y + y1 + y2 +y3 20 pstCKPropagation delay < for DDR4 tCK10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide383The timing between the DQS and clock signals on each device calibrates dynamicallyto meet tDQSS. The following figure shows the delay requirements to align DQS andclock signals. To ensure that the skew is not too large for the leveling circuit scapability, follow these rules: Propagation delay of clock signal must not be shorter than propagation delay ofDQS signal at every device:CKi DQSi > 0; 0 < i < number of components 1 Total skew of CLK and DQS signal between groups is less than one clock cycle:(CKi + DQSi) max (CKi + DQSi) min < 1 tCKFigure DQS Signal to Align DQS and ClockVTTSDRAMComponentDQ Group 0CKCK0CK1DSQiCKiCKi = Clock signal propagation delay to device iFPGASDRAMComponentSDRAMComponentDQ Group 1DQ Group iDQSi = DQ/DQS signals propagation delay to group iClk pair matching If you are using a DIMM (UDIMM, RDIMM, or LRDIMM) topology,match the trace lengths up to the DIMM connector. If you are using discretecomponents, match the lengths for all the memory components connected in the fly-by group length matching If you are using a DIMM (UDIMM, RDIMM, or LRDIMM)topology, apply the DQ group trace matching rules described in the guideline tableearlier up to the DIMM connector. If you are using discrete components, match thelengths up to the respective memory you are using DIMMs, it is assumed that lengths are tightly matched within theDIMM itself. You should check that appropriate traces are length-matched within Spacing GuidelinesThis topic provides recommendations for minimum spacing between board traces forvarious signal Guidelines for DQ, DQS, and DM TracesMaintain a minimum of 3H spacing between the edges (air-gap) of these traces.(Where H is the vertical distance to the closest return path for that particular trace.) GND or Power3HHGND or PowerH10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide384Spacing Guidelines for Address and Command and Control TracesMaintain at least 3H spacing between the edges (air-gap) of these traces. (Where H isthe vertical distance to the closest return path for that particular trace.) GND or Power3HHGND or PowerHSpacing Guidelines for Clock TracesMaintain at least 5H spacing between two clock pair or a clock pair and any othermemory interface trace. (Where H is the vertical distance to the closest return path forthat particular trace.) 5HGND or PowerHHGND or Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits)The following topics discuss different ways to lay out a wider DDR3 or DDR4 SDRAMinterface to the FPGA. Choose the topology based on board trace simulation and thetiming budget of your EMIF IP supports up to a 144-bit wide DDR3 interface. You can use discretecomponents or DIMMs to implement a wide interface (any interface wider than 72bits). Intel recommends using leveling when you implement a wide interface withDDR3 you lay out for a wider interface, all rules and constraints discussed in theprevious sections still apply. The DQS, DQ, and DM signals are point-to-point, and allthe same rules discussed in Design Layout Guidelines main challenge for the design of the fly-by network topology for the clock,command, and address signals is to avoid signal integrity issues, and to make sureyou route the DQS, DQ, and DM signals with the chosen LinksDesign Layout Guidelines on page Fly-By Network Design for Clock, Command, and Address SignalsThe EMIF IP requires the flight-time skew between the first SDRAM component andthe last SDRAM component to be less than tCK for memory clocks. Thisconstraint limits the number of components you can have for each fly-by you design with discrete components, you can choose to use one or more fly-bynetworks for the clock, command, and address following figure shows an example of a single fly-by network Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide385Figure Fly-By Network TopologyVTTFPGADDR3SDRAMDDR3SDRAMDDR3SDR AMDDR3SDRAMDDR3SDRAMDDR3SDRAMLess than tCKEvery SDRAM component connected to the signal is a small load that causesdiscontinuity and degrades the signal. When using a single fly-by network topology, tominimize signal distortion, follow these guidelines: Use 16 device instead 4 or 8 to minimize the number of devices connected tothe trace. Keep the stubs as short as possible. Even with added loads from additional components, keep the total trace lengthshort; keep the distance between the FPGA and the first SDRAM component lessthan 5 inches. Simulate clock signals to ensure a decent following figure shows an example of a double fly-by network topology. Thistopology is not rigid but you can use it as an alternative option. The advantage ofusing this topology is that you can have more SDRAM components in a system withoutviolating the tCK rule. However, as the signals branch out, the components stillcreate Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide386Figure Fly-By Network TopologyDDR3SDRAMDDR3SDRAMDDR3SDRAMDDR3S DRAMDDR3SDRAMDDR3SDRAMLess than tFPGADDR3SDRAMDDR3SDRAMDDR3SDRAMDDR3SDRA MDDR3SDRAMDDR3SDRAMLess than tVTTVTTCKCKYou must perform simulations to find the location of the split, and the best impedancefor the traces before and after the following figure shows a way to minimize the discontinuity effect. In this example,keep TL2 and TL3 matches in length. Keep TL1 longer than TL2 and TL3, so that it iseasier to route all the signals during Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide387Figure Discontinuity EffectSplitting PointTL3, ZQ = 50 TL1, ZQ = 25 TL2, ZQ = 50 You can also consider using a DIMM on each branch to replace the the trade impedance on the DIMM card is 40-ohm to 60-ohm, perform aboard trace simulation to control the reflection to within the level your system the fly-by daisy chain topology increases the complexity of the datapath andcontroller design to achieve leveling, but also greatly improves performance and easesboard layout for SDRAM can also use the SDRAM components without leveling in a design if it may resultin a more optimal solution, or use with devices that support the required electricalinterface standard, but do not support the required read and write Package DeskewTrace lengths inside the device package are not uniform for all package pins. Thenonuniformity of package traces can affect system timing for high frequencies. Apackage deskew option is available in the Intel Quartus Prime you do not enable the package deskew option, the Intel Quartus Prime softwareuses the package delay numbers to adjust skews on the appropriate signals; you donot need to adjust for package delays on the board traces. If you do enable thepackage deskew option, the Intel Quartus Prime software does not use the packagedelay numbers for timing analysis, and you must deskew the package delays with theboard traces for the appropriate signals for your LinksLayout Guidelines on page DQ/DQS/DM DeskewTo get the package delay information, follow these steps:10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide3881. Select the FPGA DQ/DQS Package Skews Deskewed on Board checkbox onthe Board Settings tab of the parameter Generate your Instantiate your IP in the Compile your Refer to the All Package Pins compilation report, or find the pin delays displayedin the <core_name>.pin Address and Command DeskewDeskew address and command delays as follows:1. Select the FPGA Address/Command Package Skews Deskewed on Boardcheckbox on the Board Settings tab of the parameter Generate your Instantiate your IP in the Compile your Refer to the All Package Pins compilation report, or find the pin delays displayedin the <core_name>.pin Package Deskew Recommendations for Intel Stratix 10 DevicesThe following table shows package deskew recommendations for Intel Stratix operating frequencies increase, it becomes increasingly critical to perform packagedeskew. The frequencies listed in the table are the minimum frequencies for which youmust perform package you plan to use a listed protocol at the specified frequency or higher, you mustperform package Frequency (MHz) for Which to Perform Package DeskewSingle RankDual RankQuad RankDDR4933800667DDR3933800667LPDDR36675 33Not requiredQDR IV933Not applicableNot applicableRLDRAM 3933667Not applicableQDR II, II+, II+ XtremeNot requiredNot applicableNot Deskew ExampleConsider an example where you want to deskew an interface with 4 DQ pins, 1 DQSpin, and 1 DQSn Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide389Let s assume an operating frequency of 667 MHz, and the package lengths for the pinsreported in the .pin file as follows:dq[0] = 120 psdq[1] = 120 psdq[2] = 100 psdq[3] = 100 psdqs = 80 psdqs_n = 80 psThe following figure illustrates this ExampleFPGA mem_dq[0]mem_dq[1]mem_dq[2]mem_dq[3]mem_ dqsmem_dqs_nmem_dq[0]mem_dq[1]mem_dq[2]m em_dq[3]mem_dqsmem_dqs_nMemory120 ps120 ps100 ps100 ps80 ps80 psABCDEFWhen you perform length matching for all the traces in the DQS group, you must takepackage delays into consideration. Because the package delays of traces A and B are40 ps longer than the package delays of traces E and F, you would need to make theboard traces for E and F 40 ps longer than the board traces for A and similar methodology would apply to traces C and D, which should be 20 ps longerthan the lengths of traces A and following figure shows this scenario with the length of trace A at 450 Example with Trace Delay CalculationsFPGAmem_dq[0]mem_dq[1]mem_dq [2]mem_dq[3]mem_dqsmem_dqs_nmem_dq[0]mem _dq[1]mem_dq[2]mem_dq[3]mem_dqsmem_dqs_n Memory120 ps120 ps100 ps100 ps80 ps80 psA=450psB=A=450psC=A+20ps=470psC=A+20ps =470psC=A+40ps=490psC=A+40ps=490ps10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide390When you enter the board skews into the Board Settings tab of the DDR3 parametereditor, you should calculate the board skew parameters as the sums of board delayand corresponding package delay. If a pin does not have a package delay (such asaddress and command pins), you should use the board delay example of the preceding figure shows an ideal case where board skews areperfectly matched. In reality, you should allow plus or minus 10 ps of skew mismatchwithin a DQS group (DQ/DQS/DM).10 Intel Stratix 10 EMIF IP for LPDDR3UG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide39111 Intel Stratix 10 EMIF IP Timing ClosureThis chapter describes timing analysis and optimization techniques that you can use toachieve timing Timing ClosureThe following sections describe the timing analysis using the respective FPGA datasheet specifications and the user-specified memory data sheet parameters. Core to core (C2C) transfers have timing constraint created and are analyzed bythe Timing Analyzer. Core timing does not include user logic timing within core orto and from EMIF block. The EMIF IP provides the constrained clock to thecustomer logic. Core to periphery (C2P) transfers have timing constraint created and are timinganalyzed by the Timing Analyzer. Because of the increased number of C2P/P2Csignals in 20nm families compared to previous families, more work is expected toensure that these special timing arcs are properly modeled, both during timinganalysis and compilation. Periphery to core (P2C) transfers have timing constraint created and are timinganalyzed by the Timing Analyzer. Because of the increased number of C2P/P2Csignals in 20nm families compared to previous families, more work is expected toensure that these special timing arcs are properly modeled, both during timinganalysis and compilation. Periphery to periphery (P2P) transfers are modeled entirely by a minimum pulsewith violation on the hard block, and have no internal timing arc. P2P transfers aremodeled only by a minimum pulse width violation on hardened account for the effects of calibration, the EMIF IP includes additional scripts that arepart of the <phy_variation_name> and<phy_variation_name>_ files that determine thetiming margin after calibration. These scripts use the setup and hold slacks ofindividual pins to emulate what is occurring during calibration to obtain timing marginsthat are representative of calibrated PHYs. The effects considered as part of thecalibrated timing analysis include improvements in margin because of calibration, andquantization error and calibration uncertainty because of voltage and temperaturechanges after LinksTiming Analysis on page 393UG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of Timing AnalysisTiming analysis of Intel Stratix 10 EMIF IP is somewhat simpler than that of earlierdevice families, because Intel Stratix 10 devices have more hardened blocks and thereare fewer soft logic registers to be analyzed, because most are user logic Intel Stratix 10 EMIF IP includes a Synopsys Design Constraints File (.sdc)which contains timing constraints specific to your IP. The .sdc file also contains ToolCommand Language (.tcl) scripts which perform various timing analyses specific tomemory timing analysis flows are available for Intel Stratix 10 EMIF IP: Early I/O Timing Analysis, which is a precompilation flow. Full Timing Analysis, which is a post-compilation LinksTiming Closure on page PHY or CoreTiming analysis of the PHY or core path includes the path from the last set of registersin the core to the first set of registers in the periphery (C2P), path from the last set ofregisters in the periphery to the first of registers in the core (P2C) and ECC relatedpath if it is timing analysis excludes user logic timing to or from EMIF blocks. The EMIF IPprovides a constrained clock (for example: ddr3_usr_clk) with which to clock customerlogic; pll_afi_clk serves this PHY or core analyzes this path by calling the report_timing command in<variation_name> and<variation_name> : In version and later, the Spatial Pessimism Removal slack values in the Core toPeriphery and Periphery to Core tables are always equal to zero. This occursbecause pessimism removal is integrated into the base timing I/O TimingI/O timing analysis includes analysis of read capture, write, address and command,DQS gating, and write Timing Analyzer provides a breakdown of the timing budgets which details marginloss due to transmitter, receiver, and channel. The Timing Analyzer displays the totalmargin in the last row of the timing I/O timing analysis described in the following topics is based on a 2 speed-gradedevice, interfacing with a DDR3 SDRAM UDIMM at 1066 MHz. A 1066 MHz DDR3SDRAM UDIMM is used for the Read CaptureRead capture timing analysis indicates the amount of slack on the DQ signals that arelatched by the FPGA using the DQS strobe output of the memory Intel Stratix 10 EMIF IP Timing ClosureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide393The Timing Analyzer analyzes read capture timing paths through conventional statictiming analysis and further processing steps that account for memory calibration(which may include pessismism removal) and calibration uncertainties as shown in thefollowing Capture Timing Analysis Channel EffectsTransmitter Effects(Memory)Receiver Effects(FPGA) WriteWrite timing analysis indicates the amount of slack on the DQ signals that are latchedby the memory device using the DQS strobe output from the FPGA with read capture, the Timing Analyzer analyzes write timing paths throughconventional static timing analysis and further processing steps that account formemory calibration (which may include pessismism removal) and calibrationuncertainties as shown in the following Timing AnalysisChannel EffectsReceiver Effects (Memory)Transmitter Effects (FPGA) Address and CommandAddress and command signals are single data rate signals latched by the memorydevice using the FPGA output clock; some are half-rate data signals, while others,such as the chip select, are full-rate Intel Stratix 10 EMIF IP Timing ClosureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide394The Timing Analyzer analyzes the address and command timing paths throughconventional static timing analysis and further processing steps that account formemory pessismism removal (as shown in the following figure). Depending on thememory protocol in use, if address command calibration is performed, calibrationuncertainty is subtracted from the timing window while PVT variation and skew effectsare not subtracted, and vice versaFigure and Command Timing Analysis Channel EffectsReceiver Effects(Memory)Transmitter Effects(FPGA) DQS Gating / PostamblePostamble timing is a setup period during which the DQS signal goes low after all theDQ data has been received from the memory device during a read operation. Afterpostamble time, the DQS signal returns from a low-impedance to a high-impedancestate to disable DQS and disallow any glitches from writing false data over valid Timing Analyzer analyzes the postamble timing path in DDRx memory protocolsonly through an equation which considers memory calibration, calibration uncertainty,and tracking uncertainties as shown in the following Gating Timing AnalysisChannel EffectsTransmitter Effects (Memory)Receiver Effects (FPGA)11 Intel Stratix 10 EMIF IP Timing ClosureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Write LevelingIn DDR3 SDRAM and DDR4 SDRAM interfaces, write leveling details the margin for theDQS strobe with respect to CK/CK# at the memory Timing Analyzer analyzes the write leveling timing path through an equationwhich considers memory calibration, calibration uncertainty and PVT variation asshown in the following Leveling Timing AnalysisChannel EffectsReceiver Effects (Memory)Transmitter Effects (FPGA) Timing Report DDRThe Report DDR task in the Timing Analyzer generates custom timing margin reportsfor all EMIF IP instances in your design. The Timing Analyzer generates this customreport by sourcing the wizard-generated <variation_name> <variation_name> script reports the following timingslacks on specific paths of the DDR SDRAM: Read capture Read resynchronization Mimic, address and command Core Core reset and removal Half-rate address and command DQS versus CK Write Write leveling (tDQSS) Write leveling (tDSS/tDSH) DQS Gating (Postamble)11 Intel Stratix 10 EMIF IP Timing ClosureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide396The <variation_name> script checks basic design rules andassumptions; if violations are found, you receive critical warnings when the TimingAnalyzer runs during compilation or when you run the Report DDR generate a timing margin report, follow these steps:1. Compile your design in the Intel Quartus Prime Launch the Timing Double-click Report DDR from the Tasks pane. This action automaticallyexecutes the Create Timing Netlist, Read SDC File, and Update TimingNetlist tasks for your project. The .sdc may not be applied correctly if the variation top-level file is the top-levelfile of the project. You must have the top-level file of the project instantiate thevariation top-level Report DDR feature creates a new DDR folder in the Timing Analyzer the DDR folder reveals the detailed timing information for each PHY timingpath, in addition to an overall timing margin summary for the instance, as shown inthe following Margin Summary Window Generated by Report DDR TaskThe following figure shows the timing analysis results calculated using FPGA timingmodel before adjustment in the Before Calibration Intel Stratix 10 EMIF IP Timing ClosureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide397Figure and Write Before CalibrationThe following two figures show the read capture and write margin summary windowgenerated by the Report DDR Task for a DDR3 core. It first shows the timing resultscalculated using the FPGA timing model. The<variation_name> then adjusts these numbers to accountfor effects that are not modeled by either the timing model or by Timing Capture Margin Summary WindowFigure Capture Margin Summary Optimizing TimingFor full-rate designs you may need to use some of the Intel Quartus Prime advancedfeatures, to meet core timing, by following these steps:1. On the Assignments menu click Settings. In the Category list, click Analysis &Synthesis Settings. For Optimization Technique select Intel Stratix 10 EMIF IP Timing ClosureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide398Figure Technique Turn on Perform physical synthesis for combinational more information about physical synthesis, refer to the Netlist andOptimizations and Physical Synthesis chapter in the Intel Quartus Prime SoftwareHandbook. Turn on Perform register retiming Turn on Perform automatic asynchronous signal pipelining Turn on Perform register duplication You can initially select Normal for Effort level, then if the core timing is still notmet, select Intel Stratix 10 EMIF IP Timing ClosureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide399Figure Synthesis OptimizationsRelated LinksNetlist Optimizations and Physical Early I/O Timing EstimationEarly I/O timing analysis allows you to run I/O timing analysis without first compilingyour design. You can use early I/O timing analysis to quickly evaluate whetheradequate timing margin exists on the I/O interface between the FPGA and externalmemory I/O timing analysis performs the following analyses: Read analysis Write analysis Address and command analysis DQS gating analysis Write leveling analysisEarly I/O timing analysis takes into consideration the following factors: The timing parameters of the memory device The speed and topology of the memory interface The board timing and ISI characteristics The timing of the selected FPGA device11 Intel Stratix 10 EMIF IP Timing ClosureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Performing Early I/O Timing AnalysisTo perform early I/O timing analysis, follow these steps:1. Instantiate an EMIF IP On the Memory Timing tab, enter accurate memory On the Board Timing tab, enter accurate values for Slew Rate, IntersymbolInterference, and Board and Package After generating your IP core, create a Intel Quartus Prime project and select yourdevice from the Available devices To launch the Timing Analyzer, select Timing Analyzer from the Tools To run early I/O timing analysis:a. Select Run Tcl Script from the Script Run submodule\<variation_name> following figure shows an early I/O timing analysis from the Timing Analyzer usinga DDR3 example DDR Timing ResultsReport DDR details the read capture, write, address and command, DQS gating, andwrite leveling timing analyses, which are identical to those obtained after a full designcompilation. Core FPGA timing paths are not included in early I/O timing Intel Stratix 10 EMIF IP Timing ClosureUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide40112 Optimizing Controller PerformanceWhen designing an external memory interface, you should understand the waysavailable to increase the efficiency and bandwidth of the memory following topics discuss factors that affect controller efficiency and ways toincrease the efficiency of the EfficiencyController efficiency varies depending on data transaction. The best way to determinethe efficiency of the controller is to simulate the memory controller for your efficiency is expressed as:Efficiency = number of active cycles of data transfer/total number of cyclesThe total number of cycles includes the number of cycles required to issue commandsor other : You calculate the number of active cycles of data transfer in terms of local clockcycles. For example, if the number of active cycles of data transfer is 2 memory clockcycles, you convert that to the local clock cycle which is following cases are based on a high-performance controller design targeting anFPGA device with a CAS latency of 3, and burst length of 4 on the memory side (2cycles of data transfer), with accessed bank and row in the memory device alreadyopen. The FPGA has a command latency of 9 cycles in half-rate mode. Thelocal_ready signal is high. Case 1: The controller performs individual = 1/(1 + CAS + command latency) = 1/(1+ +9) = 1 = Case 2: The controller performs 4 back to back this case, the number of data transfer active cycles is 8. The CAS latency isonly counted once because the data coming back after the first read is the CAS latency for the first read has an impact on efficiency. The commandlatency is also counted once because the back to back read commands use thesame bank and = 4/(4 + CAS + command latency) = 4/(4+ +9) = 1 = Interface StandardComplying with certain interface standard specifications affects controller | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008RegisteredWhen interfacing the memory device to the memory controller, you must observetiming specifications and perform the following bank management operations: ActivateBefore you issue any read (RD) or write (WR) commands to a bank within anSDRAM device, you must open a row in that bank using the activate (ACT)command. After you open a row, you can issue a read or write command to thatrow based on the tRCD specification. Reading or writing to a closed row hasnegative impact on the efficiency as the controller has to first activate that rowand then wait until tRCD time to perform a read or write. PrechargeTo open a different row in the same bank, you must issue a precharge precharge command deactivates the open row in a particular bank or the openrow in all banks. Switching a row has a negative impact on the efficiency as youmust first precharge the open row, then activate the next row and wait tRCD timeto perform any read or write operation to the row. Device CAS latencyThe higher the CAS latency, the less efficient an individual access. The memorydevice has its own read latency, which is about 12 ns to 20 ns regardless of theactual frequency of the operation. The higher the operating frequency, the longerthe CAS latency is in number of cycles. RefreshA refresh, in terms of cycles, consists of the precharge command and the waitingperiod for the auto refresh. Based on the memory data sheet, these componentsrequire the following values: tRP = 12 ns, 3 clock cycles for a 200-MHz operation (5 ns period for 200 MHz) tRFC = 75 ns, 15 clock cycles for a 200-MHz on this calculation, a refresh pauses read or write operations for 18 clockcycles. So, at 200 MHz, you lose (18 x 5 us) of the total Bank Management EfficiencyThe following figures show examples of how the bank management operations affectcontroller first figure shows a read operation in which you have to change a row in a figure shows how CAS latency and precharge and activate commands following figure illustrates a read-after-write operation. The controller changes therow address after the write-to-read from a different Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide403Figure Operation Changing A Row in A Bank(1)(1)(1)(2)(2)(3)(4)(5)The following sequence of events describes the above local_read_req signal goes high, and when the local_ready signal goeshigh, the controller accepts the read request along with the After the memory receives the last write data, the row changes for read. Now yourequire a precharge command to close the row opened for write. The controllerwaits for tWR time (3 memory clock cycles) to give the precharge command afterthe memory receives the last write After the controller issues the precharge command, it must wait for tRP time toissue an activate command to open a After the controller gives the activate command to activate the row, it needs towait tRCD time to issue a read After the memory receives the read command, it takes the memory some time toprovide the data on the pin. This time is known as CAS latency, which is 3 memoryclock cycles in this this particular case, you need approximately 17 local clock cycles to issue a readcommand to the memory. Because the row in the bank changes, the read operationtakes a longer time, as the controller has to issue the precharge and activatecommands first. You do not have to take into account tWTR for this case because theprecharge and activate operations already exceeded tWTR following figure shows the case where you use the same the row and bankaddress when the controller switches from write to read. In this case, the readcommand latency is Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide404Figure From Write to Read Same Row and Bank Address(1)(2)(3)(4)The following sequence of events describes the above local_read_req signal goes high and the local_ready signal is highalready. The controller accepts the read request along with the When switching from write to read, the controller has to wait tWTR time before itgives a read command to the The SDRAM device receives the read After the SDRAM device receives the read command, it takes some time to givethe data on the pin. This time is called CAS latency, which is 3 memory clockcycles in this the case illustrated in the second figure above, you need approximately 11 localclock cycles to issue a read command to the memory. Because the row in the bankremains the same, the controller does not have to issue the precharge and activatecommands, which speeds up the read operation and in turn results in a betterefficiency compared to the case in the first figure , if you do not switch between read and write often, the efficiency of yourcontroller improves Data TransferThe following methods of data transfer reduce the efficiency of your controller: Performing individual read or write accesses is less efficient. Switching between read and write operation has a negative impact on theefficiency of the controller. Performing read or write operations from different rows within a bank or in adifferent bank if the bank and a row you are accessing is not already open alsoaffects the efficiency of your Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide405The following figure shows an example of changing the row in the same Row in the Same Bank(1)(2)The following sequence of events describes the above figure:1. You have to wait tWR time before giving the precharge command2. You then wait tRP time to give the activate Improving Controller EfficiencyYou can use the following tools and methods to improve the efficiency of yourcontroller. Auto-Precharge Commands Additive Latency Bank Interleaving Command Queue Look-Ahead Depth Additive Latency and Bank Interleaving User-Controlled Refresh Frequency of Operation Burst Length Series of Reads or WritesThe following sections discuss these methods in Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Auto-Precharge CommandsThe auto-precharge read and write commands allow you to indicate to the memorydevice that a given read or write command is the last access to the currently memory device automatically closes or auto-precharges the page that is currentlybeing accessed, so that the next access to the same bank is faster. The Auto-Precharge command is useful when you want to perform fast random Timer Bank Pool (TBP) block supports the dynamic page policy, where dependingon user input on local autoprecharge input would keep a page open or close. In aclosed-page policy, a page is always closed after it is accessed with auto-prechargecommand. When the data pattern consists of repeated reads or writes to addressesnot within the same page, the optimal system achieves the maximum efficiencyallowed by continuous page miss limited access. Efficiency losses are limited to thoseassociated with activating and refreshing. An efficiency of 10-20% should be expectedfor this closed-page an open-page policy, the page remains open after it is accessed for incomingcommands. When the data pattern consists of repeated reads or writes to sequentialaddresses within the same page, the optimal system can achieve 100% efficiency forpage-open transactions (ignoring the effects of periodic refreshes, which typicallyconsume around 2-3% of total efficiency), with minimum latency for highest prioritysingle you turn on Enable Auto-Precharge Control, you can instruct the controller toissue an autoprecharge read or write command. The next time you access that bank,the access will be faster because the controller does not have to precharge the bankbefore activating the row that you want to controller-derived autoprecharge logic evaluates the pending commands in thecommand buffer and determines the most efficient autoprecharge operation toperform. The autoprecharge logic can reorder commands if necessary. When all TBPare occupied due to tracking an open page, TBP uses a scheme called on-demandflush, where it stops tracking a page to create space for an incoming following figure compares auto-precharge with and without look-ahead Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide407Figure With and Without Look-ahead Auto-PrechargeWithout using the look-ahead auto-precharge feature, the controller must prechargeto close and then open the row before the write or read burst for every row using the look-ahead precharge feature, the controller decides whether to doauto-precharge read/write by evaluating the incoming command; subsequent reads orwrites to same bank/different row will require only an activate shown in the preceding figure, the controller performs an auto-precharge for thewrite command to bank 0 at cycle 1. The controller detects that the next write at cycle13 is to a different row in bank 0, and hence saves 2 data following efficiency results apply to the above figure:Table Efficiencies With and Without Look-Ahead Auto-PrechargeFeatureWithout Look-ahead Auto-prechargeWith Look-ahead Auto-prechargeActive cycles of data transfer1616Total number of cycles1917Approximate efficiency84%94%The look-ahead auto-precharge used increases efficiency by approximately 10%.The following figure shows how you can improve controller efficiency using the auto-precharge Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide408Figure Efficiency Using Auto-Precharge Command(1)(2)The following sequence of events describes the above figure:1. The controller accepts a read request from the local side as soon as thelocal_ready signal goes The controller gives the activate command and then gives the read command. Theread command latency is approximately 14 clock cycles for this case as comparedto the similar case with no auto precharge which had approximately 17 clockcycles of latency (described in the "data Transfer" topic).When using the auto-precharge option, note the following guidelines: Use the auto-precharge command if you know the controller is issuing the nextread or write to a particular bank and a different row. Auto-precharge does not improve efficiency if you auto-precharge a row andimmediately reopen LatencyThe following latency data applies to all memory protocols supported by the IntelStratix 10 EMIF in Full-Rate Memory Clock CyclesRate 1ControllerAddress &CommandPHY Address& CommandMemoryReadLatency 2PHY ReadData ReturnControllerRead DataReturnRound TripRound TripWithoutMemoryHalf:Write1223-23 Half:Read823-236827-4724Quarter:Write142 3-23 12 Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide409Rate 1ControllerAddress &CommandPHY Address& CommandMemoryReadLatency 2PHY ReadData ReturnControllerRead DataReturnRound TripRound TripWithoutMemoryQuarter:Read1023-236143 5-5532Half:Write(ECC)1423-23 Half:Read(ECC)1223-236831-5128Quarter:Wr ite (ECC)1423-23 Quarter:Read (ECC)1223-2361437-57341. User interface rate; the controller always operates in half Minimum and maximum read latency range for DDR3, DDR4, and Additive LatencyAdditive latency increases the efficiency of the command and data bus for may issue the commands externally but the device holds the commands internallyfor the duration of additive latency before executing, to improve the systemscheduling. The delay helps to avoid collision on the command bus and gaps in datainput or output bursts. Additive latency allows the controller to issue the row andcolumn address commands activate, and read or write in consecutive clock cycles,so that the controller need not hold the column address for several (tRCD) cycles. Thisgap between the activate and the read or write command can cause bubbles in thedata following figure shows an example of additive Latency ReadCKCommandDQDQS/DQS#T0[1][2]T1T2T3T4T 5T6T7T8CK#tRCD (MIN) ACTnnn + 1n + 2n + 3nNOPNOPNOPNOPNOPNOPNOPRDAL = 2 RL = 5 (1)CL = 3 12 Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide410The following sequence of events describes the above figure:1. The controller issues a read or write command before the tRCD (MIN) requirement additive latency less than or equal to tRCD (MIN).2. The controller holds the read or write command for the time defined by additivelatency before issuing it internally to the SDRAM latency = additive latency + CAS latencyWrite latency = additive latency + CAS latency CalibrationThe time needed for calibration varies, depending on many factors including theinterface width, the number of ranks, frequency, board layout, and difficulty following table lists approximate typical calibration times for various protocols Stratix 10 EMIF IP Approximate Calibration TimesProtocolRank and FrequencyTypical Calibration TimeDDR3, x64 UDIMM, DQS x8, DM on1 rank, 933 MHz102 ms1 rank, 800 MHz106 ms2 rank, 933 MHz198 ms2 rank, 800 MHz206 msDDR4, x64 UDIMM, DQS x8, DBI on1 rank, 1067 MHz314 ms1 rank, 800 MHz353 ms2 rank 1067 MHz625 ms2 rank 800 MHz727 msRLDRAM 3, x361200 MHz2808 ms1067 MHz2825 ms1200 MHz, with DM2818 ms1067 MHz, with DM2833 msQDR II, x36, BWS on333 MHz616 ms633 MHz833 msQDR-IV, x36, BWS on1067 MHz1563 ms1067 MHz, with DBI1556 Bank InterleavingYou can use bank interleaving to sustain bus efficiency when the controller misses apage, and that page is in a different Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide411Note: Page size refers to the minimum number of column locations on any row that youaccess with a single activate command. For example: For a 512Mb x8 DDR3 SDRAMwith 1024 column locations (column address A[9:0]), page size = 1024 columns x 8 =8192 bits = 8192/8 bytes = 1024 bytes (1 KB)Without interleaving, the controller sends the address to the SDRAM device, receivesthe data requested, and then waits for the SDRAM device to precharge and reactivatebefore initiating the next data transaction, thus wasting several clock allows banks of the SDRAM device to alternate their backgroundoperations and access cycles. One bank undergoes its precharge/activate cycle whileanother is being accessed. By alternating banks, the controller improves itsperformance by masking the precharge/activate time of each bank. If there are fourbanks in the system, the controller can ideally send one data request to each of thebanks in consecutive clock example, in the first clock cycle, the CPU sends an address to Bank 0, and thensends the next address to Bank 1 in the second clock cycle, before sending the thirdand fourth addresses to Banks 2 and 3 in the third and fourth clock cyclesrespectively. The sequence is as follows:1. Controller sends address 0 to Bank Controller sends address 1 to Bank 1 and receives data 0 from Bank Controller sends address 2 to Bank 2 and receives data 1 from Bank Controller sends address 3 to Bank 3 and receives data 2 from Bank Controller receives data 3 from Bank following figure shows how you can use interleaving to increase Interleaving to Increase BandwidthAccess Bank 0Access Bank 1Access Bank 2Access Bank 3Access Bank 0 (again)Access Pattern With 4-way InterleavingMemory Bank 0MemoryBank 1MemoryBank 2MemoryBank 3CPUAccess Pattern Without InterleavingStart Access for D1Start Access for D2 D1 availableCPUMemory12 Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide412The controller supports three interleaving options:Chip-Bank-Row-Col This is a noninterleaved option. Select this option to improveefficiency with random trafficChip-Row-Bank-Col This option uses bank interleaving without chip selectinterleaving. Select this option to improve efficiency with sequential traffic, byspreading smaller data structures across all banks in a - This option uses bank interleaving with chip selectinterleaving. Select this option to improve efficiency with sequential traffic andmultiple chip selects. This option allows smaller data structures to spread acrossmultiple banks and interleaving is a fixed pattern of data transactions, enabling best-case bandwidthand latency, and allowing for sufficient interleaved transactions between openingbanks to completely hide tRC. An optimal system can achieve 100% efficiency for bankinterleave transactions with 8 banks. A system with less than 8 banks is unlikely toachieve 100%. Command Queue Look-Ahead DepthThe command queue look-ahead depth value determines the number of read or writerequests that the look-ahead bank management logic examines. The command queuelook-ahead depth value also determines how many open pages the controller example, if you set the command queue look-ahead depth value to 4, thecontroller can track 4 open pages. In a 4-bank interleaving case, the controller willreceive repeated commands with addresses of bank A, bank B, bank C, and bank receive the next set of commands, the controller issues a precharge command toexit the current page and then issues an activate command to track the new incomingpage, leading to a drop in with Command Queue Look-ahead Depth of 4With the command queue look-ahead depth set to 8, the controller can track 8 openpages and overall efficiency is much improved relative to a command queue look-ahead value of Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide413Figure with Command Queue Look-ahead Depth of 8There is a trade-off between efficiency and resource usage. Higher command queuelook-ahead values are likely to increase bank management efficiency, but at the costof higher resource usage. Smaller command queue look-ahead values may be lessefficient, but also consume fewer resources. Also, a command queue look-ahead valuegreater than 4 may cause timing violations for interfaces approaching their : If you set Command Queue Look-ahead depth to a value greater than 4, you may notbe able to run the interface at maximum achieve an optimized balance of controller efficiency versus resource usage andfrequency, you must understand your traffic patterns. You should simulate your designwith a variety of controller settings to observe the results of different : User-selectable Command Queue Look-ahead depth is available only when using thesoft memory controller. For the hard memory controller, the Command Queue Look-ahead depth value is hard-coded to Additive Latency and Bank InterleavingUsing additive latency together with bank interleaving increases the bandwidth of following figure shows an example of bank interleaving in a read operationwithout additive latency. The example uses bank interleave reads with CAS latency of 4, and burst length of Interleaving Without Additive LatencyCommandCKCK#DQSDQT0[1][3][2][4][5 ]ACTACTREADREADREADACTBank xRow nBank zRow nBank zCol nBank xCol nBank yRow nBank yCol nT1T2T3T4T5T6T7T8T9T10T11T12T13T14Addres sA1012 Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide414The following sequence of events describes the above figure:1. The controller issues an activate command to open the bank, which activates bankx and the row in After tRCD time, the controller issues a read with auto-precharge command to thespecified Bank y receives an activate command after tRRD The controller cannot issue an activate command to bank z at its optimal locationbecause it must wait for bank x to receive the read with auto-prechargecommand, thus delaying the activate command for one clock The delay in activate command causes a gap in the output data from the : If you use additive latency of 1, the latency affects only read commands and not thetiming for write following figure shows an example of bank interleaving in a read operation withadditive latency. The example uses bank interleave reads with additive latency of 3,CAS latency of 4, and burst length of 4. In this configuration, the controller issuesback-to-back activate and read with auto-precharge Interleaving With Additive LatencyCKCK#DQSDQT0T1T2T3T4T5T6T7T8T9T10 T11T12T13T14CommandACTREADREADACTAddress A10ACTREADBank xRow nBank yCol nBank yRow nBank zCol nBank zRow nBank xCol n[1][2][3][4][5]The following sequence of events describes the above figure:1. The controller issues an activate command to bank The controller issues a read with auto precharge command to bank x right afterthe activate command, before waiting for the tRCD The controller executes the read with auto-precharge command tRCD time later onthe rising edge 4 cycles of CAS latency later, the SDRAM device issues the data on the data For burst length of 4, you need 2 cycles for data transfer. With 2 clocks of givingactivate and read with auto-precharge commands, you get a continuous flow ofoutput Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide415Compare the efficiency results in the two preceding figures: bank interleave reads with no additive latency, CAS latency of 4, and burst lengthof 4 (first figure),Number of active cycles of data transfer = number of cycles = 15Efficiency = 40% bank interleave reads with additive latency of 3, CAS latency of 4, and burstlength of 4 (second figure),Number of active cycles of data transfer = number of cycles = 14Efficiency = approximately 43%The interleaving reads used with additive latency increases efficiency by approximately3%.Note: Additive latency improves the efficiency of back-to-back interleaved reads or writes,but not individual random reads or User-Controlled RefreshThe requirement to periodically refresh memory contents is normally handled by thememory controller; however, the User Controlled Refresh option allows you todetermine when memory refresh specific knowledge of traffic patterns, you can time the refresh operations so thatthey do not interrupt read or write operations, thus improving : If you enable the auto-precharge control, you must ensure that the average periodicrefresh requirement is met, because the controller does not issue any refreshes untilyou instruct it Back-to-Back User-Controlled Refresh UsageThe following diagram illustrates the user-controlled refresh for the hard memorycontroller (HMC), using the MMR Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide416Figure Refresh via MMR InterfaceTo perform a user-controlled refresh in the hard memory controller using the MMRinterface, follow these steps:1. Write to the cfg_user_rfsh_en register (address=0x019) with the data0x0000_0010 to enable user Write to the mmr_refresh_req register (address=0x02c) with the data0x0000_0001 to send a refresh request to rank : Each bit corresponds to one specific rank; for example, data0x0000_0002 corresponds to rank 1. You may program refreshes to more than one rank at a Read from the mmr_refresh_ack register (address=0x032) until thereaddatavalid signal is asserted and the read data is 1'b1, indicating that arefresh operation is in You can issue the next refresh request only after you see the the acknowledgesignal asserted (at time 4).5. Write to the mmr_refresh_req register (address=0x02c) with data0x0000_0000 to disable the refresh You can implement a timer to track tRFC before sending the next Frequency of OperationCertain frequencies of operation give you the best possible latency based on thememory parameters. The memory parameters you specify through the parametereditor are converted to clock cycles and rounded Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide417If you are using a memory device that has tRCD = 20 ns and running the interface at100 MHz, you get the following results: For full-rate implementation (tCk = 10 ns):tRCD convert to clock cycle = 20/10 = 2. For half rate implementation (tCk = 20 ns):tRCD convert to clock cycle = 20/20 = 1This frequency and parameter combination is not easy to find because there are manymemory parameters and frequencies for the memory device and the controller to device parameters are optimal for the speed at which the device is designedto run, so you should run the device at that most cases, the frequency and parameter combination is not optimal. If you areusing a memory device that has tRCD = 20 ns and running the interface at 133 MHz,you get the following results: For full-rate implementation (tCk = ns):tRCD convert to clock cycle = 20 = , rounded up to 3 clock cycles ns. For half rate implementation (tCk = 15 ns):tRCD convert to clock cycle = 20/15 = , rounded up to 2 clock cycles or 30 is no latency difference for this frequency and parameter Series of Reads or WritesPerforming a series of reads or writes from the same bank and row increasescontroller case shown in the second figure in the "Bank Management Efficiency" topicdemonstrates that a read performed from the same row takes only clock cyclesto transfer data, making the controller 27% not perform random reads or random writes. When you perform reads and writesto random locations, the operations require row and bank changes. To change banks,the controller must precharge the previous bank and activate the row in the new if you change the row in the same bank, the controller has to close the bank(precharge) and reopen it again just to open a new row (activate). Because of theprecharge and activate commands, efficiency can decrease by as much as 3 15%, asthe controller needs more time to issue a read or you must perform a random read or write, use additive latency and bankinterleaving to increase efficiency depends on the method of data transfer between the memorydevice and the FPGA, the memory standards specified by the memory device vendor,and the type of memory Data ReorderingData reordering and command reordering can both contribute towards achievingcontroller Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide418The Data Reordering feature allows the single-port memory controller to change theorder of read and write commands to achieve highest efficiency. You can enable datareordering by turning on Enable Reordering on the Controller Settings tab of theparameter the soft memory controller, inter-bank data reordering serves to minimize busturnaround time by optimizing the ordering of read and write commands going todifferent banks; commands going to the same bank address are not Reordering for Minimum Bus TurnaroundIn the hard memory controller, inter-row data reordering serves to minimize tRC byreordering commands going to different bank and row addresses; command going tothe same bank and row address are not reordered. Inter-row data reordering inheritsthe minimum bus turnaround time benefit from inter-bank data Reordering for Minimum Starvation ControlThe controller implements a starvation counter to ensure that lower-priority requestsare not forgotten as higher-priority requests are reordered for starvation control, a counter is incremented for every command served. You can seta starvation limit, to ensure that a waiting command is served immediately upon thestarvation counter reaching the specified example, if you set a starvation limit of 10, a lower-priority command will betreated as high priority and served immediately, after ten other commands are servedbefore Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Command ReorderingData reordering and command reordering can both contribute towards achievingcontroller protocols are naturally inefficient, because commands are fetched and processedsequentially. The DDRx command and DQ bus are not fully utilized as few potentialcycles are wasted and degrading the efficiencyThe command reordering feature, or look-ahead bank management feature, allows thecontroller to issue bank management commands early based on incoming patterns, sothat when the command reaches the memory interface, the desired page in memory isalready command cycles during the tRCD period are idle and the bank-managementcommands are issued to next access banks. When the controller is serving the nextcommand, the bank is already precharged. The command queue look-ahead depth isconfigurable from 1-16, to specify how many read or write requests the look-aheadbank management logic examines. With the look-ahead command queue, ifconsecutive write or read requests are to a sequential address with same row, samebank, and column incremental by 1, the controller merges the write or read requestsat the memory transaction into a single With and Without Look-Ahead Bank Mangement Feature12 Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide420Compare the following efficiency results for the above figure:Table Results for Above FigureWithout Look-ahead BankManagementWith Look-ahead Bank ManagementActive cycles of data transfer1212Total number of cycles2016Approximate efficiency60%75%In the above table, the use of look-ahead bank management increases efficiency by15%. The bank look-ahead pattern verifies that the system is able to completely hidethe bank precharge and activation for specific sequences in which the minimumnumber of page-open transactions are placed between transactions to closed pages toallow bank look-ahead to occur just in time for the closed pages. An optimal systemwould completely hide bank activation and precharge performance penalties for thebank look-ahead traffic pattern and achieve 100% efficiency, ignoring BandwidthBandwidth depends on the efficiency of the memory controller controlling the datatransfer to and from the memory can express bandwidth as follows:Bandwidth = data width (bits) data transfer rate (1/s) rate transfer (1/s) = 2 frequency of operation (4 for QDR SRAM interfaces).The following example shows the bandwidth calculation for a 16-bit interface that has70% efficiency and runs at 200 MHz frequency:Bandwidth = 16 bits 2 clock edges 200 MHz 70% = typically has an efficiency of around 70%, but when you use the memorycontroller, efficiency can vary from 10 to 92%.In QDR II+ or QDR II SRAM the IP implements two separate unidirectional write andread data buses, so the data transfer rate is four times the clock rate. The datatransfer rate for a 400-MHz interface is 1, 600 Mbps. The efficiency is the percentageof time the data bus is transferring data. It is dependent on the type of memory. Forexample, in a QDR II+ or QDR II SRAM interface with separate write and read ports,the efficiency is 100% when there is an equal number of read and write operations onthese memory Optimizing Controller PerformanceUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide42113 Intel Stratix 10 EMIF IP DebuggingThis chapter discusses issues and strategies for debugging your external memoryinterface support resources for external memory interface debugging, visit the ExternalMemory Interfaces Support Center on Links External Memory Interfaces Support Center Analyzing Timing of Memory Interface Configuration Performance IssuesThere are a large number of interface combinations and configurations possible in anIntel design, therefore it is impractical for Intel to explicitly state the achievable fMAXfor every seeks to provide guidance on typical performance, but this data is subject tomemory component timing characteristics, interface widths, depths directly affectingtiming deration requirements, and the achieved skew and timing numbers for aspecific timing issues should generally not be affected by interface loading or layoutcharacteristics. In general, the Intel performance figures for any given device familyand speed-grade combination should usually be resolve FPGA (PHY and PHY reset) timing issues, refer to the Analyzing Timing ofMemory IP interface timing (address and command, half-rate address and command,read and write capture) is directly affected by any layout issues (skew), loading issues(deration), signal integrity issues (crosstalk timing deration), and component speedgrades (memory timing size and tolerance). Intel performance figures are typicallystated for the default (single rank, unbuffered DIMM) case. Intel provides additionalexpected performance data where possible, but the fMAX is not achievable in allconfigurations. Intel recommends that you optimize the following items wheneverinterface timing issues occur: Improve PCB layout tolerances Use a faster speed grade of memory component Ensure that the interface is fully and correctly terminated Reduce the loading (reduce the deration factor)UG-S10EMI | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of Interface Configuration Bottleneck and Efficiency IssuesDepending on the transaction types, efficiency issues can exist where the achieveddata rate is lower than expected. Ideally, these issues should be assessed andresolved during the simulation stage because they are sometimes impossible to solvelater without rearchitecting the interface has a maximum theoretical data rate derived from the clock frequency,however, in practise this theoretical data rate can never be achieved continuously dueto protocol overhead and bus turnaround your desired configuration to ensure that you have specified a suitableexternal memory family and that your chosen controller configuration can achieveyour required can be assessed in several different ways, and the primary requirement isan achievable continuous data rate. The local interface signals combined with thememory interface signals and a command decode trace should provide adequatevisibility of the operation of the IP to understand whether your required data rate issufficient and the cause of the efficiency show if under ideal conditions the required data rate is possible in the chosentechnology, follow these steps:1. Use the memory vendors own testbench and your own transaction Use either your own driver, or modify the provided example driver, to replicate thetransaction types typical of your Simulate this performance using your chosen memory controller and decide if theachieved performance is still the following points that may cause efficiency or bottleneck issues at thisstage: Identify the memory controller rate (full, half, or quarter) and commands, whichmay take two or four times longer than necessary Determine whether the memory controller is starved for data by observing theappropriate request signals. Determine whether the memory controller processor transactions at a ratesufficient to meet throughput requirements by observing appropriate signals,including the local ready has several versions and types of memory controller, and where possible you canevaluate different configurations based on the results of the first using either a faster interface, or a different memory type to better alignyour data rate requirements to the IP available directly from also provides stand-alone PHY configurations so that you may develop customcontrollers or use third-party controllers designed specifically for your Functional Issue EvaluationFunctional issues occur at all frequencies (using the same conditions) and are notaltered by speed grade, temperature, or PCB changes. You should use functionalsimulation to evaluate functional Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide423The Intel FPGA IP includes the option to autogenerate a testbench specific to your IPconfiguration, which provides an easy route to functional following issues should be considered when trying to debug functional issues in asimulation Intel IP Memory ModelIntel memory IP autogenerates a generic simplified memory model that works in allcases. This simple read and write model is not designed or intended to verify allentered IP parameters or transaction Intel-generated memory model may be suitable to evaluate some limitedfunctional issues, but it does not provide comprehensive functional Vendor Memory ModelContact the memory vendor directly, because many additional models are availablefrom the vendor's support using memory vendor models, ensure that the model is correctly defined for thefollowing characteristics: Speed grade Organization Memory allocation Maximum memory usage Number of ranks on a DIMM Buffering on the DIMM ECCNote: Refer to the file supplied with the memory vendor model, for moreinformation about how to define this information for your configuration. Also refer toTranscript Window Messages, for more : Intel does not provide support for vendor-specific memory simulation vendor models output a wealth of information regarding any deviceviolations that may occur because of incorrectly parameterized Transcript Window MessagesWhen you are debugging a functional issue in simulation, vendor models typicallyprovide much more detailed checks and feedback regarding the interface and theiroperational requirements than the Intel generic general, you should use a vendor-supplied model whenever one is using second-source vendor models in preference to the Intel generic issues can be traced to incorrectly configured IP for the specified memorycomponents. Component data sheets usually contain settings information for severaldifferent speed grades of memory. Be aware data sheet specify parameters in fixedunits of time, frequencies, or clock Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide424The Intel generic memory model always matches the parameters specified in the IP,as it is generated using the same engine. Because vendor models are independent ofthe IP generation process, they offer a more robust IP parameterization simulation, review the transcript window messages and do not rely on theSimulation Passed message at the end of simulation. This message only indicates thatthe example driver successfully wrote and then read the correct data for a single if the interface functionally passes in simulation, the vendor model may reportoperational violations in the transcript window. These reported violations oftenspecifically explain why an interface appears to pass in simulation, but fails models typically perform checks to ensure that the following types ofparameters are correct: Burst length Burst order tMRD tMOD tRFC tREFPDEN tRP tRAS tRC tACTPDEN tWR tWRPDEN tRTP tRDPDEN tINIT tXPDLL tCKE tRRD tCCD tWTR tXPR PRECHARGE CAS length Drive strength AL tDQS CAS_WL13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide425 Refresh Initialization tIH tIS tDH tDSIf a vendor model can verify all these parameters are compatible with your chosencomponent values and transactions, it provides a specific insight into hardwareinterface Modifying the Example Driver to Replicate the FailureOften during debugging, you may discover that the example driver design workssuccessfully, but that your custom logic encounters data the example design works but your custom design doesn't, the underlyingproblem may be either of the following: Related to the way that the local interface transactions are occurring. You shouldprobe and compare using the Signal Tap II analyzer. Related to the types or format of transactions on the external memory should try modifying the example design to replicate the issues on the local interface side include: Incorrect local-address-to-memory-address translation causing the word order tobe different than expected. Refer to Burst Definition in your memory vendor datasheet. Incorrect timing on the local interface. When your design requests a transaction,the local side must be ready to service that transaction as soon as it is acceptedwithout any pause. For more information, refer to the Avalon Interface Specification .The default example driver performs only a limited set of transaction types,consequently potential bus contention or preamble and postamble issues can often bemasked in its default operation. For successful debugging, isolate the custom logictransaction types that are causing the read and write failures and modify the exampledriver to demonstrate the same issue. Then, you can try to replicate the failure in RTLsimulation with the modified Intel Stratix 10 interfaces, you can enable the Traffic Generator in the exampledesign, allowing you to use the EMIF Debug Toolkit to configure different trafficpattern for debug problem that you can replicate in RTL simulation indicates a potential bug in the should recheck the IP parameters. A problem that you can not replicate in RTLsimulation indicates a timing issue on the PCB. You can try to replicate the issue on anIntel development platform to rule out a board : Ensure that all PCB timing, loading, skew, and deration information is correctly definedin the Intel Quartus Prime software. The timing report is inaccurate if this initial datais not Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide426Functional simulation allows you to identify any issues with the configuration of eitherthe memory controller or the PHY. You can then check the operation against both thememory vendor data sheet and the respective JEDEC specification. After you resolvefunctional issues, you can start testing more information about simulation, refer to the Simulation Links Avalon Interface Specifications Intel Stratix 10 EMIF Simulating Memory IP on page Timing Issue CharacteristicsThe PHY and controller combinations autogenerate timing constraint files to ensurethat the PHY and external interface are fully constrained and that timing is analyzedduring compilation. However, timing issues can still occur. This topic discusses how toidentify and resolve any timing issues that you may issues typically fall into two distinct categories: FPGA core timing reported issues External memory interface timing issues in a specific mode of operation or on aspecific PCBTiming Analyzer reports timing issues in two categories: core to core and core to IOEtransfers. These timing issues include the PHY and PHY reset sections in the TimingAnalyzer Report DDR subsection of timing analysis. External memory interface timingissues are specifically reported in the Timing Analyzer Report DDR subsection,excluding the PHY and PHY reset. The Report DDR PHY and PHY reset sections onlyinclude the PHY, and specifically exclude the controller, core, PHY-to-controller andlocal interface. Intel Quartus Prime timing issues should always be evaluated andcorrected before proceeding to any hardware timing issues are usually Intel Quartus Prime timing issues, which are notreported in the Intel Quartus Prime software, if incorrect or insufficient PCB topologyand layout information is not supplied. PCB timing issues are typically characterized bycalibration failure, or failures during user mode when the hardware is heated orcooled. Further PCB timing issues are typically hidden if the interface frequency Evaluating FPGA Timing IssuesUsually, you should not encounter timing issues with Intel-provided IP unless yourdesign exceeds Intel's published performance range or you are using a device forwhich the Intel Quartus Prime software offers only preliminary timing model , timing issues can occur in the following circumstances: The .sdc files are incorrectly added to the Intel Quartus Prime project Intel Quartus Prime analysis and synthesis settings are not correct Intel Quartus Prime Fitter settings are not correct13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide427For all of these issues, refer to the correct user guide for more information aboutrecommended settings and follow these steps:1. Ensure that the IP generated .sdc files are listed in the Intel Quartus Prime TimingAnalyzer files to include in the project Ensure that Analysis and Synthesis Settings are set to OptimizationTechnique Speed .3. Ensure that Fitter Settings are set to Fitter Effort Standard Fit .4. Use Timing Analyzer Report Ignored Constraints, to ensure that .sdc files aresuccessfully Use Timing Analyzer Report Unconstrained Paths, to ensure that all criticalpaths are correctly complex timing problems can occur if any of the following conditions are true: The design includes multiple PHY or core projects Devices where the resources are heavily used The design includes wide, distributed, maximum performance interfaces in largedie sizesAny of the above conditions can lead to suboptimal placement results when the PHY orcontroller are distributed around the FPGA. To evaluate such issues, simplify thedesign to just the autogenerated example top-level file and determine if the coremeets timing and you see a working interface. Failure implies that a morefundamental timing issue exists. If the standalone design passes core timing, evaluatehow this placement and fit is different than your complete LogicLock regions, or design partitions to better define the placement of yourmemory controllers. When you have your interface standalone placement, repeat foradditional interfaces, combine, and finally add the rest of your , use fitter seeds and increase the placement and router effort Evaluating External Memory Interface Timing IssuesExternal memory interface timing issues usually relate to the FPGA input and outputcharacteristics, PCB timing, and the memory component FPGA input and output characteristics are usually fixed values, because the IOEstructure of the devices is fixed. Optimal PLL characteristics and clock routingcharacteristics do have an effect. Assuming the IP is correctly constrained withautogenerated assignments, and you follow implementation rules, the design shouldreach the stated performance component characteristics are fixed for any given component or using faster components or DIMMs in marginal cases when PCB skew may besuboptimal, or your design includes multiple ranks when deration may cause readcapture or write timing challenges. Using faster memory components often reducesthe memory data output skew and uncertainty easing read capture, and lowering thememory s input setup and hold requirement, which eases write Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide428Increased PCB skew reduces margins on address, command, read capture and writetiming. If you are narrowly failing timing on these paths, consider reducing the boardskew (if possible), or using faster memory. Address and command timing typicallyrequires you to manually balance the reported setup and hold values with thededicated address and command phase in the to the respective IP user guide for more multiple-rank UDIMM interfaces can place considerable loading on theFPGA driver. Typically a quad rank interface can have thirty-six loads. In multiple-rankconfigurations, Intel's stated maximum data rates are not likely to be achievablebecause of loading deration. Consider using different topologies, for exampleregistered DIMMs, so that the loading is because of increased loading, or suboptimal layout may result in a lower thandesired operating frequency meeting timing. You should close timing in the TimingAnalyzer software using your expected loading and layout rules before committing toPCB that any design with an Intel PHY is correctly constrained and meets timing inthe Timing Analyzer software. You must address any constraint or timing failuresbefore testing more information about timing constraints, refer to the Timing Analysis LinksAnalyzing Timing of Memory Verifying Memory IP Using the Signal Tap II Logic AnalyzerThe Signal Tap II logic analyzer shows read and write activity in the more information about using the Signal Tap II logic analyzer, refer to the DesignDebugging Using the Signal Tap II Embedded Logic Analyzer chapter in volume 3 ofthe Intel Quartus Prime HandbookTo add the Signal Tap II logic analyzer, follow these steps:1. On the Tools menu click Signal Tap II Logic Analyzer .2. In the Signal Configuration window next to the Clock box, click ... (BrowseNode Finder). the memory interface system clock (typically * phy_clk) in the Named box,for Filter select Signal Tap II: presynthesis and click Select the memory interface clock that is exposed to the user Click Under Signal Configuration, specify the following settings: For Sample depth, select 512 For RAM type, select Auto For Trigger flow control, select Sequential For Trigger position, select Center trigger position ForTrigger conditions , select 113 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide4297. On the Edit menu, click Add Search for specific nodes that you want to monitor, and click : Signal Tap can probe only nodes that are exposed to FPGA core logic. Referto pin descriptions for help in deciding which signals to Decide which signal and event you want to trigger on, and set the correspondingtrigger On the File menu, click Save, to save the Signal Tap II . stp file to your : If you see the message Do you want to enable Signal Tap II file for the current project, click After you add signals to the Signal Tap II logic analyzer, recompile your design byclicking Start Compilation on the Processing Following compilation, verify that Timing Analyzer timing analysis Connect the development board to your On the Tools menu, click Signal Tap II Logic the correct <project_name>.sof file to the SOF Manager:a. Click ... to open the Select Program Files dialog Select <your_project_name>. Click To download the file, click the Program Device When the example design including Signal Tap II successfully downloads to yourdevelopment board, click Run Analysis to run once, or click Autorun Analysis torun LinksDesign Debugging with the Signal Tap Logic Signals to Monitor with the Signal Tap II Logic AnalyzerThis topic lists the memory controller signals you should consider analyzing fordifferent memory interfaces. This list is not exhaustive, but is a starting the following signals: amm_addr amm_rdata amm_rdata_valid amm_read_req amm_ready amm_wdata amm_write_req fail pass13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide430 afi_cal_fail afi_cal_success test_complete be_reg (QDRII only) pnf_per_bit rdata_reg rdata_valid_reg data_out data_in written_data_fifo|data_out usequencer|state * usequencer|phy_seq_rdata_valid usequencer|phy_seq_read_fifo_q usequencer|phy_read_increment_vfifo * usequencer|phy_read_latency_counter uread_datapath|afi_rdata_en uread_datapath|afi_rdata_valid uread_datapath|ddio_phy_dq qvld_wr_address * qvld_rd_address * Hardware Debugging GuidelinesBefore debugging your design, confirm that it follows the recommended design to the Design Flow chapter in volume 1 of the External Memory keep a record of tests, to avoid repeating the same tests later. To startdebugging the design, perform the following initial LinksRecommended Design Create a Simplified Design that Demonstrates the Same IssueTo help debugging, create a simple design that replicates the simple design should compile quickly and be easy to understand. The EMIF IPgenerates an example top-level file that is ideal for debugging. The example top-levelfile uses all the same parameters, pin-outs, and so you are using the Intel Stratix 10 example design and the Traffic Generator , youcan configure the traffic pattern using the EMIF Debug Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide431Related LinksExternal Memory Interface Debug Measure Power Distribution NetworkMeasure voltages of the various power supplies on their hardware developmentplatform over a suitable time base and with a suitable that you use an appropriate probe and grounding scheme. In addition, take themeasurements directly on the pins or vias of the devices in question, and with thehardware Measure Signal Integrity and Setup and Hold MarginMeasure the signals on the PCB. When measuring any signal, consider the edge rate ofthe signal, not just its frequency. Modern FPGA devices have very fast edge rates,therefore you must use a suitable oscilloscope, probe, and grounding scheme whenyou measure the can take measurements to capture the setup and hold time of key signal classeswith respect to their clock or strobe. Ensure that the measured setup and hold marginis at least better than that reported in the Intel Quartus Prime software. A worsemargin indicates a timing discrepancy somewhere in the project; however, this issuemay not be the cause of your Vary VoltageVary the voltage of your system, if you suspect a marginality the voltage usually causes devices to operate faster and also usuallyprovides increased noise Operate at a Lower SpeedTest the interface at a lower speed. If the interface works at a lower speed, theinterface is correctly pinned out and the interface fails at a lower speed, determine if the test is valid. Many high-speedmemory components have a minimal operating frequency, or require subtly differentconfigurations when operating at a lower example, DDR3 SDRAM typically requires modification to the following parametersif you want to operate the interface at lower speeds: tMRD tWTR CAS latency and CAS write latency13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Determine Whether the Issue Exists in Previous Versions ofSoftwareHardware that works before an update to either the Intel Quartus Prime software orthe memory IP indicates that the development platform is not the , the previous generation IP may be less susceptible to a PCB issue, maskingthe Determine Whether the Issue Exists in the Current Version ofSoftwareDesigns are often tested using previous generations of Intel software or may not be upgraded for various reasons: Multiple engineers are on the same project. To ensure compatibility, a commonrelease of Intel software is used by all engineers for the duration of the productdevelopment. The design may be several releases behind the current Intel QuartusPrime software version. Many companies delay before adopting a new release of software so that they canfirst monitor Internet forums to get a feel for how successful other users say thesoftware is. Many companies never use the latest version of any software, preferring to waituntil the first service pack is released that fixes the primary issues. Some users may only have a license for the older version of the software and canonly use that version until their company makes the financial decision to upgrade. The local interface specification from Intel FPGA IP to the customer's logicsometimes changes from software release to software release. If you have alreadyspent resources designing interface logic, you may be reluctant to repeat thisexercise. If a block of code is already signed off, you may be reluctant to modify itto upgrade to newer IP from all of the above scenarios, you must determine if the issue still exists in the latestversion of the Intel software. Bug fixes and enhancements are added to the Intel FPGAIP every release. Depending on the nature of the bug or enhancement, it may notalways be clearly documented in the release , if the latest version of the software resolves the issue, it may be easier todebug the version of software that you are Try A Different PCBIf you are using the same Intel FPGA IP on several different hardware platforms,determine whether the problem occurs on all platforms or just on instances of the same PCB, or multiple instances of the same interface, onphysically different hardware platforms may exhibit different behavior. You candetermine if the configuration is fundamentally not working, or if some form ofmarginality is involved in the Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide433Issues are often reported on the alpha build of a development platform. These areproduced in very limited numbers and often have received limited bare-board testing,or functional testing. These early boards are often more unreliable than productionquality , if the IP is from a previous project to help save development resources,determine whether the specific IP configuration works on a previous Try Other ConfigurationsDesigns are often quite large, using multiple blocks of IP in many differentcombinations. Determine whether any other configurations work correctly on thedevelopment full project may have multiple external memory controllers in the same device, ormay have configurations where only half the memory width or frequency is out what does and does not work to help the debugging of the Debugging ChecklistThe following checklist is a good starting point when debugging an external a different IP parameters at the operating frequency (tMRD, tWTR for example).Ensure you have constrained your design with proper timing deration and have closed the design. If it fails in simulation, it will fail in and assign RZQ (OCT).Measure the power distribution network (PDN).Measure signal setup and hold FPGA and cool the at a lower or higher board timing and trace 13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide434CheckItemCheck LVDS and clock sources, I/O voltages and PLL clock source, specification, and to a smaller interface width or a single Catagorizing Hardware IssuesThe following topics divide issues into categories. By determining which category (orcategories) an issue belongs in, you may be able to better focus on the cause of issues fall into three categories: Signal integrity issues Hardware and calibration issues Intermittent Signal Integrity IssuesMany design issues, including some at the protocol layer, can be traced back to signalintegrity problems. You should check circuit board construction, power systems,command, and data signaling to determine if they meet infrequent, random errors exist in the memory subsystem, product reliabilitysuffers. Check the bare circuit board or PCB design file. Circuit board errors can causepoor signal integrity, signal loss, signal timing skew, and trace impedance traces with unbalanced lengths or signals that are routed too closelytogether can cause Characteristics of Signal Integrity IssuesSignal integrity problems often appear when the performance of the hardware designis design may not always initialize and calibrate correctly, or may exhibit occasionalbit errors in user mode. Severe signal integrity issues can result in total failure of aninterface at certain data rates, and sporadic component failure because of electricalstress. PCB component variance and signal integrity issues often show up as failureson one PCB, but not on another identical board. Timing issues can have a similarcharacteristic. Multiple calibration windows or significant differences in the calibrationresults from one calibration to another can also indicate signal integrity Evaluating SignaI Integrity IssuesSignal integrity problems can only really be evaluated in two ways: direct measurement using suitable test equipment like an oscilloscope and probe simulation using a tool like HyperLynx or Allegro PCB SICompare signals to the respective electrical specification. You should look forovershoot and undershoot, non-monotonicity, eye height and width, and Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User SkewEnsure that all clocked signals, commands, addresses, and control signals arrive at thememory inputs at the same length variations cause data valid window variations between the signals,reducing margin. For example, DDR3-800 at 400 MHz has a data valid window that issmaller than 1,250 ps. Trace length skew or crosstalk can reduce this data validwindow further, making it difficult to design a reliably operating memory that the skew figure previously entered into the Intel FPGA IP matches thatactually achieved on the PCB, otherwise Intel Quartus Prime timing analysis of theinterface is CrosstalkCrosstalk is best evaluated early in the memory design the clock-to-data strobes, because they are bidirectional. Measure the crosstalkat both ends of the line. Check the data strobes to clock, because the clocks areunidirectional, these only need checking at the memory end of the Power SystemSome memory interfaces draw current in spikes from their power delivery system asSDRAMs are based on capacitive memory are read and refreshed one at a time, which causes dynamic currents that canstress any power distribution network (PDN). The various power rails should bechecked either at or as close as possible to the SDRAM power pins. Ideally, you shoulduse a real-time oscilloscope set to fast glitch triggering to check the power Clock SignalsThe clock signal quality is important for any external memory include frequency, digital core design (DCD), high width, low width,amplitude, jitter, rise, and fall Read Data Valid Window and Eye DiagramThe memory generates the read signals. Take measurements at the FPGA end of ease read diagram capture, modify the example driver to mask writes or modify thePHY to include a signal that you can trigger on when performing Write Data Valid Window and Eye DiagramThe FPGA generates the write signals. Take measurements at the memory device endof the ease write diagram capture, modify the example driver to mask reads or modify thePHY export a signal that is asserted when performing OCT and ODT UsageModern external memory interface designs typically use OCT for the FPGA end of theline, and ODT for the memory component end of the line. If either the OCT or ODT areincorrectly configured or enabled, signal integrity problems Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide436If the design uses OCT, the RZQ pin must be placed correctly for the OCT to work. Ifyou do not place the RZQ pin, the Intel Quartus Prime software allocates themautomatically with the following warning:Critical Warning(12677): No exact pin location assignment(s) for 1 pins of 122 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. If you see these warnings, the RZQ pin may have been allocated to a pin that does nothave the required external resistor present on the board. This allocation renders theOCT circuit faulty, resulting in unreliable calibration and or interface behavior. The pinswith the required external resistor must be specified in the Intel Quartus the FPGA, ensure that you perform the following: Connect the RZQ pin to the correct resistors and pull-down to ground in theschematic or PCB. Contain the RZQ pins within a bank of the device that is operating at the sameVCCIO voltage as the interface that is terminated. Review the Fitter Pin-Out file for RZQ pins to ensure that they are on the correctpins, and that only the correct number of calibration blocks exists in your design. Check in the fitter report that the input, output, and bidirectional signals withcalibrated OCT all have the termination control block applicable to the associatedRZQ the memory components, ensure that you perform the following: Connect the required resistor to the correct pin on each and every component,and ensure that it is pulled to the correct voltage. Place the required resistor close to the memory component. Correctly configure the IP to enable the desired termination at initialization time. Check that the speed grade of memory component supports the selected ODTsetting. Check that the second source part that may have been fitted to the PCB, supportsthe same ODT settings as the Hardware and Calibration IssuesHardware and calibration issues have the following definitions: Calibration issues result in calibration failure, which usually causes thectl_cal_fail signal to be asserted. Hardware issues result in read and write failures, which usually causes the passnot fail (pnf) signal to be : Ensure that functional, timing, and signal integrity issues are not the direct cause ofyour hardware issue, as functional, timing or signal integrity issues are usually thecause of any hardware Postamble Timing Issues and MarginThe postamble timing is set by the PHY during Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide437You can diagnose postamble issues by viewing the pnf_per_byte signal from theexample driver. Postamble timing issues mean only read data is corrupted during thelast beat of any read Intermittent Issue EvaluationIntermittent issues are typically the hardest type of issue to debug they appearrandomly and are hard to that occur during run-time indicate a data-related issue, which you can identifyby the following actions: Add the Signal Tap II logic analyzer and trigger on the post-trigger pnf Use a stress pattern of data or transactions, to increase the probability of theissue Heat up or cool down the system Run the system at a slightly faster frequencyIf adding the Signal Tap II logic analyzer or modifying the project causes the issue togo away, the issue is likely to be placement or timing that occur at start-up indicate that the issue is related to calibration, which youcan identify by the following actions: Modify the design to continually calibrate and reset in a loop until the error isobserved Where possible, evaluate the calibration margin either from the debug toolkit orsystem console. Capture the calibration error stage or error code, and use this information withwhatever specifically occurs at that stage of calibration to assist with yourdebugging of the LinksExternal Memory Interface Debug Debugging Intel Stratix 10 EMIF IPYou can debug hardware failures by connecting to the EMIF Debug Toolkit or byexporting an Avalon-MM slave port, from which you can access information gatheredduring calibration. You can also connect to this port to mask ranks and to can access the exported Avalon-MM port in two ways: Via the External Memory Interface Debug Toolkit Via On-Chip Debug (core logic on the FPGA) External Memory Interface Debug ToolkitThe External Memory Interface Debug Toolkit provides access to data collected by theNios II sequencer during memory calibration, and allows you to perform certain Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide438The External Memory Interface Debug Toolkit provides access to data including thefollowing: General interface information, such as protocol and interface width Calibration results per group, including pass/fail status, failure stage, and delaysettingsYou can also perform the following tasks: Mask ranks from calibration (you might do this to skip specific ranks) Request recalibration of the On-Chip Debug for Intel Stratix 10The On-Chip Debug feature allows user logic to access the same debug capabilities asthe External Memory Interface Toolkit. You can use On-Chip Debug to monitor thecalibration results of an external memory interface, without a connected use On-Chip Debug, you need a C header file which is provided as part of theexternal memory interface IP. The C header file defines data structures that containcalibration data, and definitions of the commands that can be sent to the On-Chip Debug feature accesses the data structures through the Avalon-MM portthat is exposed by the EMIF IP when you turn on debugging Configuring Your EMIF IP for Use with the Debug ToolkitThe Intel Stratix 10 EMIF Debug Interface IP core contains the access point throughwhich the EMIF Debug Toolkit reads calibration data collected by the Nios II an EMIF IP Core to an Intel Stratix 10 EMIF Debug InterfaceFor the EMIF Debug Toolkit to access the calibration data for a Intel Stratix 10 EMIF IPcore, you must connect one of the EMIF cores in each I/O column to a Intel Stratix 10EMIF Debug Interface IP core. Subsequent EMIF IP cores in the same column mustconnect in a daisy chain to the are two ways that you can add the Intel Stratix 10 EMIF Debug Interface IP coreto your design: When you generate your EMIF IP core, on the Diagnostics tab, select Add EMIFDebug Interface for the EMIF Debug Toolkit/On-Chip Debug Port; you donot have to separately instantiate a Intel Stratix 10 EMIF Debug Interface method does not export an Avalon-MM slave port. You can use this method ifyou require only EMIF Debug Toolkit access to this I/O column; that is, if you donot require On-Chip Debug Port access, or PHYLite reconfiguration access. When you generate your EMIF IP core, on the Diagnostics tab, select Export forthe EMIF Debug Toolkit/On-Chip Debug Port. Then, separately instantiate anIntel Stratix 10 EMIF Debug Interface core and connect its to_ioaux interface tothe cal_debug interface on the EMIF IP core. This method is appropriate if youwant to also have On-Chip Debug Port access to this I/O column, or PHYLitereconfiguration Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide439For each of the above methods, you must assign a unique interface ID for eachexternal memory interface in the I/O column, to identify that interface in the DebugToolkit. You can assign an interface ID using the dropdown list that appears when youenable the Debug Toolkit/On-Chip Debug Port Additional EMIF IP Cores for DebuggingAfter you have connected a Intel Stratix 10 EMIF Debug Interface to one of the EMIFIP cores in an I/O column, you must then connect subsequent EMIF IP cores in thatcolumn in a daisy-chain manner. If you don't require debug capabilities for a particularEMIF IP core, you do not have to connect that core to the daisy create a daisy chain of EMIF IP cores, follow these steps:1. On the first EMIF IP core, select Enable Daisy-Chaining for EMIF DebugToolkit/On-Chip Debug Port to create an Avalon-MM interface On the second EMIF IP core, select Export as the EMIF Debug Toolkit/On-ChipDebug Port mode, to export an Avalon-MM interface called the cal_debug_out interface of the first EMIF core to the cal_debuginterface of the second EMIF To connect more EMIF cores to the daisy chain, select the Enable Daisy-Chaining for EMIF Debug Toolkit/On-Chip Debug Port option on the secondcore, connect it to the next core using the Export option as described the process for subsequent EMIF you place any PHYLite cores with dynamic reconfiguration enabled into the same I/Ocolumn as an EMIF IP core, you should instantiate and connect the PHYLite cores in asimilar way. See the Altera PHYLite for Memory Megafunction User Guide for LinksIntel FPGA PHYLite for Parallel Interfaces IP Core User Example Tcl Script for Running the EMIF Debug ToolkitIf you want, you can run the EMIF Debug Toolkit using a Tcl script. The followingexample Tcl script is applicable to all device following example Tcl script opens a file, runs the debug toolkit, and writes theresulting calibration reports to a should adjust the variables in the script to match your design. You can then runthe script using the command quartus_sh -t # Modify the following variables for your projectset project " "# Index of the programming cable. Can be listed using "get_hardware_names"set hardware_index 1# Index of the device on the specified cable. Can be listed using "get_device_names"set device_index 1# SOF file containing the EMIF to debugset sof " "# Connection ID of the EMIF debug interface. Can be listed using "get_connections"set connection_id 2# Output file13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide440set report " "# The following code opens a project and writes its calibration reports to a $projectload_package ::quartus::external_memif_toolkitinitial ize_connectionsset hardware_name [lindex [get_hardware_names] $hardware_index]set device_name [lindex [get_device_names -hardware_name $hardware_name] $device_index]link_project_to_device -device_name $device_name -hardware_name $hardware_name -sof_file $sofestablish_connection -id $connection_idcreate_connection_report -id $connection_id -report_type summarycreate_connection_report -id $connection_id -report_type calibwrite_connection_target_report -id $connection_id -file $ Using the EMIF Debug Toolkit with Intel Stratix 10 HPS InterfacesThe External Memory Interface Debug Toolkit is not directly compatible with IntelStratix 10 HPS debug your Intel Stratix 10 HPS interface using the EMIF Debug Toolkit, you shouldcreate an identically parameterized, non-HPS version of your interface, and apply theEMIF Debug Toolkit to that interface. When you finish debugging this non-HPSinterface, you can then apply any needed changes to your HPS interface, and continueyour design Intel Stratix 10 EMIF Debugging ExamplesThis topic provides examples of debugging a single external memory interface, and ofadding additional EMIF instances to an I/O a Single External Memory Interface1. Under EMIF Debug Toolkit/On-Chip Debug Port, select Add EMIF DebugInterface.(If you want to use the On-Chip Debug Port instead of the EMIF Debug Toolkit,select Export instead.)Figure With Debug Interface Added (No Additional Ports)global_reset_reset_sinkpll_ref_clk _clock_sinkoct_conduit_endmem_conduit_en dstatus_conduit_endctrl_amm_avalon_slave _0emif_usr_clk_clock_sourceemif_usr_rese t_reset_sourceemifemif_02. If you want to connect additional EMIF or PHYLite components in this I/O column,select Enable Daisy Chaining for EMIF Debug Toolkit/On-Chip Debug Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide441Figure With cal_debug Avalon Master Exportedglobal_reset_reset_sinkpll_ref_c lk_clock_sinkoct_conduit_endmem_conduit_ endstatus_conduit_endctrl_amm_avalon_sla ve_0emif_usr_clk_clock_sourceemif_usr_re set_reset_sourcecal_debug_out_reset_rese t_sourcecal_debug_out_clk_clock_sourceca l_debug_out_avalon_masteremifemif_0cal_d ebug AvalonMaster ExportedAdding Additional EMIF Instances to an I/O Column1. Under EMIF Debug Toolkit/On-Chip Debug Port, select With cal_debug Avalon Slave Exportedglobal_reset_reset_sinkpll_ref_c lk_clock_sinkoct_conduit_endmem_conduit_ endstatus_conduit_endcal_debug_reset_res et_sinkcal_debug_clk_clock_sinkctrl_amm_ avalon_slave_0cal_debug_avalon_slaveemif _usr_clk_clock_sourceemif_usr_reset_rese t_sourceemifemif_1cal_debug AvalonSlave Exported2. Specify a unique interface ID for this EMIF If you want to connect additional EMIF or PHYLite components in this I/O column,select Enable Daisy Chaining for EMIF Debug Toolkit/On-Chip Debug With Both cal_debug Master and Slave Exportedglobal_reset_reset_sinkpll_ref_c lk_clock_sinkoct_conduit_endmem_conduit_ endstatus_conduit_endcal_debug_reset_res et_sinkcal_debug_clk_clock_sinkctrl_amm_ avalon_slave_0cal_debug_avalon_slaveemif _usr_clk_clock_sourceemif_usr_reset_rese t_sourcecal_debug_out_reset_reset_source cal_debug_out_clk_clock_sourcecal_debug_ out_avalon_masteremifemif_1cal_debug AvalonSlave Exportedcal_debug AvalonMaster the cal_debug Avalon Master, clock, and reset interfaces of the previouscomponent to the cal_debug Avalon Slave, clock, and reset interfaces of Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide442Figure Components User InterfaceThe EMIF toolkit provides a graphical user interface for communication functions provided in the toolkit are also available directly from the quartus_shTCL shell, through the external_memif_toolkit TCL package. The availablity ofTCL support allows you to create scripts to run automatically from TCL. You can findinformation about specific TCL commands by running help -pkgexternal_memif_toolkit from the quartus_sh TCL you want, you can begin interacting with the toolkit through the GUI, and laterautomate your workflow by creating TCL scripts. The toolkit GUI records a history ofthe commands that you run. You can see the command history on the History tab inthe toolkit CommunicationCommunication between the EMIF Toolkit and external memory interface connectionsis achieved using a JTAG Avalon-MM master attached to the sequencer following figure shows the structure of EMIF IP with JTAG Avalon-MM masterattached to sequencer bus Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide443Figure IP with JTAG Avalon-MM MasterSCCPHYAFITrackingJTAG Avalon Master(new)Combined ROM/RAM(Variable Size)Sequencer ManagersBridgeNIOS IIAvalon-MMAvalon-MMDebug BusSequencer BusRegister FileEMIF Setup and UseBefore using the EMIF Toolkit, you should compile your design and program the targetdevice with the resulting SRAM Object File (. sof).For designs compiled in the IntelQuartus Prime software, all debugging information resides in the .sof can run the toolkit using all your project files, or using only the Intel QuartusPrime Project File (.qpf), Intel Quartus Prime Settings File (.qsf), and .sof you have programmed the target device, you can run the EMIF Toolkit and openyour project. You can then use the toolkit to create connections to the externalmemory General WorkflowTo use the EMIF Toolkit, you must link your compiled project to a device, and create acommunication channel to the connection that you want to Linking the Project to a Device1. To launch the toolkit, select External Memory Interface Toolkit from the Toolsmenu in the Intel Quartus Prime After you have launched the toolkit, open your project and click the Initializeconnections task in the Tasks window, to initialize a list of all To link your project to a specific device on specific hardware, perform the followingsteps:13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide444a. Click the Link Project to Device task in the Tasks Select the desired hardware from the Hardware dropdown menu in the LinkProject to Device dialog Select the desired device on the hardware from the Device dropdown menu inthe Link Project to Device dialog Select SOF as the Link file type, verify that the .sof file is correct for yourprogrammed device, and click Project to Device Dialog BoxFor designs compiled in the Intel Quartus Prime software, the SOF file contains adesign hash to ensure the SOF file used to program the device matches the SOF filespecified for linking to a project. If the hash does not match, an error the toolkit successfully verifies all connections, it then attempts to determine theconnection type for each connection. Connections of a known type are listed in theLinked Connections report, and are available for the toolkit to Establishing Communication to ConnectionsAfter you have completed linking the project, you can establish communication to In the Tasks window, Click Establish Memory Interface Connection to create a connection to theexternal memory interface. Click Establish Efficiency Monitor Connection to create a connection to theefficiency monitor. Click Establish Traffic Generator Connection to create a connection to theTraffic Generator To create a communication channel to a connection, select the desired connectionfrom the displayed pulldown menu of connections, and click Ok. The toolkitestablishes a communication channel to the connection, creates a report folder forthe connection, and creates a folder of tasks for the : By default, the connection and the reports and tasks folders are namedaccording to the hierarchy path of the connection. If you want, you canspecify a different name for the connection and its You can run any of the tasks in the folder for the connection; any resulting reportsappear in the reports folder for the Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Selecting an Active InterfaceIf you have more than one external memory interface in an I/O column, you canselect one instance as the active interface for To select one of multiple EMIF instances in an I/O column, use the Set ActiveInterface dialog If you want to generate reports for the new active interface, you must firstrecalibrate the ReportsThe toolkit can generate a variety of reports, including summary, calibration, andmargining reports for external memory interface connections. To generate a supportedtype of report for a connection, you run the associated task in the tasks folder for ReportThe Summary Report provides an overview of the memory interface; it consists of thefollowing tables: Summary table. Provides a high-level summary of calibration results. This tablelists details about the connection, IP version, IP protocol, and basic calibrationresults, including calibration failures. This table also lists the estimated averageread and write data valid windows, and the calibrated read and write latencies. Interface Details table. Provides details about the parameterization of the memoryIP. This table allows you to verify that the parameters in use match the actualmemory device in use. Ranks Masked from Calibration tables (DDR3 only). Lists any ranks that weremasked from calibration when calibration occurred. Masked ranks are ignoredduring Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide446Calibration ReportThe Calibration Report provides detailed information about the margins observedduring calibration, and the settings applied to the memory interface during calibration;it consists of the following tables: Calibration Status Per Group table: Lists the pass/fail status per group. DQ Pin Margins Observed During Calibration table: Lists the DQ read/writemargins and calibrated delay settings. These are the expected margins aftercalibration, based on calibration data patterns. This table also contains DM/DBImargins, if applicable. DQS Pin Margins Observed During Calibration table: Lists the DQS marginsobserved during calibration. FIFO Settings table: Lists the VFIFO and LFIFO settings made during calibration. Latency Observed During Calibration table: Lists the calibrated read/write latency. Address/Command Margins Observed During Calibration table: Lists the marginson calibrated A/C pins, for protocols that support Address/Command On-Chip Debug Port for Intel Stratix 10 EMIF IPThe EMIF On-Chip Debug Port allows user logic to access the same calibration dataused by the EMIF Toolkit, and allows user logic to send commands to the can use the EMIF On-Chip Debug Port to access calibration data for your designand to send commands to the sequencer just as the EMIF Toolkit would. The followinginformation is available: Pass/fail status for each DQS group Read and write data valid windows for each groupIn addition, user logic can request the following commands from the sequencer: Destructive recalibration of all groups Masking of groups and ranks Generation of per-DQ pin margining data as part of calibrationThe user logic communicates through an Avalon-MM slave interface as shown Logic AccessUser logicIntel Memory InterfaceAvalon SlaveRelated LinksIntel FPGA PHYLite for Parallel Interfaces IP Core User Guide13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User EMIF On-Chip Debug PortAccess to on-chip debug is provided through software running on a Nios processorconnected to the external memory you enable the Use Soft Nios Processor for On-Chip Debug option, thesystem instantiates a soft Nios processor, and software files are provided as part ofthe EMIF on how to use the software are available in the following file: :<variation_name>/altera_emif_arch_nf_<version number>/<synth|sim>/<variation_name>_altera_emif_arch_nf_<versionnumber>_<unique ID> Access ProtocolThe On-Chip Debug Port provides access to calibration data through an Avalon-MMslave interface. To send a command to the sequencer, user logic sends a commandcode to the command space in sequencer memory. The sequencer polls the commandspace for new commands after each group completes calibration, and continuouslyafter overall calibration has communication protocol to send commands from user logic to the sequencer usesa multistep handshake with a data structure as shown below, and an algorithm asshown in the figure which struct_debug_data_struct {...// Command interactionalt_u32 requested_command;alt_u32 command_status;alt_u32 command_parameters[COMMAND_PARAM_WORDS]; ...}To send a command to the sequencer, user logic must first poll the command_statusword for a value of TCLDBG_TX_STATUS_CMD_READY, which indicates that thesequencer is ready to accept commands. When the sequencer is ready to acceptcommands, user logic must write the command parameters intocommand_parameters, and then write the command code sequencer detects the command code and replaces command_status withTCLDBG_TX_STATUS_CMD_EXE, to indicate that it is processing the command. Whenthe sequencer has finished running the command, it sets command_status toTCLDBG_TX_STATUS_RESPONSE_READY to indicate that the result of the command isavailable to be read. (If the sequencer rejects the requested command as illegal, itsets command_status to TCLDBG_TX_STATUS_ILLEGAL_CMD.)User logic acknowledges completion of the command by writingTCLDBG_CMD_RESPONSE_ACK to requested_command. The sequencer responds bysetting command_status back to STATUS_CMD_READY. (If an illegal command isreceived, it must be cleared using CMD_RESPONSE_ACK.)13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide448Figure Algorithm FlowchartRead Command_statusYesNocommand_status == CMD_READY ?EndYesNocommand_status == RESPONSE_READY ?Write command payloadWrite command codeRead command_statusWrite RESPONSE_ACK On-Die Termination CalibrationThe Calibrate Termination feature lets you determine the optimal On-DieTermination and Output Drive Strength settings for your memory Calibrate Termination function runs calibration with all available terminationsettings and selects the optimal settings based on the calibration Calibrate Termination feature is available for DDR3, DDR4, and RLDRAM Eye DiagramThe Generate Eye Diagram feature allows you to create read and write eyediagrams for each pin in your memory Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide449The Generate Eye Diagram feature uses calibration data patterns to determinemargins at each Vref setting on both the FPGA pins and the memory device pins. A fullcalibration is done for each Vref setting. Other settings, such as DQ delay chains, willchange for each calibration. At the end of a Generate Eye Diagram command, adefault calibration is run to restore original behaviorThe Generate Eye Diagram feature is available for DDR4 and QDR-IV Driver Margining for Intel Stratix 10 EMIF IPThe Driver Margining feature lets you measure margins on your memory interfaceusing a driver with arbitrary traffic measured with this feature may differ from margins measured duringcalibration, because of different traffic patterns. Driver margining is not available ifECC is use driver margining, ensure that the following signals on the driver are connectedto In-System Sources/Probes: Reset_n: An active low reset signal Pass: A signal which indicates that the driver test has completed successfully. Nofurther memory transactions must be sent after this signal is asserted. Fail: A signal which indicates that the driver test has failed. No further memorytransactions must be sent after this signal is asserted. PNF (Pass Not Fail): An array of signals that indicate the pass/fail status ofindividual bits of a data burst. The PNF should be arranged such that each bitindex corresponds to (Bit of burst * DQ width) + (DQ pin). A 1indicates pass, 0 indicates fail. If the PNF width exceeds the capacity of one In-System Probe, specify them in PNF[1] and PNF[2]; otherwise, leave them you are using the example design with a single EMIF, the In-System Sources/Probescan be enabled by adding the following line to your .qsf file:set_global_assignment -name VERILOG_MACRO"ALTERA_EMIF_ENABLE_ISSP=1" Determining MarginThe Driver Margining feature lets you measure margins on your EMIF IP interfaceusing a driver with arbitrary traffic Driver Margining feature is available only for DDR3 and DDR4 interfaces, whenECC is not Establish a connection to the desired interface and ensure that it has Select Driver Margining from the Commands folder under the target Select the appropriate In-System Sources/Probes using the drop-down If required, set additional options in the Advanced Options section:13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide450 Specify Traffic Generator to allow margining on a per-rank , margining is performed on all ranks together. Step size specifies the granularity of the driver margining process. Largerstep sizes allow faster margining but reduced accuracy. It is recommended toomit this setting. Adjust delays after margining causes delay settings to be adjusted to thecenter of the window based on driver margining results. The Margin Read, Write, Write DM, and DBI checkboxes allow you tocontrol which settings are tested during driver margining. You can uncheckboxes to allow driver margining to complete more Click OK to run the toolkit measures margins for DQ read/write and DM. The process may takeseveral minutes, depending on the margin size and the duration of the drivertests. The test results are available in the Margin Traffic Generator Traffic Generator lets you emulate traffic to the external memory, and helpsyou test, debug, and understand the performance of your external memory interfaceon hardware in a standalone fashion, without having to incorporate your entire Traffic Generator lets you customize data patterns being written to thememory, address locations accessed in the memory, and the order of write and readtransactions. You can use the traffic generator code with any FPGA architecture andmemory Configuring the Traffic Generator traffic generator replaces user logic to generate traffic to the external must incorporate the traffic generator design into the EMIF IP design during you generate the example design in the parameter editor, the traffic generatormodule and EMIF IP are generated together. If you have an example design with theTraffic Generator enabled, you can configure the traffic pattern using the EMIFDebug Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide451Figure Generator Generated with EMIF IP in Example Design ModeGenerating the External Memory Interface1. Select the FPGA and Memory On the Diagnostics tab, configure the following parameters:a. Select Use Configurable Avalon Traffic Generator Configure the desired traffic pattern, by specifying traffic patterns to bebypassed. The traffic pattern not bypassed is issued to the memoryimmediately after completion of calibration. You can choose to bypass any ofthe following traffic patterns: Bypass the default traffic pattern Specifies not to use the defaulttraffic patterns from the traffic generator. The default patterns includesingle read/write, byte-enabled read/write, and block read/write. Bypass the user-configured traffic stage. Specifies to skip the stagethat uses the user-defined test bench file to configure the traffic generatorin simulation. Bypass the traffic generator repeated-writes/repeated-reads testpattern. Bypasses the traffic generator's repeat test stage, which causesevery write and read to be repeated several times. Bypass the traffic generator stress pattern. Bypasses a test stageintended to stress-test signal integrity and memory interface calibration. Export Traffic Generator configuration interface. Instantiates aport for traffic generator configuration. Use this port if the traffic generatoris to be configured by user Click Generate Example Design to generate the EMIF IP, including the TrafficGenerator design, with the traffic pattern that you have : If you click the Generate HDL option instead, the Traffic Generator is not included in the generated Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide452Figure the Traffic Generator in the Parameter Configurable Traffic Generator Configuration OptionsThe EMIF Configurable Traffic Generator offers a range of configuration options forfast debugging of your external memory interface. You configure the traffic generatorby modifying address-mapped registers through the simulation test bench file or bycreating a configuration test SyntaxThe test bench includes an example test syntax for writing to a configuraton register is as follows:tg_send_cfg_write_<index>(<Register Name>, <Value to bewritten>);The index value represents the index of the memory interface (which is usually 0, butcan be 0/1 in ping-pong PHY mode).The register name values are listed in the tables of configuration options, and can alsobe found in the file, in the same directory as thetest final configuration command must be a write of any value to TG_START, whichstarts the traffic generator for the specified OptionsConfiguration options are divided into read/write, address, data, and data maskgeneration Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide453Table Options for Read/Write GenerationToolkit GUI TabToolkit GUI ParameterRegister NameDescription----TG_STARTTells the system to perform a writeto this register to initiate trafficgeneration the number of read/writeloops to perform before completionof the test stage. A loop is a singleiteration of writes and reads. Uponcompletion, the base address iseither incremented (SEQ orRAND_SEQ) or replaced by anewly generated random address(RAND or RAND_SEQ).Writes per blockTG_WRITE_COUNTSpecifies the number of writes tobe performed in each loop of per blockTG_READ_COUNTSpecifies the number of reads tobe performed in each loop of thetest. This register must have thesame value as the number of times eachwrite transaction is the number of times eachread transaction is per blockTG_BURST_LENGTHConfigures the length of eachwrite/read burst to the record of first failureoccurrence. New failureinformation such as expected data,read data, and fail address, iswritten to the correspondingregisters following the next the byte-enable (datamask enable) register within thetraffic generator which allows thecurrent test to use the source of data usedfor data signal generation duringthe test. Set to 0 to use pseudo-random data. Set to 1 to use user-specified values stored in the staticdata the source of data usedfor byte-enable signal generationduring the test. Set to 0 to usepseudo-random data. Set to 1 touse user-specified values stored inthe static data Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide454Table Options for Address GenerationToolkit GUI TabToolkit GUI ParameterRegister NameDescriptionAddressStart AddressTG_SEQ_START_ADDR_WR_LSpecifies the sequential startaddress (lower 32 bits).Start addressTG_SEQ_START_ADDR_WR_HSpecifies the sequential startaddress (upper 32 bits)Address modeTG_ADDR_MODE_WRSpecifies how write addresses aregenerated by writing the value inparentheses to the registeraddress. Values are: randomizethe address for every write (0),increment sequentially from aspecified address (1), incrementsequentially from a randomaddress (2), or perform one hotaddressing (3).Number of sequentialaddressTG_RAND_SEQ_ADDRS_WRSpe cifies the number of times toincrement sequentially on therandom base address beforegenerating a new random to start addressTG_RETURN_TO_START_ADDRReturn to start address indeterministic sequential addressmode (if 1 is written toTG_ADDR_MODE_WR) after everyloop of | Mask ModeTG_RANK_MASK_ENSpecifies the rank masking modeby writing the value in parenthesesto the register address. Valuesare: disable rank masking (0),maintain a static rank mask (1),cycle through rank masksincrementally (2).Bank Address | Mask ModeTG_BANK_MASK_ENSpecifies the bank masking modeby writing the value in parenthesesto the register address. Valuesare: disable bank masking (0),maintain a static bank mask (1),cycle through bank masksincrementally (2), cycle throughonly three consecutive bank masks(3).Row | Mask ModeTG_ROW_MASK_ENSpecifies the mode for rowmasking by writing the value inparentheses to the registeraddress. Values are: disable rowmasking (0), maintain a static rowmask (1), cycle through rowmasks incrementally (2).Bank Group | Mask ModeTG_BG_MASK_ENSpecifies the mode for bank groupmasking by writing the value inparentheses to the registeraddress. Values are: disable bankgroup masking (0), maintain astatic bank group mask (1), cyclethrough bank group masksincrementally (2).Rank | Mask ValueTG_RANK_MASKSpecifies the initial rank to bemasked into the generated trafficgenerator 13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide455Toolkit GUI TabToolkit GUI ParameterRegister NameDescriptionBank Address | Mask ValueTG_BANK_MASKSpecifies the initial bank to bemasked into the generated trafficgenerator | Mask ValueTG_ROW_MASKSpecifies the initial row to bemasked into the generated trafficgenerator Group | Mask ValueTG_BG_MASKSpecifies the initial bank group tobe masked into the generatedtraffic generator AddressIncrementTG_SEQ_ADDR_INCRSpecifie s the increment to usewhen sequentially incrementingthe address. This value is used byboth deterministic sequentialaddressing and random sequentialaddressing. (Refer toTG_ADDR_MODE_WR)Start AddressTG_SEQ_START_ADDR_RD_LSpecifies the sequential start readaddress (lower 32 bits).TG_SEQ_START_ADDR_RD_HSpecifies the sequential start readaddress (upper 32 bits).Address ModeTG_ADDR_MODE_RDSimilar to TG_ADDR_MODE_WRbut for of sequentialaddressTG_RAND_SEQ_ADDRS_RDSpe cifies the number of times toincrement the random sequentialread Options for Data GenerationToolkit GUI TabToolkit GUI ParameterRegister NameDescriptionDataSeed/Fixed PatternTG_DATA_SEEDSpecifies an initial value to the datagenerator corresponding to theindex and Fixed Patternradio buttonsTG_DATA_MODESpecifies whether to treat the initialvalue of the data generator ofcorresponding index as a seed forgenerating pseudo-random data(value of 0) or to keep the initialvalue static (value of 1).Table Options for Data Mask GenerationToolkit GUI TabToolkit GUI ParameterRegister NameDescriptionDataSeed/Fixed PatternTG_BYTEEN_SEEDSpecifies an initial value to thebyte-enable generatorcorresponding to the index and Fixed Patternradio buttonsTG_BYTEEN_MODESpecifies whether to treat theinitial value of the byte-enablegenerator of corresponding indexas a seed and generate pseudo-random data (value of 0) or tokeep the initial value static (valueof 1). Test InformationIn the test bench file, register reads are encoded in a similar syntax to register Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide456The following example illustrates the syntax of a register read:integer <Variable Name>;tg_send_cfg_read_<index>(<Register Name>, <Variable Name>);In hardware, you can probe the registers storing the test information (such as pnfper bit persist, first fail read address, first fail read data, andfirst fail expected data).Table Information Read-Accessible Through Register AddressesRegister NameDescriptionTG_PASSReturns a high value if the traffic generator passes at theend of all the test a high value if the traffic generator fails at the endof all the test the failure count (lower 32 bits).TG_FAIL_COUNT_HReports the failure count(upper 32 bits).TG_FIRST_FAIL_ADDR_LReports the address of the first failure (lower 32 bits).TG_FIRST_FAIL_ADDR_HReports the address of the first failure (upper 32 bits).TG_FIRST_FAIL_IS_READFirst failure is Read failure is Write the traffic generator version the number of data the number of byte-enable the rank address the bank address the row address the bank group the width of all data and PNF signals within thetraffic the length of the static pattern to be loaded intostatic per-pin data the length of the static pattern to be loaded intostatic per-pin byte-enable the minimum address increment permitted forsequential and random-sequential address error bits. Refer to Error Report Register Bits the persistent PNF per bit as an array of the first failure expected data. This is read as anarray of 32-bit the first failure read data. This is read as an arrayof 32-bit Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide457The configuration error report register contains information on commonmisconfigurations of the traffic generator. The bit corresponding to a givenconfiguration error is set high when that configuration error is detected. Ensure thatall bits in this register are low, to avoid test failures or unexpected behavior due toimproper Report Register BitsBit Index (LSB = 0x0)Bit NameDescription of Error0ERR_MORE_READS_THAN_WRITESYou have requested more readtransactions per loop than writetransactions per configured burst length is greaterthan the configured sequential addressincrement when address generation isin sequential or random configured sequential addressincrement is less than the minimumrequired address increment whenaddress generation is in sequential orrandom sequential configured sequential addressincrement is not a multiple of theminimum required address incrementwhen address generation is insequential or random sequential configured start addresses forreads and writes are different whenaddress generation is in configured address modes forreads and writes are configured number of randomsequential addresses for reads andwrites are different when addressgeneration is in random number of read and/or writerepeats is set to burst length is set greater than 1and read/write requests are set greaterthan Running the Traffic Generator can use the EMIF Debug Toolkit to configure the traffic generator infrastructure tosend custom traffic patterns to the the EMIF Debug Toolkit by selecting Tools System Debugging Tools External Memory Interface After you launch the toolkit, you must establish the following connections, beforerunning the custom traffic generator:13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide458 Initialize Connections Link Project to Device Connections Create Memory Interface Connection Create Traffic Generator the Traffic Generator by selecting Traffic Generator Settings RunCustom Traffic Understanding the Custom Traffic Generator User InterfaceThe Custom Traffic Generator interface lets you configure data patterns, the bytes tobe enabled, the addressing mode, and the order in which traffic is interface has three tabs: Data tab Address tab Loops tabData TabThe Data tab is divided into Data Pins and Data Mask Pins Tab13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide459The Data Pins section helps with customizing the patterns selected for the data can choose between two options for Data Mode: PRBS The default write data to all the data pins. Fixed Pattern Lets you specify a pattern to be written to the the All Pins option when you want to write the same data pattern to all thedata pins. If data must be individually assigned to the data pins, you must enter thedata value for each individual pin. The width of the data entered is based on theAVL_TO_DQ_WIDTH_RATIO, which is based on the ratio of the memory clock to theuser data bytes are enabled by default; the Data Mask Pins section lets you disableany of the bytes if you want to. To disable data bytes individually, select Test can choose between two options for Data Mode: PRBS Specifies the PRBS pattern to enable or disable data bytes. A 1 denotes adata byte enabled, while a 0 denotes a data byte being masked or disabled. Fixed Pattern Lets you enable or disable individual bytes. You can apply byteenables to all pins or to individual bytes. A 1 denotes a data byte enabled, while a0 denotes a data byte being masked or TabThe Address tab lets you configure sequential, random, or random sequential (wherethe initial start address is random, but sequential thereafter) addressing schemes. TheAddress tab is divided into Address Mode and Address Configuration Tab13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide460The Address Mode section lets you specify the pattern of addresses generated toaccess the memory. You can choose between three address modes : Sequential Each address is incremented by the Sequential address incrementvalue that you specify. You also specify the Start Address from which theincrements begin. Random Each address is generated randomly. (You set the number of randomaddresses on the Loops tab.) Random Sequential Each address is generated randomly, and then incrementedsequentially. You specify the number of sequential increments in the Number ofsequential addresses Address Configuration section contains the settings with which you configurethe address mode that you chose in the Address Mode section. The following settingsare available: Start address Specifies the starting address for Sequential Address Mode. Themaximum address value that can be reached is 1FF_FFFF. (The Traffic will accept higher values, but wraps back to 0 after the maximum value hasbeen reached.) The Start address setting applies only to Sequential AddressMode. Number of sequential addresses Specifies the number of sequential addressesgenerated after the first random address generated. This setting applies only inRandom sequential mode. Sequential address increment Specifies the size of increment between eachaddress in the Sequential address mode and Random sequential addressmode. Return to start address Specifies that the address value generated return backto the value entered in the Start Address field, after a block of transactions tothe memory has completed. This setting applies only to Sequential addressmode. Address masking Masking provides additional options for exploring certainspecific address spaces in memory: Disabled does not enable masking, and increments address based on theselected Address Mode. Fixed cycling allows you to restrict the addressing to a specific row or aspecific bank, which you can specify in the corresponding Mask Value TabThe Loops tab lets you order the transactions to the memory as desired. A unit size oftransactions to the memory is defined as a block; a block includes a set of writetransaction(s) immediately followed by a set of read transaction(s).13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide461Figure Tab13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide462The Loops tab provides the following configuration options: Loops Specifies the number of blocks of transactions to be sent to the option helps to extend the range of addresses that the controller can address range is incremented as each loop is executed, unless you specifyReturn to Start Address, which causes each loop to begin from the same startaddress. The range of supported values for the Loops option is from 1 to 4095. Writes per block Specifies the size of the block (that is, the number ofconsecutive write operations that can be issued in a single block). The range ofvalues for this option is as follows: When address masking is disabled, the number of writes per block supportedis 1 to 4094. When address masking is enabled, the maximum number of writes issuedinside a block is 255. Reads per block Specifies the number of consecutive read operations that can beissued in a single block, immediately following the consecutive writes issued. Thenumber of reads per block should be identical to the number of writes per block,because data mismatches can occur when the two values are not identical. Therange of values for this option is as follows: When address masking is disabled, the number of reads per block supported is1 to 4094. When address masking is enabled, the maximum number of reads issuedinside a block is 255. Write repeats Specifies the number of times each write command is issued inrepetition to the same address. A maximum number of 255 repeat writetransactions can be issued. The repeat writes are issued immediately after the firstwrite command has been issued. Read repeats Specifies the number of times each read command is issued inrepetition to the same address. A maximum number of 255 repeat readtransactions can be issued. The repeat reads are issued immediately after the firstread command has been issued. Avalon burst length Specifies the length of each Avalon burst. The value of thisfield should be less than the Sequential address increment specified on theAddress tab. The number of write and read repeats default to 1 if the Avalonburst length is greater than Applying the Traffic Generator can apply the Traffic Generator to run stress tests, debug your hardwareplatform for signal integrity problems, and to emulate actual memory topic presents some common applications where you can benefit by using theTraffic Generator Signal Integrity with PRBS Data PatternYou can apply PRBS data to the data pins to help emulate an actual traffic pattern tothe memory interface. The traffic generator uses a PRBS7 data pattern as the defaulttraffic pattern on the data pins, and can support PRBS-15 and Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide463Debugging and Monitoring an Address for Reliable Data CaptureYou can send a single write followed by multiple reads to a specific address to helpdebug and monitor a specific address for reliable data capture. You can do this withthe following settings: Writes per block: 1 Reads per block: 1 Write repeats: 1 Read repeats: 1 to 255Figure the Loops Tab for a Single Write Followed by Multiple ReadsIf you specify a Loops value greater than 1, every block of write and multiple readtransactions will follow the same pattern. If there is a specific address to which thistransaction must be issued, you should specify that address in the Start address fieldon the Address tab, with the Sequential address mode Large Sections of MemoryThe maximum number of unique addresses that can be written to in one block is4094. Using the maximum Loops value of 4095, the address range that can besupported in one test is equal to the number of loops multiplied by the number ofwrites per block. Further address expansion can be achieved by changing the Startaddress value appropriately and reissuing the continue addressing sections of the memory beyond the address range that can bespecified in one set of toolkit configurations, you can incrementally access the next setof addresses in the memory by changing the Start address example, in a memory where row address width is 15, bank address width is 3and column address width is 10, the total number of address locations to be accessedis: 2 (row address width) x (bank address width x 2 (column address width)). Themaximum number of address locations that can be accessed is limited by the width ofthe internal address bus, which is 25 bits the example described above, you must set the following values on the Addresstab: Select the Sequential address mode. Set the Start address to 0x00. Ensure that you do not select Return to start addess. Ensure that you disable address masking for rank, row, bank, and bank Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide464Figure Configuration to Access the First Set of AddressesYou must also set the following values on the Loops tab: Set Loops to the maximun value of 4095. Set Writes per block to the maximum value of 4094. Set Reads per block to the maximum value of 4094. Set Write repeats to 1. Set Read repeats to Configuration to Access the First Set of AddressesEach iteration can access a maximum of 4095 x 4094 locations (16,764,930 addresslocations Address ranging from 000_0000 h to FF_D001 h). To access the next4095 x 4094 locations, the same settings as above must be repeated, except for theStart address value, whichmust be set to a hex value of 16,764,931 same process can be repeated to further access memory locations inside thememory. The maximum value supported is 25 h 1FF_FFFF which is the equivalent of33,554,432 locations inside the Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide465Figure Configuration to Access the Second Set of Testing the EMIF Interface Using the Traffic Generator EMIF Configurable Traffic Generator can assist in debugging and stress-testingyour external memory FeaturesThe traffic generator has the following key features: Is a standalone, soft-logic device that resides in the FPGA core. Is independent of the FPGA architecture and the external memory protocol in use. Offers configuration options for the generation of reads and writes, addressing,data, and data Test InformationIn the test bench file, register reads are encoded in a similar syntax to register following example illustrates the syntax of a register read:integer <Variable Name>;tg_send_cfg_read_<index>(<Register Name>, <Variable Name>);In hardware, you can probe the registers storing the test information (such as pnfper bit persist, first fail read address, first fail read data, andfirst fail expected data).Table Information Read-Accessible Through Register AddressesRegister NameDescriptionTG_PASSReturns a high value if the traffic generator passes at theend of all the test a high value if the traffic generator fails at the endof all the test 13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide466Register NameDescriptionTG_FAIL_COUNT_LReports the failure count (lower 32 bits).TG_FAIL_COUNT_HReports the failure count(upper 32 bits).TG_FIRST_FAIL_ADDR_LReports the address of the first failure (lower 32 bits).TG_FIRST_FAIL_ADDR_HReports the address of the first failure (upper 32 bits).TG_FIRST_FAIL_IS_READFirst failure is Read failure is Write the traffic generator version the number of data the number of byte-enable the rank address the bank address the row address the bank group the width of all data and PNF signals within thetraffic the length of the static pattern to be loaded intostatic per-pin data the length of the static pattern to be loaded intostatic per-pin byte-enable the minimum address increment permitted forsequential and random-sequential address error bits. Refer to Error Report Register Bits the persistent PNF per bit as an array of the first failure expected data. This is read as anarray of 32-bit the first failure read data. This is read as an arrayof 32-bit configuration error report register contains information on commonmisconfigurations of the traffic generator. The bit corresponding to a givenconfiguration error is set high when that configuration error is detected. Ensure thatall bits in this register are low, to avoid test failures or unexpected behavior due toimproper Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide467Table Report Register BitsBit Index (LSB = 0x0)Bit NameDescription of Error0ERR_MORE_READS_THAN_WRITESYou have requested more readtransactions per loop than writetransactions per configured burst length is greaterthan the configured sequential addressincrement when address generation isin sequential or random configured sequential addressincrement is less than the minimumrequired address increment whenaddress generation is in sequential orrandom sequential configured sequential addressincrement is not a multiple of theminimum required address incrementwhen address generation is insequential or random sequential configured start addresses forreads and writes are different whenaddress generation is in configured address modes forreads and writes are configured number of randomsequential addresses for reads andwrites are different when addressgeneration is in random number of read and/or writerepeats is set to burst length is set greater than 1and read/write requests are set greaterthan Performing Your Own Tests Using Traffic Generator you want, you can create your own configuration test stage for the EMIFConfigurable Traffic general flow of a configuration test stage, including the default test stages, is asfollows: Configure the number of loops to be completed by the traffic generator(TG_LOOP_COUNT). Configure the number of writes and reads to be complete per loop(TG_WRITE_COUNT and TG_READ_COUNT respectively). Choose the burst length of each write and read (TG_BURST_LENGTH). Select starting write address by writing to the lower and upper bits of the addressregister (TG_SEQ_START_ADDR_WR_L and TG_SEQ_START_ADDR_WR_H,respectively).13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide468 Select write address generation mode (TG_ADDR_MODE_WR). Select starting read address by writing to the lower and upper bits of the addressregister (TG_SEQ_START_ADDR_RD_L and TG_SEQ_START_ADDR_RD_H,respectively). Select read address generation mode (TG_ADDR_MODE_RD). If applicable, select sequential address increment (TG_SEQ_ADDR_INCR). Write initial values/seeds to the data and byte-enable generators (TG_DATA_SEEDand TG_BYTEEN_SEED). Select generation mode of the data and byte-enable generators (TG_DATA_MODEand TG_BYTEEN_MODE). Initiate test (TG_START).SimulationFor a comprehensive example of how to write your own configuration test forsimulation, refer to the test bench file, located at<example_design_directory>/sim/ed_sim/altera_emif_tg_avl_2_<>/ iterate over the data generators or byte-enable generators, you must read thenumber of data generators and number of byte-enable generators. These values aremapped to read-accessible registers TG_NUM_DATA_GEN and TG_NUM_BYTEEN_GEN,respectively. The following example illustrates how one would configure the datagenerators to continuously output the pattern 0x5a, using the simulation test bench:integer num_data_generators; ... tg_send_cfg_read_0(TG_NUM_DATA_GEN, num_data_generators); tg_send_cfg_write_0(TG_DATA_MODE, 32'h1); for (i = 0; i < num_data_generators; i = i + 1) begin tg_send_cfg_write_0(TG_DATA_SEED + i, 32'h5A); endHardwareConfiguration test stages in hardware must be inserted into the RTL, and will resemblethe single read/write, byte-enable, and block read/write stages in the default testpattern. In most cases, you can modify one of the existing stages to create thedesired custom test stage. The stages are linear, finite, state machines that writepredetermined values to the configuration address-mapped registers. As always, thelast state in configuration is a write to address 0x0 or TG_START. The state machinethen waits for the traffic generator to return a signal signifying its completion of thetest to the aforementioned default test stages as examples of hardware test default test stages are contained within the following files: <example_design_directory>/qii/ed_synth/altera_emif_tg_avl_2_<>/ <example_design_directory>/qii/ed_synth/altera_emif_tg_avl_2_<>/ Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide469You can also configure the configurable traffic generator in real time using the EMIFDebug Toolkit. The configuration settings available in the Toolkit interface are detailedin the Configurable Traffic Generator Configuration Options Signal Splitter ComponentThe signal splitter (altera_emif_sig_splitter) is an internal IP component whichreceives a single signal as its input and passes that signal directly to n outputs, wheren is an interger value equal to or greater than signal splitter is useful becausePlatform Designer does not directly allow one-to-many connections for signal splitter contains no logic or memory elements. When you configure thesignal splitter to have exactly one output port, it is functionally identical to a singlewire, and can be replaced by one with no loss of rzq_splitter is an instantiation of the signal splitter component specifically forthe RZQ signal. The signal splitter facilitates the sharing of one RZQ signal amongmultiple memory interfaces in an EMIF example The Traffic Generator ReportThe traffic generator report provides information about the configuration of the TrafficGenerator and the result of the most recent run of the Traffic Generator ReportThe traffic generator report contains the following information: A Pass flag value of 1 indicates that the run completed with no errors. A Fail flag value of 1 indicates that the run encountered one or more errors. The Failure Count indicates the number of read transactions where data did notmatch the expected value. The First failure address indicates the address corresponding to the first datamismatch. The Version indicates the version number of the traffic generator. The Number of data generators indicates the number of data pins at thememory interface. The Number of byte enable generators indicates the number of byte enableand data mask pins at the memory interface. The Rank Address, Bank address, and Bank group width values indicate thenumber of bits in the Avalon address corresponding to each of those components. The Data/Byte enable pattern length indicates the number of bits in the fixedpattern used on each data/byte enable pin. The PNF (pass not fail) value indicates the persistent pass/fail status for each bitin the Avalon data. It is also presented on a per-memory-pin basis for each beatwithin a memory burst. Fail Expected Data is the data that was expected on the first failing transaction(if applicable). Fail Read Data is the data that was received on the first failing transaction (ifapplicable).13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Calibration Adjustment Delay Step Sizes for Intel Stratix 10DevicesRefer to the following tables for information on delay step sizes for AddressingEach reconfigurable feature of the interface has an associated memory address;however, this address is placement dependent. If Altera PHYLite for Parallel InterfacesIP cores and the Intel Stratix 10 External Memory Interfaces IP cores share the sameI/O column, you must track the addresses of the interface lanes and the is done at the 32-bit word boundary, where avl_address[1:0] are MapThese points apply to the following table: id[3:0] refers to the Interface ID parameter. lane_addr[7:0] refers to the address of a given lane in an interface. The Fittersets this address value. You can query this in the Parameter Table LookupOperation Sequence as described in Address Lookup section of the Intel PHYLitefor Parallel Interfaces IP Core User Guide. pin[4:0] refers to the physical location of the pin in a lane. You can use theFitter to automatically determine a pin location or you can manually set the pinlocation through .qsf assignment. Refer to the Parameter Table Lookup OperationSequence as described in Address Lookup section of the Intel PHYLite for ParallelInterfaces IP Core User Guide for more Address R/WAddress CSR RControlValueFieldRangePin Output Phase{id[3:0],3'h4,lane_addr[7:0],pin{4: 0],8'D0}{id[3:0],3'h4,lane_addr[7:0],pin {4:0],8'E8} Setting: Referto Table 452 on page 474Maximum Setting: Referto Table 452 on page 474Incremental Delay:1/128th VCO clock periodNote: The pin outputphase switchesfrom the CSRvalue to theAvalon value afterthe first Avalonwrite. It is onlyreset to the CSRvalue on a resetof the Pin PVTCompensatedInput Delay{id[3:0],3'h4,lane_addr[7:0],Not Setting: 0Maximum Setting: 511VCO clock 13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide471FeatureAvalon Address R/WAddress CSR RControlValueFieldRange4'hC,lgc_sel[1:0] ,pin_off[2:0],4'h0} lgc_sel[1:0] is: 2'b01 for DQ[5:0] 2'b10 for DQ[11:6] pin_off[2:0] : 3'h0: DQ [0],DQ [6] 3 h1: DQ [1],DQ [7] 3 h2: DQ [2],DQ [8] 3 h3: DQ [3],DQ [9] 3 h4: DQ [4],DQ [10] 3 h5: DQ [5],DQ [11]Incremental Delay:1/256th VCO clock Enable120 = Delay value is = Select delay valuefrom Avalon Strobe PVTcompensatedinput delay 2{id[3:0],3'h4,lane_addr[7:0],4'hC,lgc_s el[1:0],3'h6,4'h0} lgc_sel[1:0] =2'b01Not Setting: 0Maximum Setting: 1023VCO clock periodsIncremental Delay:1/256th VCO clock Enable120 = Select delay valuefrom CSR register. TheCSR value is set throughthe Capture StrobePhase Shift parameterduring IP = Select delay valuefrom Avalon Strobe enablephase 2{id[3:0],3'h4,lane_addr[7:0],4'hC,lgc_s el[1:0],3'h7,4'h0} lgc_sel[1:0] =2'b01{id[3:0],3'h4,lane_addr[7:0],4'hC, 9'h198} Setting: Referto Table 452 on page 474Maximum Setting: Referto Table 452 on page 474Incremental Delay:1/128th VCO clock Enable150 = Select delay valuefrom CSR register1 = Select delay valuefrom Avalon 13 Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide472FeatureAvalon Address R/WAddress CSR RControlValueFieldRangeStrobe enabledelay 2{id[3:0],3'h4,lane_addr[7:0],4'hC,9'h00 8}{id[3:0],3'h4,lane_addr[7:0],4'hC,9'h1 A8} Setting: 0external clock cyclesMaximum Setting: 63external memory clockcyclesIncremental Delay: 1external memory Enable150 = Select delay valuefrom CSR register1 = Select delay valuefrom Avalon Read valid delay2{id[3:0],3'h4,lane_addr[7:0],4'hC, 9'h00C}{id[3:0],3'h4,lane_addr[7:0],4'hC ,9'h1A4} Setting: 0external clock cyclesMaximum Setting: 127external memory clockcyclesIncremental Delay: 1external memory Enable150 = Select delay valuefrom CSR register1 = Select delay valuefrom Avalon Internal VREFCode{id[3:0],3'h4,lane_addr[7:0],4'h C,9'h014}Not to Calibrated VREFSettings in the IntelPHYLite for ParallelInterfaces IP Core 9 1. Reserved bit ranges must be Modifying these values must be done on all lanes in a : For more information about performing various clocking and delay calculations,depending on the interface frequency and rate, refer to Output and Strobe Enable Minimum and Maximum Phase SettingsWhen dynamically reconfiguring the interpolator phase settings, the values must bekept within the ranges below to ensure proper operation of the Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide473Table and Strobe Enable Minimum and Maximum Phase SettingsVCOMultiplicationFactorCore RateMinimum Interpolator PhaseMaximum InterpolatorPhaseOutputBidirectionalBidi rectional withOCT Enabled1Full0x0800x1000x1000xA80Half0x08 00x1000x1000xBC0Quarter0x0800x1000x1000x A002Full0x0800x1000x1800x1400Half0x0800x 1000x1800x1400Quarter0x0800x1000x1800x14 004Full0x0800x1000x2800x1FFFHalf0x0800x1 000x2800x1FFFQuarter0x0800x1000x2800x1FF F8Full0x0800x1000x4800x1FFFHalf0x0800x10 00x4800x1FFFQuarter0x0800x1000x4800x1FFF For more information about performing various clocking and delay calculations,depending on the interface frequency and rate, refer to Intel Stratix 10 EMIF IP DebuggingUG-S10EMI | Stratix 10 External Memory Interfaces IP User Guide47414 Document Revision History for Intel Stratix 10External Memory Interfaces IP User GuideTable Revision HistoryDateVersionChangesNovember Entire document extensively restructured and revised, consolidating relevantcontent from the External Memory Interface Handbook. Created End-User Signals chapter, comprising interface and signal descriptions,AFI signals and timing diagrams, and memory-mapped register (MMR)information. Created protocol-specific chapters consolidating parameter descriptions, boardskew equations, pin planning information, and board design guidelines for eachmemory protocol. Created chapters for Timing Closure, Optimizing Controller Performance, Updated the topics in the I/O Column section. Updated DQ and DQS Pins Assignment section with new pin information. Updated the Placement Guidelines section with more detailed description. Updated the Resource Sharing Guidelines for Intel Stratix 10EMIF IP section. Updated the Parameterizing Intel Stratix 10 External Memory Interface IPsection. Updated the Parameterizing Altera PHYLite for Parallel Interfaces IP Coresection. Added a topic about OCT in the Altera PHYLite for Parallel Interfaces IP CoreReferences section. Added a note that you can only use the Report DDR function if you enable thedynamic reconfiguration feature. The dynamic reconfiguration feature is notavailable with the current version of the Altera PHYLite for Parallel Interfaces Initial | Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2008Registered

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